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a65191c27a40ded62cb22879b2df5ea93f3e0223
[microwatt.git] / soc.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
5 use std.textio.all;
6 use std.env.stop;
7
8 library work;
9 use work.common.all;
10 use work.wishbone_types.all;
11
12
13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
14 --
15 -- Main bus:
16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
17 -- 0x40000000: DRAM (when present)
18 -- 0x80000000: Block RAM (aliased & repeated)
19
20 -- IO Bus:
21 -- 0xc0000000: SYSCON
22 -- 0xc0002000: UART0
23 -- 0xc0003000: UART1 (if any)
24 -- 0xc0004000: XICS ICP
25 -- 0xc0005000: XICS ICS
26 -- 0xc0006000: SPI Flash controller
27 -- 0xc0007000: GPIO controller
28 -- 0xc0008000: USB UART (valentyusb)
29 -- 0xc8nnnnnn: External IO bus
30 -- 0xf0000000: Flash "ROM" mapping
31 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
32
33 -- External IO bus:
34 -- 0xc8000000: LiteDRAM control (CSRs)
35 -- 0xc8020000: LiteEth CSRs (*)
36 -- 0xc8030000: LiteEth MMIO (*)
37 -- 0xc8040000: LiteSDCard CSRs
38
39 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
40 -- are actually decoded as a single wishbone which LiteEth will
41 -- internally split based on bit 16.
42
43 -- (**) DRAM init code is currently special and goes to the external
44 -- IO bus, this will be fixed when it's moved out of litedram and
45 -- into the main SoC once we have a common "firmware".
46
47 -- Interrupt numbers:
48 --
49 -- 0 : UART0
50 -- 1 : Ethernet
51 -- 2 : UART1
52 -- 3 : SD card
53 -- 4 : GPIO
54 -- 5 : UARTUSB
55
56 entity soc is
57 generic (
58 MEMORY_SIZE : natural;
59 RAM_INIT_FILE : string;
60 CLK_FREQ : positive;
61 SIM : boolean;
62 HAS_FPU : boolean := true;
63 HAS_BTC : boolean := true;
64 HAS_SHORT_MULT : boolean := false;
65 DISABLE_FLATTEN_CORE : boolean := false;
66 HAS_DRAM : boolean := false;
67 DRAM_SIZE : integer := 0;
68 DRAM_INIT_SIZE : integer := 0;
69 HAS_SPI_FLASH : boolean := false;
70 SPI_FLASH_DLINES : positive := 1;
71 SPI_FLASH_OFFSET : integer := 0;
72 SPI_FLASH_DEF_CKDV : natural := 2;
73 SPI_FLASH_DEF_QUAD : boolean := false;
74 SPI_BOOT_CLOCKS : boolean := true;
75 LOG_LENGTH : natural := 512;
76 HAS_LITEETH : boolean := false;
77 UART0_IS_16550 : boolean := true;
78 HAS_UART1 : boolean := false;
79 HAS_UARTUSB : boolean := false;
80 ICACHE_NUM_LINES : natural := 64;
81 ICACHE_NUM_WAYS : natural := 2;
82 ICACHE_TLB_SIZE : natural := 64;
83 DCACHE_NUM_LINES : natural := 64;
84 DCACHE_NUM_WAYS : natural := 2;
85 DCACHE_TLB_SET_SIZE : natural := 64;
86 DCACHE_TLB_NUM_WAYS : natural := 2;
87 HAS_SD_CARD : boolean := false;
88 HAS_GPIO : boolean := false;
89 NGPIO : natural := 32
90 );
91 port(
92 rst : in std_ulogic;
93 system_clk : in std_ulogic;
94 clk_48 : in std_ulogic := '0';
95
96 -- "Large" (64-bit) DRAM wishbone
97 wb_dram_in : out wishbone_master_out;
98 wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
99
100 -- "Small" (32-bit) external IO wishbone
101 wb_ext_io_in : out wb_io_master_out;
102 wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
103 wb_ext_is_dram_csr : out std_ulogic;
104 wb_ext_is_dram_init : out std_ulogic;
105 wb_ext_is_eth : out std_ulogic;
106 wb_ext_is_sdcard : out std_ulogic;
107
108 -- external DMA wishbone with 32-bit data/address
109 wishbone_dma_in : out wb_io_slave_out := wb_io_slave_out_init;
110 wishbone_dma_out : in wb_io_master_out := wb_io_master_out_init;
111
112 -- External interrupts
113 ext_irq_eth : in std_ulogic := '0';
114 ext_irq_sdcard : in std_ulogic := '0';
115
116 -- UART0 signals:
117 uart0_txd : out std_ulogic;
118 uart0_rxd : in std_ulogic := '0';
119
120 -- UART1 signals:
121 uart1_txd : out std_ulogic;
122 uart1_rxd : in std_ulogic := '0';
123
124 -- USB signals:
125 usb_d_p : in std_ulogic := '0';
126 usb_d_n : in std_ulogic := '0';
127 usb_pullup : out std_ulogic;
128
129 -- SPI Flash signals
130 spi_flash_sck : out std_ulogic;
131 spi_flash_cs_n : out std_ulogic;
132 spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
133 spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
134 spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
135
136 -- GPIO signals
137 gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0);
138 gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0);
139 gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
140
141 -- DRAM controller signals
142 alt_reset : in std_ulogic := '0'
143 );
144 end entity soc;
145
146 architecture behaviour of soc is
147
148 -- Wishbone master signals:
149 signal wishbone_dcore_in : wishbone_slave_out;
150 signal wishbone_dcore_out : wishbone_master_out;
151 signal wishbone_icore_in : wishbone_slave_out;
152 signal wishbone_icore_out : wishbone_master_out;
153 signal wishbone_debug_in : wishbone_slave_out;
154 signal wishbone_debug_out : wishbone_master_out;
155
156 -- Arbiter array (ghdl doesnt' support assigning the array
157 -- elements in the entity instantiation)
158 constant NUM_WB_MASTERS : positive := 4;
159 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
160 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
161
162 -- Wishbone master (output of arbiter):
163 signal wb_master_in : wishbone_slave_out;
164 signal wb_master_out : wishbone_master_out;
165 signal wb_snoop : wishbone_master_out;
166
167 -- Main "IO" bus, from main slave decoder to the latch
168 signal wb_io_in : wishbone_master_out;
169 signal wb_io_out : wishbone_slave_out;
170
171 -- Secondary (smaller) IO bus after the IO bus latch
172 signal wb_sio_out : wb_io_master_out;
173 signal wb_sio_in : wb_io_slave_out;
174
175 -- Syscon signals
176 signal dram_at_0 : std_ulogic;
177 signal do_core_reset : std_ulogic;
178 signal wb_syscon_in : wb_io_master_out;
179 signal wb_syscon_out : wb_io_slave_out;
180
181 -- UART0 signals:
182 signal wb_uart0_in : wb_io_master_out;
183 signal wb_uart0_out : wb_io_slave_out;
184 signal uart0_dat8 : std_ulogic_vector(7 downto 0);
185 signal uart0_irq : std_ulogic;
186
187 -- UART1 signals:
188 signal wb_uart1_in : wb_io_master_out;
189 signal wb_uart1_out : wb_io_slave_out;
190 signal uart1_dat8 : std_ulogic_vector(7 downto 0);
191 signal uart1_irq : std_ulogic;
192
193 -- UARTUSB signals:
194 signal wb_uartusb_in : wb_io_master_out;
195 signal wb_uartusb_out : wb_io_slave_out;
196 signal uartusb_irq : std_ulogic;
197
198 -- SPI Flash controller signals:
199 signal wb_spiflash_in : wb_io_master_out;
200 signal wb_spiflash_out : wb_io_slave_out;
201 signal wb_spiflash_is_reg : std_ulogic;
202 signal wb_spiflash_is_map : std_ulogic;
203
204 -- XICS signals:
205 signal wb_xics_icp_in : wb_io_master_out;
206 signal wb_xics_icp_out : wb_io_slave_out;
207 signal wb_xics_ics_in : wb_io_master_out;
208 signal wb_xics_ics_out : wb_io_slave_out;
209 signal int_level_in : std_ulogic_vector(15 downto 0);
210 signal ics_to_icp : ics_to_icp_t;
211 signal core_ext_irq : std_ulogic;
212
213 -- GPIO signals:
214 signal wb_gpio_in : wb_io_master_out;
215 signal wb_gpio_out : wb_io_slave_out;
216 signal gpio_intr : std_ulogic := '0';
217
218 -- Main memory signals:
219 signal wb_bram_in : wishbone_master_out;
220 signal wb_bram_out : wishbone_slave_out;
221
222 -- DMI debug bus signals
223 signal dmi_addr : std_ulogic_vector(7 downto 0);
224 signal dmi_din : std_ulogic_vector(63 downto 0);
225 signal dmi_dout : std_ulogic_vector(63 downto 0);
226 signal dmi_req : std_ulogic;
227 signal dmi_wr : std_ulogic;
228 signal dmi_ack : std_ulogic;
229
230 -- Per slave DMI signals
231 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
232 signal dmi_wb_req : std_ulogic;
233 signal dmi_wb_ack : std_ulogic;
234 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
235 signal dmi_core_req : std_ulogic;
236 signal dmi_core_ack : std_ulogic;
237
238 -- Delayed/latched resets and alt_reset
239 signal rst_core : std_ulogic := '1';
240 signal rst_uart : std_ulogic := '1';
241 signal rst_xics : std_ulogic := '1';
242 signal rst_spi : std_ulogic := '1';
243 signal rst_gpio : std_ulogic := '1';
244 signal rst_bram : std_ulogic := '1';
245 signal rst_dtm : std_ulogic := '1';
246 signal rst_wbar : std_ulogic := '1';
247 signal rst_wbdb : std_ulogic := '1';
248 signal alt_reset_d : std_ulogic;
249
250 -- IO branch split:
251 type slave_io_type is (SLAVE_IO_SYSCON,
252 SLAVE_IO_UART,
253 SLAVE_IO_ICP,
254 SLAVE_IO_ICS,
255 SLAVE_IO_UART1,
256 SLAVE_IO_SPI_FLASH,
257 SLAVE_IO_GPIO,
258 SLAVE_IO_UARTUSB,
259 SLAVE_IO_EXTERNAL);
260 signal current_io_decode : slave_io_type;
261
262 signal io_cycle_none : std_ulogic;
263 signal io_cycle_syscon : std_ulogic;
264 signal io_cycle_uart : std_ulogic;
265 signal io_cycle_uart1 : std_ulogic;
266 signal io_cycle_uartusb : std_ulogic;
267 signal io_cycle_icp : std_ulogic;
268 signal io_cycle_ics : std_ulogic;
269 signal io_cycle_spi_flash : std_ulogic;
270 signal io_cycle_gpio : std_ulogic;
271 signal io_cycle_external : std_ulogic;
272
273 function wishbone_widen_data(wb : wb_io_master_out) return wishbone_master_out is
274 variable wwb : wishbone_master_out;
275 begin
276 wwb.adr := wb.adr(wb.adr'left downto 1);
277 wwb.dat := wb.dat & wb.dat;
278 wwb.sel := x"00";
279 if wb.adr(0) = '0' then
280 wwb.sel(3 downto 0) := wb.sel;
281 else
282 wwb.sel(7 downto 4) := wb.sel;
283 end if;
284 wwb.cyc := wb.cyc;
285 wwb.stb := wb.stb;
286 wwb.we := wb.we;
287 return wwb;
288 end;
289
290 function wishbone_narrow_data(wwbs : wishbone_slave_out; adr : std_ulogic_vector(29 downto 0))
291 return wb_io_slave_out is
292 variable wbs : wb_io_slave_out;
293 begin
294 wbs.ack := wwbs.ack;
295 wbs.stall := wwbs.stall;
296 if adr(0) = '0' then
297 wbs.dat := wwbs.dat(31 downto 0);
298 else
299 wbs.dat := wwbs.dat(63 downto 32);
300 end if;
301 return wbs;
302 end;
303
304 -- This is the component exported by the 16550 compatible
305 -- UART from FuseSoC.
306 --
307 component uart_top port (
308 wb_clk_i : in std_ulogic;
309 wb_rst_i : in std_ulogic;
310 wb_adr_i : in std_ulogic_vector(2 downto 0);
311 wb_dat_i : in std_ulogic_vector(7 downto 0);
312 wb_dat_o : out std_ulogic_vector(7 downto 0);
313 wb_we_i : in std_ulogic;
314 wb_stb_i : in std_ulogic;
315 wb_cyc_i : in std_ulogic;
316 wb_ack_o : out std_ulogic;
317 int_o : out std_ulogic;
318 stx_pad_o : out std_ulogic;
319 srx_pad_i : in std_ulogic;
320 rts_pad_o : out std_ulogic;
321 cts_pad_i : in std_ulogic;
322 dtr_pad_o : out std_ulogic;
323 dsr_pad_i : in std_ulogic;
324 ri_pad_i : in std_ulogic;
325 dcd_pad_i : in std_ulogic
326 );
327 end component;
328
329 constant UART0_IS_POTATO : boolean := not UART0_IS_16550;
330 begin
331
332 resets: process(system_clk)
333 begin
334 if rising_edge(system_clk) then
335 rst_core <= rst or do_core_reset;
336 rst_uart <= rst;
337 rst_spi <= rst;
338 rst_xics <= rst;
339 rst_gpio <= rst;
340 rst_bram <= rst;
341 rst_dtm <= rst;
342 rst_wbar <= rst;
343 rst_wbdb <= rst;
344 alt_reset_d <= alt_reset;
345 end if;
346 end process;
347
348 -- Processor core
349 processor: entity work.core
350 generic map(
351 SIM => SIM,
352 HAS_FPU => HAS_FPU,
353 HAS_BTC => HAS_BTC,
354 HAS_SHORT_MULT => HAS_SHORT_MULT,
355 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
356 ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
357 LOG_LENGTH => LOG_LENGTH,
358 ICACHE_NUM_LINES => ICACHE_NUM_LINES,
359 ICACHE_NUM_WAYS => ICACHE_NUM_WAYS,
360 ICACHE_TLB_SIZE => ICACHE_TLB_SIZE,
361 DCACHE_NUM_LINES => DCACHE_NUM_LINES,
362 DCACHE_NUM_WAYS => DCACHE_NUM_WAYS,
363 DCACHE_TLB_SET_SIZE => DCACHE_TLB_SET_SIZE,
364 DCACHE_TLB_NUM_WAYS => DCACHE_TLB_NUM_WAYS
365 )
366 port map(
367 clk => system_clk,
368 rst => rst_core,
369 alt_reset => alt_reset_d,
370 wishbone_insn_in => wishbone_icore_in,
371 wishbone_insn_out => wishbone_icore_out,
372 wishbone_data_in => wishbone_dcore_in,
373 wishbone_data_out => wishbone_dcore_out,
374 wb_snoop_in => wb_snoop,
375 dmi_addr => dmi_addr(3 downto 0),
376 dmi_dout => dmi_core_dout,
377 dmi_din => dmi_dout,
378 dmi_wr => dmi_wr,
379 dmi_ack => dmi_core_ack,
380 dmi_req => dmi_core_req,
381 ext_irq => core_ext_irq
382 );
383
384 -- Wishbone bus master arbiter & mux
385 wb_masters_out <= (0 => wishbone_dcore_out,
386 1 => wishbone_icore_out,
387 2 => wishbone_widen_data(wishbone_dma_out),
388 3 => wishbone_debug_out);
389 wishbone_dcore_in <= wb_masters_in(0);
390 wishbone_icore_in <= wb_masters_in(1);
391 wishbone_dma_in <= wishbone_narrow_data(wb_masters_in(2), wishbone_dma_out.adr);
392 wishbone_debug_in <= wb_masters_in(3);
393 wishbone_arbiter_0: entity work.wishbone_arbiter
394 generic map(
395 NUM_MASTERS => NUM_WB_MASTERS
396 )
397 port map(
398 clk => system_clk,
399 rst => rst_wbar,
400 wb_masters_in => wb_masters_out,
401 wb_masters_out => wb_masters_in,
402 wb_slave_out => wb_master_out,
403 wb_slave_in => wb_master_in
404 );
405
406 -- Snoop bus going to caches.
407 -- Gate stb with stall so the caches don't see the stalled strobes.
408 -- That way if the caches see a strobe when their wishbone is stalled,
409 -- they know it is an access by another master.
410 process(all)
411 begin
412 wb_snoop <= wb_master_out;
413 if wb_master_in.stall = '1' then
414 wb_snoop.stb <= '0';
415 end if;
416 end process;
417
418 -- Top level Wishbone slaves address decoder & mux
419 --
420 -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
421 -- 0000 - BRAM
422 -- 0001 - DRAM
423 -- 01xx - DRAM
424 -- 10xx - BRAM
425 -- 11xx - IO
426 --
427 slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
428 type slave_top_type is (SLAVE_TOP_BRAM,
429 SLAVE_TOP_DRAM,
430 SLAVE_TOP_IO);
431 variable slave_top : slave_top_type;
432 variable top_decode : std_ulogic_vector(3 downto 0);
433 begin
434 -- Top-level address decoder
435 top_decode := wb_master_out.adr(28 downto 26) & dram_at_0;
436 slave_top := SLAVE_TOP_BRAM;
437 if std_match(top_decode, "0000") then
438 slave_top := SLAVE_TOP_BRAM;
439 elsif std_match(top_decode, "0001") then
440 slave_top := SLAVE_TOP_DRAM;
441 elsif std_match(top_decode, "01--") then
442 slave_top := SLAVE_TOP_DRAM;
443 elsif std_match(top_decode, "10--") then
444 slave_top := SLAVE_TOP_BRAM;
445 elsif std_match(top_decode, "11--") then
446 slave_top := SLAVE_TOP_IO;
447 end if;
448
449 -- Top level wishbone muxing.
450 wb_bram_in <= wb_master_out;
451 wb_bram_in.cyc <= '0';
452 wb_dram_in <= wb_master_out;
453 wb_dram_in.cyc <= '0';
454 wb_io_in <= wb_master_out;
455 wb_io_in.cyc <= '0';
456 case slave_top is
457 when SLAVE_TOP_BRAM =>
458 wb_bram_in.cyc <= wb_master_out.cyc;
459 wb_master_in <= wb_bram_out;
460 when SLAVE_TOP_DRAM =>
461 if HAS_DRAM then
462 wb_dram_in.cyc <= wb_master_out.cyc;
463 wb_master_in <= wb_dram_out;
464 else
465 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
466 wb_master_in.dat <= (others => '1');
467 wb_master_in.stall <= '0';
468 end if;
469 when SLAVE_TOP_IO =>
470 wb_io_in.cyc <= wb_master_out.cyc;
471 wb_master_in <= wb_io_out;
472 end case;
473
474 end process slave_top_intercon;
475
476 -- IO wishbone slave 64->32 bits converter
477 --
478 -- For timing reasons, this adds a one cycle latch on the way both
479 -- in and out. This relaxes timing and routing pressure on the "main"
480 -- memory bus by moving all simple IOs to a slower 32-bit bus.
481 --
482 -- This implementation is rather dumb at the moment, no stash buffer,
483 -- so we stall whenever that latch is busy. This can be improved.
484 --
485 slave_io_latch: process(system_clk)
486 -- State
487 type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
488 variable state : state_t;
489
490 -- Misc
491 variable has_top : boolean;
492 variable has_bot : boolean;
493 variable do_cyc : std_ulogic;
494 variable end_cyc : std_ulogic;
495 variable slave_io : slave_io_type;
496 variable match : std_ulogic_vector(31 downto 12);
497 begin
498 if rising_edge(system_clk) then
499 do_cyc := '0';
500 end_cyc := '0';
501 if (rst) then
502 state := IDLE;
503 wb_io_out.ack <= '0';
504 wb_io_out.stall <= '0';
505 wb_sio_out.stb <= '0';
506 end_cyc := '1';
507 has_top := false;
508 has_bot := false;
509 else
510 case state is
511 when IDLE =>
512 -- Clear ACK in case it was set
513 wb_io_out.ack <= '0';
514
515 -- Do we have a cycle ?
516 if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
517 -- Stall master until we are done, we are't (yet) pipelining
518 -- this, it's all slow IOs.
519 wb_io_out.stall <= '1';
520
521 -- Start cycle downstream
522 do_cyc := '1';
523 wb_sio_out.stb <= '1';
524
525 -- Copy write enable to IO out, copy address as well
526 wb_sio_out.we <= wb_io_in.we;
527 wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left - 1 downto 0) & '0';
528
529 -- Do we have a top word and/or a bottom word ?
530 has_top := wb_io_in.sel(7 downto 4) /= "0000";
531 has_bot := wb_io_in.sel(3 downto 0) /= "0000";
532
533 -- If we have a bottom word, handle it first, otherwise
534 -- send the top word down. XXX Split the actual mux out
535 -- and only generate a control signal.
536 if has_bot then
537 if wb_io_in.we = '1' then
538 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
539 end if;
540 wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
541
542 -- Wait for ack
543 state := WAIT_ACK_BOT;
544 else
545 if wb_io_in.we = '1' then
546 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
547 end if;
548 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
549
550 -- Bump address
551 wb_sio_out.adr(0) <= '1';
552
553 -- Wait for ack
554 state := WAIT_ACK_TOP;
555 end if;
556 end if;
557 when WAIT_ACK_BOT =>
558 -- If we aren't stalled by the device, clear stb
559 if wb_sio_in.stall = '0' then
560 wb_sio_out.stb <= '0';
561 end if;
562
563 -- Handle ack
564 if wb_sio_in.ack = '1' then
565 -- If it's a read, latch the data
566 if wb_sio_out.we = '0' then
567 wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
568 end if;
569
570 -- Do we have a "top" part as well ?
571 if has_top then
572 -- Latch data & sel
573 if wb_io_in.we = '1' then
574 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
575 end if;
576 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
577
578 -- Bump address and set STB
579 wb_sio_out.adr(0) <= '1';
580 wb_sio_out.stb <= '1';
581
582 -- Wait for new ack
583 state := WAIT_ACK_TOP;
584 else
585 -- We are done, ack up, clear cyc downstream
586 end_cyc := '1';
587
588 -- And ack & unstall upstream
589 wb_io_out.ack <= '1';
590 wb_io_out.stall <= '0';
591
592 -- Wait for next one
593 state := IDLE;
594 end if;
595 end if;
596 when WAIT_ACK_TOP =>
597 -- If we aren't stalled by the device, clear stb
598 if wb_sio_in.stall = '0' then
599 wb_sio_out.stb <= '0';
600 end if;
601
602 -- Handle ack
603 if wb_sio_in.ack = '1' then
604 -- If it's a read, latch the data
605 if wb_sio_out.we = '0' then
606 wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
607 end if;
608
609 -- We are done, ack up, clear cyc downstram
610 end_cyc := '1';
611
612 -- And ack & unstall upstream
613 wb_io_out.ack <= '1';
614 wb_io_out.stall <= '0';
615
616 -- Wait for next one
617 state := IDLE;
618 end if;
619 end case;
620 end if;
621
622 -- Create individual registered cycle signals for the wishbones
623 -- going to the various peripherals
624 if do_cyc = '1' or end_cyc = '1' then
625 io_cycle_none <= '0';
626 io_cycle_syscon <= '0';
627 io_cycle_uart <= '0';
628 io_cycle_uart1 <= '0';
629 io_cycle_uartusb <= '0';
630 io_cycle_icp <= '0';
631 io_cycle_ics <= '0';
632 io_cycle_spi_flash <= '0';
633 io_cycle_gpio <= '0';
634 io_cycle_external <= '0';
635 wb_sio_out.cyc <= '0';
636 wb_ext_is_dram_init <= '0';
637 wb_spiflash_is_map <= '0';
638 wb_spiflash_is_reg <= '0';
639 wb_ext_is_dram_csr <= '0';
640 wb_ext_is_eth <= '0';
641 wb_ext_is_sdcard <= '0';
642 end if;
643 if do_cyc = '1' then
644 -- Decode I/O address
645 -- This is real address bits 29 downto 12
646 match := "11" & wb_io_in.adr(26 downto 9);
647 slave_io := SLAVE_IO_SYSCON;
648 if std_match(match, x"FF---") and HAS_DRAM then
649 slave_io := SLAVE_IO_EXTERNAL;
650 io_cycle_external <= '1';
651 wb_ext_is_dram_init <= '1';
652 elsif std_match(match, x"F----") then
653 slave_io := SLAVE_IO_SPI_FLASH;
654 io_cycle_spi_flash <= '1';
655 wb_spiflash_is_map <= '1';
656 elsif std_match(match, x"C8---") then
657 -- Ext IO "chip selects"
658 if std_match(match, x"--00-") and HAS_DRAM then
659 slave_io := SLAVE_IO_EXTERNAL;
660 io_cycle_external <= '1';
661 wb_ext_is_dram_csr <= '1';
662 elsif (std_match(match, x"--02-") or std_match(match, x"--03-")) and
663 HAS_LITEETH then
664 slave_io := SLAVE_IO_EXTERNAL;
665 io_cycle_external <= '1';
666 wb_ext_is_eth <= '1';
667 elsif std_match(match, x"--04-") and HAS_SD_CARD then
668 slave_io := SLAVE_IO_EXTERNAL;
669 io_cycle_external <= '1';
670 wb_ext_is_sdcard <= '1';
671 else
672 io_cycle_none <= '1';
673 end if;
674 elsif std_match(match, x"C0000") then
675 slave_io := SLAVE_IO_SYSCON;
676 io_cycle_syscon <= '1';
677 elsif std_match(match, x"C0002") then
678 slave_io := SLAVE_IO_UART;
679 io_cycle_uart <= '1';
680 elsif std_match(match, x"C0003") then
681 slave_io := SLAVE_IO_UART1;
682 io_cycle_uart1 <= '1';
683 elsif std_match(match, x"C0004") then
684 slave_io := SLAVE_IO_ICP;
685 io_cycle_icp <= '1';
686 elsif std_match(match, x"C0005") then
687 slave_io := SLAVE_IO_ICS;
688 io_cycle_ics <= '1';
689 elsif std_match(match, x"C0006") then
690 slave_io := SLAVE_IO_SPI_FLASH;
691 io_cycle_spi_flash <= '1';
692 wb_spiflash_is_reg <= '1';
693 elsif std_match(match, x"C0007") then
694 slave_io := SLAVE_IO_GPIO;
695 io_cycle_gpio <= '1';
696 elsif std_match(match, x"C0008") then
697 slave_io := SLAVE_IO_UARTUSB;
698 io_cycle_uartusb <= '1';
699 else
700 io_cycle_none <= '1';
701 end if;
702 current_io_decode <= slave_io;
703 wb_sio_out.cyc <= '1';
704 end if;
705 end if;
706 end process;
707
708 -- IO wishbone slave interconnect.
709 --
710 slave_io_intercon: process(all)
711 begin
712 wb_uart0_in <= wb_sio_out;
713 wb_uart0_in.cyc <= io_cycle_uart;
714 wb_uart1_in <= wb_sio_out;
715 wb_uart1_in.cyc <= io_cycle_uart1;
716
717 wb_spiflash_in <= wb_sio_out;
718 wb_spiflash_in.cyc <= io_cycle_spi_flash;
719 -- Clear top bits so they don't make their way to the
720 -- flash chip.
721 wb_spiflash_in.adr(27 downto 26) <= "00";
722
723 wb_gpio_in <= wb_sio_out;
724 wb_gpio_in.cyc <= io_cycle_gpio;
725
726 wb_uartusb_in <= wb_sio_out;
727 wb_uartusb_in.cyc <= io_cycle_uartusb;
728 -- valentyusb was built at base 0x0, it only needs 5 low bits
729 wb_uartusb_in.adr <= (others => '0');
730 wb_uartusb_in.adr(4 downto 0) <= wb_sio_out.adr(4 downto 0);
731
732 -- Only give xics 8 bits of wb addr (for now...)
733 wb_xics_icp_in <= wb_sio_out;
734 wb_xics_icp_in.adr <= (others => '0');
735 wb_xics_icp_in.adr(5 downto 0) <= wb_sio_out.adr(5 downto 0);
736 wb_xics_icp_in.cyc <= io_cycle_icp;
737 wb_xics_ics_in <= wb_sio_out;
738 wb_xics_ics_in.adr <= (others => '0');
739 wb_xics_ics_in.adr(9 downto 0) <= wb_sio_out.adr(9 downto 0);
740 wb_xics_ics_in.cyc <= io_cycle_ics;
741
742 wb_ext_io_in <= wb_sio_out;
743 wb_ext_io_in.cyc <= io_cycle_external;
744
745 wb_syscon_in <= wb_sio_out;
746 wb_syscon_in.cyc <= io_cycle_syscon;
747
748 case current_io_decode is
749 when SLAVE_IO_EXTERNAL =>
750 wb_sio_in <= wb_ext_io_out;
751 when SLAVE_IO_SYSCON =>
752 wb_sio_in <= wb_syscon_out;
753 when SLAVE_IO_UART =>
754 wb_sio_in <= wb_uart0_out;
755 when SLAVE_IO_ICP =>
756 wb_sio_in <= wb_xics_icp_out;
757 when SLAVE_IO_ICS =>
758 wb_sio_in <= wb_xics_ics_out;
759 when SLAVE_IO_UART1 =>
760 wb_sio_in <= wb_uart1_out;
761 when SLAVE_IO_UARTUSB =>
762 wb_sio_in <= wb_uartusb_out;
763 when SLAVE_IO_SPI_FLASH =>
764 wb_sio_in <= wb_spiflash_out;
765 when SLAVE_IO_GPIO =>
766 wb_sio_in <= wb_gpio_out;
767 end case;
768
769 -- Default response, ack & return all 1's
770 if io_cycle_none = '1' then
771 wb_sio_in.dat <= (others => '1');
772 wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
773 wb_sio_in.stall <= '0';
774 end if;
775
776 end process;
777
778 -- Syscon slave
779 syscon0: entity work.syscon
780 generic map(
781 HAS_UART => true,
782 HAS_DRAM => HAS_DRAM,
783 BRAM_SIZE => MEMORY_SIZE,
784 DRAM_SIZE => DRAM_SIZE,
785 DRAM_INIT_SIZE => DRAM_INIT_SIZE,
786 CLK_FREQ => CLK_FREQ,
787 HAS_SPI_FLASH => HAS_SPI_FLASH,
788 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
789 HAS_LITEETH => HAS_LITEETH,
790 HAS_SD_CARD => HAS_SD_CARD,
791 UART0_IS_16550 => UART0_IS_16550,
792 HAS_UART1 => HAS_UART1,
793 HAS_UARTUSB => HAS_UARTUSB
794 )
795 port map(
796 clk => system_clk,
797 rst => rst,
798 wishbone_in => wb_syscon_in,
799 wishbone_out => wb_syscon_out,
800 dram_at_0 => dram_at_0,
801 core_reset => do_core_reset,
802 soc_reset => open -- XXX TODO
803 );
804
805 --
806 -- UART0
807 --
808 -- Either potato (legacy) or 16550
809 --
810 uart0_pp: if UART0_IS_POTATO generate
811 uart0: entity work.pp_soc_uart
812 generic map(
813 FIFO_DEPTH => 32
814 )
815 port map(
816 clk => system_clk,
817 reset => rst_uart,
818 txd => uart0_txd,
819 rxd => uart0_rxd,
820 irq => uart0_irq,
821 wb_adr_in => wb_uart0_in.adr(9 downto 0) & "00",
822 wb_dat_in => wb_uart0_in.dat(7 downto 0),
823 wb_dat_out => uart0_dat8,
824 wb_cyc_in => wb_uart0_in.cyc,
825 wb_stb_in => wb_uart0_in.stb,
826 wb_we_in => wb_uart0_in.we,
827 wb_ack_out => wb_uart0_out.ack
828 );
829
830 wb_uart0_out.dat <= x"000000" & uart0_dat8;
831 wb_uart0_out.stall <= not wb_uart0_out.ack;
832 end generate;
833
834 uart0_16550 : if UART0_IS_16550 generate
835 signal irq_l : std_ulogic;
836 begin
837 uart0: uart_top
838 port map (
839 wb_clk_i => system_clk,
840 wb_rst_i => rst_uart,
841 wb_adr_i => wb_uart0_in.adr(2 downto 0),
842 wb_dat_i => wb_uart0_in.dat(7 downto 0),
843 wb_dat_o => uart0_dat8,
844 wb_we_i => wb_uart0_in.we,
845 wb_stb_i => wb_uart0_in.stb,
846 wb_cyc_i => wb_uart0_in.cyc,
847 wb_ack_o => wb_uart0_out.ack,
848 int_o => irq_l,
849 stx_pad_o => uart0_txd,
850 srx_pad_i => uart0_rxd,
851 rts_pad_o => open,
852 cts_pad_i => '1',
853 dtr_pad_o => open,
854 dsr_pad_i => '1',
855 ri_pad_i => '0',
856 dcd_pad_i => '1'
857 );
858
859 -- Add a register on the irq out, helps timing
860 uart0_irq_latch: process(system_clk)
861 begin
862 if rising_edge(system_clk) then
863 uart0_irq <= irq_l;
864 end if;
865 end process;
866
867 wb_uart0_out.dat <= x"000000" & uart0_dat8;
868 wb_uart0_out.stall <= not wb_uart0_out.ack;
869 end generate;
870
871
872 uart0_valentyusb : if HAS_UARTUSB generate
873 component valentyusb port (
874 clk_clksys : in std_ulogic;
875 clk_clk48 : in std_ulogic;
876 reset : in std_ulogic;
877 usb_d_p : in std_ulogic;
878 usb_d_n : in std_ulogic;
879 usb_pullup : out std_ulogic;
880 usb_tx_en : out std_ulogic;
881 interrupt : out std_ulogic;
882 wishbone_adr : in std_ulogic_vector(29 downto 0);
883 wishbone_dat_w : in std_ulogic_vector(31 downto 0);
884 wishbone_dat_r : out std_ulogic_vector(31 downto 0);
885 wishbone_sel : in std_ulogic_vector(3 downto 0);
886 wishbone_cyc : in std_ulogic;
887 wishbone_stb : in std_ulogic;
888 wishbone_ack : out std_ulogic;
889 wishbone_we : in std_ulogic;
890 wishbone_cti : in std_ulogic_vector(2 downto 0);
891 wishbone_bte : in std_ulogic_vector(1 downto 0);
892 wishbone_err : out std_ulogic
893 );
894 end component;
895 signal irq_l : std_ulogic;
896 begin
897 uart0: valentyusb
898 port map (
899 clk_clksys => system_clk,
900 clk_clk48 => clk_48,
901 reset => rst_uart,
902 usb_d_p => usb_d_p,
903 usb_d_n => usb_d_n,
904 usb_pullup => usb_pullup,
905 -- TODO, output flag
906 usb_tx_en => open,
907 wishbone_adr => "0000000000000000" & wb_uartusb_in.adr(13 downto 0),
908 wishbone_dat_r => wb_uartusb_out.dat,
909 wishbone_dat_w => wb_uartusb_in.dat,
910 wishbone_sel => wb_uartusb_in.sel,
911 wishbone_cyc => wb_uartusb_in.cyc,
912 wishbone_stb => wb_uartusb_in.stb,
913 wishbone_ack => wb_uartusb_out.ack,
914 wishbone_we => wb_uartusb_in.we,
915 interrupt => irq_l,
916 -- XXX matt check this
917 wishbone_cti => "000",
918 -- XXX matt check this
919 wishbone_bte => "00",
920 wishbone_err => open
921 );
922
923 wb_uartusb_out.stall <= not wb_uartusb_out.ack;
924
925 -- Add a register on the irq out, helps timing
926 uartusb_irq_latch: process(system_clk)
927 begin
928 if rising_edge(system_clk) then
929 uartusb_irq <= irq_l;
930 end if;
931 end process;
932 end generate;
933
934 --
935 -- UART1
936 --
937 -- Always 16550 if it exists
938 --
939 uart1: if HAS_UART1 generate
940 signal irq_l : std_ulogic;
941 begin
942 uart1: uart_top
943 port map (
944 wb_clk_i => system_clk,
945 wb_rst_i => rst_uart,
946 wb_adr_i => wb_uart1_in.adr(2 downto 0),
947 wb_dat_i => wb_uart1_in.dat(7 downto 0),
948 wb_dat_o => uart1_dat8,
949 wb_we_i => wb_uart1_in.we,
950 wb_stb_i => wb_uart1_in.stb,
951 wb_cyc_i => wb_uart1_in.cyc,
952 wb_ack_o => wb_uart1_out.ack,
953 int_o => irq_l,
954 stx_pad_o => uart1_txd,
955 srx_pad_i => uart1_rxd,
956 rts_pad_o => open,
957 cts_pad_i => '1',
958 dtr_pad_o => open,
959 dsr_pad_i => '1',
960 ri_pad_i => '0',
961 dcd_pad_i => '1'
962 );
963 -- Add a register on the irq out, helps timing
964 uart0_irq_latch: process(system_clk)
965 begin
966 if rising_edge(system_clk) then
967 uart1_irq <= irq_l;
968 end if;
969 end process;
970 wb_uart1_out.dat <= x"000000" & uart1_dat8;
971 wb_uart1_out.stall <= not wb_uart1_out.ack;
972 end generate;
973
974 no_uart1 : if not HAS_UART1 generate
975 wb_uart1_out.dat <= x"00000000";
976 wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
977 wb_uart1_out.stall <= '0';
978 uart1_irq <= '0';
979 end generate;
980
981 spiflash_gen: if HAS_SPI_FLASH generate
982 spiflash: entity work.spi_flash_ctrl
983 generic map (
984 DATA_LINES => SPI_FLASH_DLINES,
985 DEF_CLK_DIV => SPI_FLASH_DEF_CKDV,
986 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD,
987 BOOT_CLOCKS => SPI_BOOT_CLOCKS
988 )
989 port map(
990 rst => rst_spi,
991 clk => system_clk,
992 wb_in => wb_spiflash_in,
993 wb_out => wb_spiflash_out,
994 wb_sel_reg => wb_spiflash_is_reg,
995 wb_sel_map => wb_spiflash_is_map,
996 sck => spi_flash_sck,
997 cs_n => spi_flash_cs_n,
998 sdat_o => spi_flash_sdat_o,
999 sdat_oe => spi_flash_sdat_oe,
1000 sdat_i => spi_flash_sdat_i
1001 );
1002 end generate;
1003
1004 no_spi0_gen: if not HAS_SPI_FLASH generate
1005 wb_spiflash_out.dat <= (others => '1');
1006 wb_spiflash_out.ack <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
1007 wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
1008 end generate;
1009
1010 xics_icp: entity work.xics_icp
1011 port map(
1012 clk => system_clk,
1013 rst => rst_xics,
1014 wb_in => wb_xics_icp_in,
1015 wb_out => wb_xics_icp_out,
1016 ics_in => ics_to_icp,
1017 core_irq_out => core_ext_irq
1018 );
1019
1020 xics_ics: entity work.xics_ics
1021 generic map(
1022 SRC_NUM => 16,
1023 PRIO_BITS => 3
1024 )
1025 port map(
1026 clk => system_clk,
1027 rst => rst_xics,
1028 wb_in => wb_xics_ics_in,
1029 wb_out => wb_xics_ics_out,
1030 int_level_in => int_level_in,
1031 icp_out => ics_to_icp
1032 );
1033
1034 gpio0_gen: if HAS_GPIO generate
1035 gpio : entity work.gpio
1036 generic map(
1037 NGPIO => NGPIO
1038 )
1039 port map(
1040 clk => system_clk,
1041 rst => rst_gpio,
1042 wb_in => wb_gpio_in,
1043 wb_out => wb_gpio_out,
1044 gpio_in => gpio_in,
1045 gpio_out => gpio_out,
1046 gpio_dir => gpio_dir,
1047 intr => gpio_intr
1048 );
1049 end generate;
1050
1051 -- Assign external interrupts
1052 interrupts: process(all)
1053 begin
1054 int_level_in <= (others => '0');
1055 int_level_in(0) <= uart0_irq;
1056 int_level_in(1) <= ext_irq_eth;
1057 int_level_in(2) <= uart1_irq;
1058 int_level_in(3) <= ext_irq_sdcard;
1059 int_level_in(4) <= gpio_intr;
1060 int_level_in(5) <= uartusb_irq;
1061 end process;
1062
1063 -- BRAM Memory slave
1064 bram: if MEMORY_SIZE /= 0 generate
1065 bram0: entity work.wishbone_bram_wrapper
1066 generic map(
1067 MEMORY_SIZE => MEMORY_SIZE,
1068 RAM_INIT_FILE => RAM_INIT_FILE
1069 )
1070 port map(
1071 clk => system_clk,
1072 rst => rst_bram,
1073 wishbone_in => wb_bram_in,
1074 wishbone_out => wb_bram_out
1075 );
1076 end generate;
1077
1078 no_bram: if MEMORY_SIZE = 0 generate
1079 wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
1080 wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
1081 wb_bram_out.stall <= not wb_bram_out.ack;
1082 end generate;
1083
1084 -- DMI(debug bus) <-> JTAG bridge
1085 dtm: entity work.dmi_dtm
1086 generic map(
1087 ABITS => 8,
1088 DBITS => 64
1089 )
1090 port map(
1091 sys_clk => system_clk,
1092 sys_reset => rst_dtm,
1093 dmi_addr => dmi_addr,
1094 dmi_din => dmi_din,
1095 dmi_dout => dmi_dout,
1096 dmi_req => dmi_req,
1097 dmi_wr => dmi_wr,
1098 dmi_ack => dmi_ack
1099 );
1100
1101 -- DMI interconnect
1102 dmi_intercon: process(dmi_addr, dmi_req,
1103 dmi_wb_ack, dmi_wb_dout,
1104 dmi_core_ack, dmi_core_dout)
1105
1106 -- DMI address map (each address is a full 64-bit register)
1107 --
1108 -- Offset: Size: Slave:
1109 -- 0 4 Wishbone
1110 -- 10 16 Core
1111
1112 type slave_type is (SLAVE_WB,
1113 SLAVE_CORE,
1114 SLAVE_NONE);
1115 variable slave : slave_type;
1116 begin
1117 -- Simple address decoder
1118 slave := SLAVE_NONE;
1119 if std_match(dmi_addr, "000000--") then
1120 slave := SLAVE_WB;
1121 elsif std_match(dmi_addr, "0001----") then
1122 slave := SLAVE_CORE;
1123 end if;
1124
1125 -- DMI muxing
1126 dmi_wb_req <= '0';
1127 dmi_core_req <= '0';
1128 case slave is
1129 when SLAVE_WB =>
1130 dmi_wb_req <= dmi_req;
1131 dmi_ack <= dmi_wb_ack;
1132 dmi_din <= dmi_wb_dout;
1133 when SLAVE_CORE =>
1134 dmi_core_req <= dmi_req;
1135 dmi_ack <= dmi_core_ack;
1136 dmi_din <= dmi_core_dout;
1137 when others =>
1138 dmi_ack <= dmi_req;
1139 dmi_din <= (others => '1');
1140 end case;
1141
1142 -- SIM magic exit
1143 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
1144 stop;
1145 end if;
1146 end process;
1147
1148 -- Wishbone debug master (TODO: Add a DMI address decoder)
1149 wishbone_debug: entity work.wishbone_debug_master
1150 port map(clk => system_clk,
1151 rst => rst_wbdb,
1152 dmi_addr => dmi_addr(1 downto 0),
1153 dmi_dout => dmi_wb_dout,
1154 dmi_din => dmi_dout,
1155 dmi_wr => dmi_wr,
1156 dmi_ack => dmi_wb_ack,
1157 dmi_req => dmi_wb_req,
1158 wb_in => wishbone_debug_in,
1159 wb_out => wishbone_debug_out);
1160
1161 --pragma synthesis_off
1162 wb_x_state: process(system_clk)
1163 begin
1164 if rising_edge(system_clk) then
1165 if not rst then
1166 -- Wishbone arbiter
1167 assert not(is_x(wb_masters_out(0).cyc)) and not(is_x(wb_masters_out(0).stb)) severity failure;
1168 assert not(is_x(wb_masters_out(1).cyc)) and not(is_x(wb_masters_out(1).stb)) severity failure;
1169 assert not(is_x(wb_masters_out(2).cyc)) and not(is_x(wb_masters_out(2).stb)) severity failure;
1170 assert not(is_x(wb_masters_in(0).ack)) severity failure;
1171 assert not(is_x(wb_masters_in(1).ack)) severity failure;
1172 assert not(is_x(wb_masters_in(2).ack)) severity failure;
1173
1174 -- Main memory wishbones
1175 assert not(is_x(wb_bram_in.cyc)) and not (is_x(wb_bram_in.stb)) severity failure;
1176 assert not(is_x(wb_dram_in.cyc)) and not (is_x(wb_dram_in.stb)) severity failure;
1177 assert not(is_x(wb_io_in.cyc)) and not (is_x(wb_io_in.stb)) severity failure;
1178 assert not(is_x(wb_bram_out.ack)) severity failure;
1179 assert not(is_x(wb_dram_out.ack)) severity failure;
1180 assert not(is_x(wb_io_out.ack)) severity failure;
1181
1182 -- I/O wishbones
1183 assert not(is_x(wb_uart0_in.cyc)) and not(is_x(wb_uart0_in.stb)) severity failure;
1184 assert not(is_x(wb_uart1_in.cyc)) and not(is_x(wb_uart1_in.stb)) severity failure;
1185 assert not(is_x(wb_spiflash_in.cyc)) and not(is_x(wb_spiflash_in.stb)) severity failure;
1186 assert not(is_x(wb_xics_icp_in.cyc)) and not(is_x(wb_xics_icp_in.stb)) severity failure;
1187 assert not(is_x(wb_xics_ics_in.cyc)) and not(is_x(wb_xics_ics_in.stb)) severity failure;
1188 assert not(is_x(wb_ext_io_in.cyc)) and not(is_x(wb_ext_io_in.stb)) severity failure;
1189 assert not(is_x(wb_syscon_in.cyc)) and not(is_x(wb_syscon_in.stb)) severity failure;
1190 assert not(is_x(wb_uart0_out.ack)) severity failure;
1191 assert not(is_x(wb_uart1_out.ack)) severity failure;
1192 assert not(is_x(wb_spiflash_out.ack)) severity failure;
1193 assert not(is_x(wb_xics_icp_out.ack)) severity failure;
1194 assert not(is_x(wb_xics_ics_out.ack)) severity failure;
1195 assert not(is_x(wb_ext_io_out.ack)) severity failure;
1196 assert not(is_x(wb_syscon_out.ack)) severity failure;
1197 end if;
1198 end if;
1199 end process;
1200 --pragma synthesis_on
1201
1202 end architecture behaviour;