soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.math_real.all;
   4
   5 use std.textio.all;
   6
   7 library work;
   8 use work.common.all;
   9 use work.wishbone_types.all;
  10
  11
  12 -- 0x00000000: Main memory (1 MB)
  13 -- 0xc0002000: UART0 (for host communication)
  14 entity soc is
  15     generic (
  16         MEMORY_SIZE   : positive;
  17         RAM_INIT_FILE : string;
  18         RESET_LOW     : boolean;
  19         SIM           : boolean
  20         );
  21     port(
  22         rst          : in  std_ulogic;
  23         system_clk   : in  std_ulogic;
  24
  25         -- UART0 signals:
  26         uart0_txd    : out std_ulogic;
  27         uart0_rxd    : in  std_ulogic
  28         );
  29 end entity soc;
  30
  31 architecture behaviour of soc is
  32
  33     -- Wishbone master signals:
  34     signal wishbone_dcore_in : wishbone_slave_out;
  35     signal wishbone_dcore_out : wishbone_master_out;
  36     signal wishbone_icore_in : wishbone_slave_out;
  37     signal wishbone_icore_out : wishbone_master_out;
  38     signal wishbone_debug_in : wishbone_slave_out;
  39     signal wishbone_debug_out : wishbone_master_out;
  40
  41     -- Wishbone master (output of arbiter):
  42     signal wb_master_in : wishbone_slave_out;
  43     signal wb_master_out : wishbone_master_out;
  44
  45     -- UART0 signals:
  46     signal wb_uart0_in   : wishbone_master_out;
  47     signal wb_uart0_out  : wishbone_slave_out;
  48     signal uart_dat8     : std_ulogic_vector(7 downto 0);
  49
  50     -- Main memory signals:
  51     signal wb_bram_in     : wishbone_master_out;
  52     signal wb_bram_out    : wishbone_slave_out;
  53     constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
  54
  55     -- Core debug signals (used in SIM only)
  56     signal registers     : regfile;
  57     signal terminate     : std_ulogic;
  58
  59     -- DMI debug bus signals
  60     signal dmi_addr     : std_ulogic_vector(7 downto 0);
  61     signal dmi_din      : std_ulogic_vector(63 downto 0);
  62     signal dmi_dout     : std_ulogic_vector(63 downto 0);
  63     signal dmi_req      : std_ulogic;
  64     signal dmi_wr       : std_ulogic;
  65     signal dmi_ack      : std_ulogic;
  66
  67 begin
  68
  69     -- Processor core
  70     processor: entity work.core
  71         generic map(
  72             SIM => SIM
  73             )
  74         port map(
  75             clk => system_clk,
  76             rst => rst,
  77             wishbone_insn_in => wishbone_icore_in,
  78             wishbone_insn_out => wishbone_icore_out,
  79             wishbone_data_in => wishbone_dcore_in,
  80             wishbone_data_out => wishbone_dcore_out,
  81             registers => registers,
  82             terminate_out => terminate
  83             );
  84
  85     -- Wishbone bus master arbiter & mux
  86     wishbone_arbiter_0: entity work.wishbone_arbiter
  87         port map(
  88             clk => system_clk, rst => rst,
  89             wb1_in => wishbone_dcore_out, wb1_out => wishbone_dcore_in,
  90             wb2_in => wishbone_icore_out, wb2_out => wishbone_icore_in,
  91             wb3_in => wishbone_debug_out, wb3_out => wishbone_debug_in,
  92             wb_out => wb_master_out, wb_in => wb_master_in
  93             );
  94
  95     -- Wishbone slaves address decoder & mux
  96     slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
  97         -- Selected slave
  98         type slave_type is (SLAVE_UART,
  99                             SLAVE_MEMORY,
 100                             SLAVE_NONE);
 101         variable slave : slave_type;
 102     begin
 103         -- Simple address decoder
 104         slave := SLAVE_NONE;
 105         if wb_master_out.adr(63 downto 24) = x"0000000000" then
 106             slave := SLAVE_MEMORY;
 107         elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then
 108             if wb_master_out.adr(15 downto 12) = x"2" then
 109                 slave := SLAVE_UART;
 110             end if;
 111         end if;
 112
 113         -- Wishbone muxing. Defaults:
 114         wb_bram_in <= wb_master_out;
 115         wb_bram_in.cyc  <= '0';
 116         wb_uart0_in <= wb_master_out;
 117         wb_uart0_in.cyc <= '0';
 118         case slave is
 119         when SLAVE_MEMORY =>
 120             wb_bram_in.cyc <= wb_master_out.cyc;
 121             wb_master_in <= wb_bram_out;
 122         when SLAVE_UART =>
 123             wb_uart0_in.cyc <= wb_master_out.cyc;
 124             wb_master_in <= wb_uart0_out;
 125         when others =>
 126             wb_master_in.dat <= (others => '1');
 127             wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
 128         end case;
 129     end process slave_intercon;
 130
 131     -- Simulated memory and UART
 132     sim_terminate_test: if SIM generate
 133
 134         -- Dump registers if core terminates
 135         dump_registers: process(all)
 136         begin
 137             if terminate = '1' then
 138                 loop_0: for i in 0 to 31 loop
 139                     report "REG " & to_hstring(registers(i));
 140                 end loop loop_0;
 141                 assert false report "end of test" severity failure;
 142             end if;
 143         end process;
 144
 145     end generate;
 146
 147     -- UART0 wishbone slave
 148     -- XXX FIXME: Need a proper wb64->wb8 adapter that
 149     --            converts SELs into low address bits and muxes
 150     --            data accordingly (either that or rejects large
 151     --            cycles).
 152     uart0: entity work.pp_soc_uart
 153         generic map(
 154             FIFO_DEPTH => 32
 155             )
 156         port map(
 157             clk => system_clk,
 158             reset => rst,
 159             txd => uart0_txd,
 160             rxd => uart0_rxd,
 161             wb_adr_in => wb_uart0_in.adr(11 downto 0),
 162             wb_dat_in => wb_uart0_in.dat(7 downto 0),
 163             wb_dat_out => uart_dat8,
 164             wb_cyc_in => wb_uart0_in.cyc,
 165             wb_stb_in => wb_uart0_in.stb,
 166             wb_we_in => wb_uart0_in.we,
 167             wb_ack_out => wb_uart0_out.ack
 168             );
 169     wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
 170
 171     -- BRAM Memory slave
 172     bram0: entity work.mw_soc_memory
 173         generic map(
 174             MEMORY_SIZE   => MEMORY_SIZE,
 175             RAM_INIT_FILE => RAM_INIT_FILE
 176             )
 177         port map(
 178             clk => system_clk,
 179             rst => rst,
 180             wishbone_in => wb_bram_in,
 181             wishbone_out => wb_bram_out
 182             );
 183
 184     -- DMI(debug bus) <-> JTAG bridge
 185     dtm: entity work.dmi_dtm
 186         generic map(
 187             ABITS => 8,
 188             DBITS => 64
 189             )
 190         port map(
 191             sys_clk     => system_clk,
 192             sys_reset   => rst,
 193             dmi_addr    => dmi_addr,
 194             dmi_din     => dmi_din,
 195             dmi_dout    => dmi_dout,
 196             dmi_req     => dmi_req,
 197             dmi_wr      => dmi_wr,
 198             dmi_ack     => dmi_ack
 199             );
 200
 201     -- Wishbone debug master (TODO: Add a DMI address decoder)
 202     wishbone_debug: entity work.wishbone_debug_master
 203         port map(clk => system_clk, rst => rst,
 204                  dmi_addr => dmi_addr(1 downto 0),
 205                  dmi_dout => dmi_din,
 206                  dmi_din => dmi_dout,
 207                  dmi_wr => dmi_wr,
 208                  dmi_ack => dmi_ack,
 209                  dmi_req => dmi_req,
 210                  wb_in => wishbone_debug_in,
 211                  wb_out => wishbone_debug_out);
 212
 213
 214 end architecture behaviour;