2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
10 use work.wishbone_types.all;
13 -- 0x00000000: Main memory (1 MB)
14 -- 0xc0002000: UART0 (for host communication)
17 MEMORY_SIZE : positive;
18 RAM_INIT_FILE : string;
21 DISABLE_FLATTEN_CORE : boolean := false
25 system_clk : in std_ulogic;
28 uart0_txd : out std_ulogic;
29 uart0_rxd : in std_ulogic
33 architecture behaviour of soc is
35 -- Wishbone master signals:
36 signal wishbone_dcore_in : wishbone_slave_out;
37 signal wishbone_dcore_out : wishbone_master_out;
38 signal wishbone_icore_in : wishbone_slave_out;
39 signal wishbone_icore_out : wishbone_master_out;
40 signal wishbone_debug_in : wishbone_slave_out;
41 signal wishbone_debug_out : wishbone_master_out;
43 -- Arbiter array (ghdl doesnt' support assigning the array
44 -- elements in the entity instantiation)
45 constant NUM_WB_MASTERS : positive := 3;
46 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
47 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
49 -- Wishbone master (output of arbiter):
50 signal wb_master_in : wishbone_slave_out;
51 signal wb_master_out : wishbone_master_out;
54 signal wb_uart0_in : wishbone_master_out;
55 signal wb_uart0_out : wishbone_slave_out;
56 signal uart_dat8 : std_ulogic_vector(7 downto 0);
58 -- Main memory signals:
59 signal wb_bram_in : wishbone_master_out;
60 signal wb_bram_out : wishbone_slave_out;
61 constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
63 -- DMI debug bus signals
64 signal dmi_addr : std_ulogic_vector(7 downto 0);
65 signal dmi_din : std_ulogic_vector(63 downto 0);
66 signal dmi_dout : std_ulogic_vector(63 downto 0);
67 signal dmi_req : std_ulogic;
68 signal dmi_wr : std_ulogic;
69 signal dmi_ack : std_ulogic;
71 -- Per slave DMI signals
72 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
73 signal dmi_wb_req : std_ulogic;
74 signal dmi_wb_ack : std_ulogic;
75 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
76 signal dmi_core_req : std_ulogic;
77 signal dmi_core_ack : std_ulogic;
81 processor: entity work.core
84 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE
89 wishbone_insn_in => wishbone_icore_in,
90 wishbone_insn_out => wishbone_icore_out,
91 wishbone_data_in => wishbone_dcore_in,
92 wishbone_data_out => wishbone_dcore_out,
93 dmi_addr => dmi_addr(3 downto 0),
94 dmi_dout => dmi_core_dout,
97 dmi_ack => dmi_core_ack,
98 dmi_req => dmi_core_req
101 -- Wishbone bus master arbiter & mux
102 wb_masters_out <= (0 => wishbone_dcore_out,
103 1 => wishbone_icore_out,
104 2 => wishbone_debug_out);
105 wishbone_dcore_in <= wb_masters_in(0);
106 wishbone_icore_in <= wb_masters_in(1);
107 wishbone_debug_in <= wb_masters_in(2);
108 wishbone_arbiter_0: entity work.wishbone_arbiter
110 NUM_MASTERS => NUM_WB_MASTERS
113 clk => system_clk, rst => rst,
114 wb_masters_in => wb_masters_out,
115 wb_masters_out => wb_masters_in,
116 wb_slave_out => wb_master_out,
117 wb_slave_in => wb_master_in
120 -- Wishbone slaves address decoder & mux
121 slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
123 type slave_type is (SLAVE_UART_0,
126 variable slave : slave_type;
128 -- Simple address decoder.
130 if wb_master_out.adr(31 downto 24) = x"00" then
131 slave := SLAVE_MEMORY;
132 elsif wb_master_out.adr(31 downto 24) = x"c0" then
133 if wb_master_out.adr(23 downto 12) = x"002" then
134 slave := SLAVE_UART_0;
138 -- Wishbone muxing. Defaults:
139 wb_bram_in <= wb_master_out;
140 wb_bram_in.cyc <= '0';
141 wb_uart0_in <= wb_master_out;
142 wb_uart0_in.cyc <= '0';
145 wb_bram_in.cyc <= wb_master_out.cyc;
146 wb_master_in <= wb_bram_out;
148 wb_uart0_in.cyc <= wb_master_out.cyc;
149 wb_master_in <= wb_uart0_out;
151 wb_master_in.dat <= (others => '1');
152 wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
153 wb_master_in.stall <= '0';
155 end process slave_intercon;
157 -- Simulated memory and UART
159 -- UART0 wishbone slave
160 -- XXX FIXME: Need a proper wb64->wb8 adapter that
161 -- converts SELs into low address bits and muxes
162 -- data accordingly (either that or rejects large
164 uart0: entity work.pp_soc_uart
173 wb_adr_in => wb_uart0_in.adr(11 downto 0),
174 wb_dat_in => wb_uart0_in.dat(7 downto 0),
175 wb_dat_out => uart_dat8,
176 wb_cyc_in => wb_uart0_in.cyc,
177 wb_stb_in => wb_uart0_in.stb,
178 wb_we_in => wb_uart0_in.we,
179 wb_ack_out => wb_uart0_out.ack
181 wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
182 wb_uart0_out.stall <= '0' when wb_uart0_in.cyc = '0' else not wb_uart0_out.ack;
185 bram0: entity work.wishbone_bram_wrapper
187 MEMORY_SIZE => MEMORY_SIZE,
188 RAM_INIT_FILE => RAM_INIT_FILE
193 wishbone_in => wb_bram_in,
194 wishbone_out => wb_bram_out
197 -- DMI(debug bus) <-> JTAG bridge
198 dtm: entity work.dmi_dtm
204 sys_clk => system_clk,
206 dmi_addr => dmi_addr,
208 dmi_dout => dmi_dout,
215 dmi_intercon: process(dmi_addr, dmi_req,
216 dmi_wb_ack, dmi_wb_dout,
217 dmi_core_ack, dmi_core_dout)
219 -- DMI address map (each address is a full 64-bit register)
221 -- Offset: Size: Slave:
225 type slave_type is (SLAVE_WB,
228 variable slave : slave_type;
230 -- Simple address decoder
232 if std_match(dmi_addr, "000000--") then
234 elsif std_match(dmi_addr, "0001----") then
243 dmi_wb_req <= dmi_req;
244 dmi_ack <= dmi_wb_ack;
245 dmi_din <= dmi_wb_dout;
247 dmi_core_req <= dmi_req;
248 dmi_ack <= dmi_core_ack;
249 dmi_din <= dmi_core_dout;
252 dmi_din <= (others => '1');
256 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
261 -- Wishbone debug master (TODO: Add a DMI address decoder)
262 wishbone_debug: entity work.wishbone_debug_master
263 port map(clk => system_clk, rst => rst,
264 dmi_addr => dmi_addr(1 downto 0),
265 dmi_dout => dmi_wb_dout,
268 dmi_ack => dmi_wb_ack,
269 dmi_req => dmi_wb_req,
270 wb_in => wishbone_debug_in,
271 wb_out => wishbone_debug_out);
274 end architecture behaviour;