2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
10 use work.wishbone_types.all;
13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
17 -- 0x40000000: DRAM (when present)
18 -- 0x80000000: Block RAM (aliased & repeated)
23 -- 0xc0004000: XICS ICP
24 -- 0xc0006000: SPI Flash controller
25 -- 0xc0100000: LiteDRAM control (CSRs)
26 -- 0xf0000000: Flash "ROM" mapping
27 -- 0xff000000: DRAM init code (if any) or flash ROM
31 MEMORY_SIZE : natural;
32 RAM_INIT_FILE : string;
35 DISABLE_FLATTEN_CORE : boolean := false;
36 HAS_DRAM : boolean := false;
37 DRAM_SIZE : integer := 0;
38 DRAM_INIT_SIZE : integer := 0;
39 HAS_SPI_FLASH : boolean := false;
40 SPI_FLASH_DLINES : positive := 1;
41 SPI_FLASH_OFFSET : integer := 0;
42 SPI_FLASH_DEF_CKDV : natural := 2;
43 SPI_FLASH_DEF_QUAD : boolean := false
47 system_clk : in std_ulogic;
49 -- DRAM controller signals
50 wb_dram_in : out wishbone_master_out;
51 wb_dram_out : in wishbone_slave_out;
52 wb_dram_ctrl_in : out wb_io_master_out;
53 wb_dram_ctrl_out : in wb_io_slave_out;
54 wb_dram_is_csr : out std_ulogic;
55 wb_dram_is_init : out std_ulogic;
58 uart0_txd : out std_ulogic;
59 uart0_rxd : in std_ulogic;
62 spi_flash_sck : out std_ulogic;
63 spi_flash_cs_n : out std_ulogic;
64 spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
65 spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
66 spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
68 -- DRAM controller signals
69 alt_reset : in std_ulogic
73 architecture behaviour of soc is
75 -- Wishbone master signals:
76 signal wishbone_dcore_in : wishbone_slave_out;
77 signal wishbone_dcore_out : wishbone_master_out;
78 signal wishbone_icore_in : wishbone_slave_out;
79 signal wishbone_icore_out : wishbone_master_out;
80 signal wishbone_debug_in : wishbone_slave_out;
81 signal wishbone_debug_out : wishbone_master_out;
83 -- Arbiter array (ghdl doesnt' support assigning the array
84 -- elements in the entity instantiation)
85 constant NUM_WB_MASTERS : positive := 3;
86 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
87 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
89 -- Wishbone master (output of arbiter):
90 signal wb_master_in : wishbone_slave_out;
91 signal wb_master_out : wishbone_master_out;
93 -- Main "IO" bus, from main slave decoder to the latch
94 signal wb_io_in : wishbone_master_out;
95 signal wb_io_out : wishbone_slave_out;
97 -- Secondary (smaller) IO bus after the IO bus latch
98 signal wb_sio_out : wb_io_master_out;
99 signal wb_sio_in : wb_io_slave_out;
102 signal dram_at_0 : std_ulogic;
103 signal do_core_reset : std_ulogic;
104 signal wb_syscon_in : wb_io_master_out;
105 signal wb_syscon_out : wb_io_slave_out;
108 signal wb_uart0_in : wb_io_master_out;
109 signal wb_uart0_out : wb_io_slave_out;
110 signal uart_dat8 : std_ulogic_vector(7 downto 0);
112 -- SPI Flash controller signals:
113 signal wb_spiflash_in : wb_io_master_out;
114 signal wb_spiflash_out : wb_io_slave_out;
115 signal wb_spiflash_is_reg : std_ulogic;
116 signal wb_spiflash_is_map : std_ulogic;
119 signal wb_xics0_in : wb_io_master_out;
120 signal wb_xics0_out : wb_io_slave_out;
121 signal int_level_in : std_ulogic_vector(15 downto 0);
123 signal core_ext_irq : std_ulogic;
125 -- Main memory signals:
126 signal wb_bram_in : wishbone_master_out;
127 signal wb_bram_out : wishbone_slave_out;
129 -- DMI debug bus signals
130 signal dmi_addr : std_ulogic_vector(7 downto 0);
131 signal dmi_din : std_ulogic_vector(63 downto 0);
132 signal dmi_dout : std_ulogic_vector(63 downto 0);
133 signal dmi_req : std_ulogic;
134 signal dmi_wr : std_ulogic;
135 signal dmi_ack : std_ulogic;
137 -- Per slave DMI signals
138 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
139 signal dmi_wb_req : std_ulogic;
140 signal dmi_wb_ack : std_ulogic;
141 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
142 signal dmi_core_req : std_ulogic;
143 signal dmi_core_ack : std_ulogic;
145 -- Delayed/latched resets and alt_reset
146 signal rst_core : std_ulogic := '1';
147 signal rst_uart : std_ulogic := '1';
148 signal rst_xics : std_ulogic := '1';
149 signal rst_spi : std_ulogic := '1';
150 signal rst_bram : std_ulogic := '1';
151 signal rst_dtm : std_ulogic := '1';
152 signal rst_wbar : std_ulogic := '1';
153 signal rst_wbdb : std_ulogic := '1';
154 signal alt_reset_d : std_ulogic;
157 type slave_io_type is (SLAVE_IO_SYSCON,
162 SLAVE_IO_SPI_FLASH_REG,
163 SLAVE_IO_SPI_FLASH_MAP,
165 signal slave_io_dbg : slave_io_type;
168 resets: process(system_clk)
170 if rising_edge(system_clk) then
171 rst_core <= rst or do_core_reset;
179 alt_reset_d <= alt_reset;
184 processor: entity work.core
187 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
188 ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1')
193 alt_reset => alt_reset_d,
194 wishbone_insn_in => wishbone_icore_in,
195 wishbone_insn_out => wishbone_icore_out,
196 wishbone_data_in => wishbone_dcore_in,
197 wishbone_data_out => wishbone_dcore_out,
198 dmi_addr => dmi_addr(3 downto 0),
199 dmi_dout => dmi_core_dout,
202 dmi_ack => dmi_core_ack,
203 dmi_req => dmi_core_req,
204 ext_irq => core_ext_irq
207 -- Wishbone bus master arbiter & mux
208 wb_masters_out <= (0 => wishbone_dcore_out,
209 1 => wishbone_icore_out,
210 2 => wishbone_debug_out);
211 wishbone_dcore_in <= wb_masters_in(0);
212 wishbone_icore_in <= wb_masters_in(1);
213 wishbone_debug_in <= wb_masters_in(2);
214 wishbone_arbiter_0: entity work.wishbone_arbiter
216 NUM_MASTERS => NUM_WB_MASTERS
221 wb_masters_in => wb_masters_out,
222 wb_masters_out => wb_masters_in,
223 wb_slave_out => wb_master_out,
224 wb_slave_in => wb_master_in
227 -- Top level Wishbone slaves address decoder & mux
229 -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
236 slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
237 type slave_top_type is (SLAVE_TOP_BRAM,
240 variable slave_top : slave_top_type;
241 variable top_decode : std_ulogic_vector(3 downto 0);
243 -- Top-level address decoder
244 top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
245 slave_top := SLAVE_TOP_BRAM;
246 if std_match(top_decode, "0000") then
247 slave_top := SLAVE_TOP_BRAM;
248 elsif std_match(top_decode, "0001") then
249 slave_top := SLAVE_TOP_DRAM;
250 elsif std_match(top_decode, "01--") then
251 slave_top := SLAVE_TOP_DRAM;
252 elsif std_match(top_decode, "10--") then
253 slave_top := SLAVE_TOP_BRAM;
254 elsif std_match(top_decode, "11--") then
255 slave_top := SLAVE_TOP_IO;
258 -- Top level wishbone muxing.
259 wb_bram_in <= wb_master_out;
260 wb_bram_in.cyc <= '0';
261 wb_dram_in <= wb_master_out;
262 wb_dram_in.cyc <= '0';
263 wb_io_in <= wb_master_out;
266 when SLAVE_TOP_BRAM =>
267 wb_bram_in.cyc <= wb_master_out.cyc;
268 wb_master_in <= wb_bram_out;
269 when SLAVE_TOP_DRAM =>
270 wb_dram_in.cyc <= wb_master_out.cyc;
271 wb_master_in <= wb_dram_out;
273 wb_io_in.cyc <= wb_master_out.cyc;
274 wb_master_in <= wb_io_out;
276 end process slave_top_intercon;
278 -- IO wishbone slave 64->32 bits converter
280 -- For timing reasons, this adds a one cycle latch on the way both
281 -- in and out. This relaxes timing and routing pressure on the "main"
282 -- memory bus by moving all simple IOs to a slower 32-bit bus.
284 -- This implementation is rather dumb at the moment, no stash buffer,
285 -- so we stall whenever that latch is busy. This can be improved.
287 slave_io_latch: process(system_clk)
289 type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
290 variable state : state_t;
293 variable has_top : boolean;
294 variable has_bot : boolean;
296 if rising_edge(system_clk) then
299 wb_io_out.ack <= '0';
300 wb_io_out.stall <= '0';
301 wb_sio_out.cyc <= '0';
302 wb_sio_out.stb <= '0';
308 -- Clear ACK in case it was set
309 wb_io_out.ack <= '0';
311 -- Do we have a cycle ?
312 if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
313 -- Stall master until we are done, we are't (yet) pipelining
314 -- this, it's all slow IOs.
315 wb_io_out.stall <= '1';
317 -- Start cycle downstream
318 wb_sio_out.cyc <= '1';
319 wb_sio_out.stb <= '1';
321 -- Copy write enable to IO out, copy address as well
322 wb_sio_out.we <= wb_io_in.we;
323 wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
325 -- Do we have a top word and/or a bottom word ?
326 has_top := wb_io_in.sel(7 downto 4) /= "0000";
327 has_bot := wb_io_in.sel(3 downto 0) /= "0000";
329 -- If we have a bottom word, handle it first, otherwise
330 -- send the top word down. XXX Split the actual mux out
331 -- and only generate a control signal.
333 if wb_io_in.we = '1' then
334 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
336 wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
339 state := WAIT_ACK_BOT;
341 if wb_io_in.we = '1' then
342 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
344 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
347 wb_sio_out.adr(2) <= '1';
350 state := WAIT_ACK_TOP;
354 -- If we aren't stalled by the device, clear stb
355 if wb_sio_in.stall = '0' then
356 wb_sio_out.stb <= '0';
360 if wb_sio_in.ack = '1' then
361 -- If it's a read, latch the data
362 if wb_sio_out.we = '0' then
363 wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
366 -- Do we have a "top" part as well ?
369 if wb_io_in.we = '1' then
370 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
372 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
374 -- Bump address and set STB
375 wb_sio_out.adr(2) <= '1';
376 wb_sio_out.stb <= '1';
379 state := WAIT_ACK_TOP;
381 -- We are done, ack up, clear cyc downstram
382 wb_sio_out.cyc <= '0';
384 -- And ack & unstall upstream
385 wb_io_out.ack <= '1';
386 wb_io_out.stall <= '0';
393 -- If we aren't stalled by the device, clear stb
394 if wb_sio_in.stall = '0' then
395 wb_sio_out.stb <= '0';
399 if wb_sio_in.ack = '1' then
400 -- If it's a read, latch the data
401 if wb_sio_out.we = '0' then
402 wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
405 -- We are done, ack up, clear cyc downstram
406 wb_sio_out.cyc <= '0';
408 -- And ack & unstall upstream
409 wb_io_out.ack <= '1';
410 wb_io_out.stall <= '0';
420 -- IO wishbone slave intercon.
422 slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out,
423 wb_dram_ctrl_out, wb_xics0_out, wb_spiflash_out)
424 variable slave_io : slave_io_type;
426 variable match : std_ulogic_vector(31 downto 12);
429 -- Simple address decoder.
430 slave_io := SLAVE_IO_NONE;
431 match := "11" & wb_sio_out.adr(29 downto 12);
432 if std_match(match, x"FF---") and HAS_DRAM then
433 slave_io := SLAVE_IO_DRAM_INIT;
434 elsif std_match(match, x"F----") then
435 slave_io := SLAVE_IO_SPI_FLASH_MAP;
436 elsif std_match(match, x"C0000") then
437 slave_io := SLAVE_IO_SYSCON;
438 elsif std_match(match, x"C0002") then
439 slave_io := SLAVE_IO_UART;
440 elsif std_match(match, x"C01--") then
441 slave_io := SLAVE_IO_DRAM_CSR;
442 elsif std_match(match, x"C0004") then
443 slave_io := SLAVE_IO_ICP_0;
444 elsif std_match(match, x"C0006") then
445 slave_io := SLAVE_IO_SPI_FLASH_REG;
447 slave_io_dbg <= slave_io;
448 wb_uart0_in <= wb_sio_out;
449 wb_uart0_in.cyc <= '0';
450 wb_spiflash_in <= wb_sio_out;
451 wb_spiflash_in.cyc <= '0';
452 wb_spiflash_is_reg <= '0';
453 wb_spiflash_is_map <= '0';
455 -- Only give xics 8 bits of wb addr
456 wb_xics0_in <= wb_sio_out;
457 wb_xics0_in.adr <= (others => '0');
458 wb_xics0_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
459 wb_xics0_in.cyc <= '0';
461 wb_dram_ctrl_in <= wb_sio_out;
462 wb_dram_ctrl_in.cyc <= '0';
463 wb_dram_is_csr <= '0';
464 wb_dram_is_init <= '0';
466 wb_syscon_in <= wb_sio_out;
467 wb_syscon_in.cyc <= '0';
470 when SLAVE_IO_DRAM_INIT =>
471 wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
472 wb_sio_in <= wb_dram_ctrl_out;
473 wb_dram_is_init <= '1';
474 when SLAVE_IO_DRAM_CSR =>
475 wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
476 wb_sio_in <= wb_dram_ctrl_out;
477 wb_dram_is_csr <= '1';
478 when SLAVE_IO_SYSCON =>
479 wb_syscon_in.cyc <= wb_sio_out.cyc;
480 wb_sio_in <= wb_syscon_out;
481 when SLAVE_IO_UART =>
482 wb_uart0_in.cyc <= wb_sio_out.cyc;
483 wb_sio_in <= wb_uart0_out;
484 when SLAVE_IO_ICP_0 =>
485 wb_xics0_in.cyc <= wb_sio_out.cyc;
486 wb_sio_in <= wb_xics0_out;
487 when SLAVE_IO_SPI_FLASH_MAP =>
488 -- Clear top bits so they don't make their way to the
490 wb_spiflash_in.adr(29 downto 28) <= "00";
491 wb_spiflash_in.cyc <= wb_sio_out.cyc;
492 wb_sio_in <= wb_spiflash_out;
493 wb_spiflash_is_map <= '1';
494 when SLAVE_IO_SPI_FLASH_REG =>
495 wb_spiflash_in.cyc <= wb_sio_out.cyc;
496 wb_sio_in <= wb_spiflash_out;
497 wb_spiflash_is_reg <= '1';
499 wb_sio_in.dat <= (others => '1');
500 wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
501 wb_sio_in.stall <= '0';
507 syscon0: entity work.syscon
510 HAS_DRAM => HAS_DRAM,
511 BRAM_SIZE => MEMORY_SIZE,
512 DRAM_SIZE => DRAM_SIZE,
513 DRAM_INIT_SIZE => DRAM_INIT_SIZE,
514 CLK_FREQ => CLK_FREQ,
515 HAS_SPI_FLASH => HAS_SPI_FLASH,
516 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET
521 wishbone_in => wb_syscon_in,
522 wishbone_out => wb_syscon_out,
523 dram_at_0 => dram_at_0,
524 core_reset => do_core_reset,
525 soc_reset => open -- XXX TODO
528 -- Simulated memory and UART
530 -- UART0 wishbone slave
531 uart0: entity work.pp_soc_uart
540 irq => int_level_in(0),
541 wb_adr_in => wb_uart0_in.adr(11 downto 0),
542 wb_dat_in => wb_uart0_in.dat(7 downto 0),
543 wb_dat_out => uart_dat8,
544 wb_cyc_in => wb_uart0_in.cyc,
545 wb_stb_in => wb_uart0_in.stb,
546 wb_we_in => wb_uart0_in.we,
547 wb_ack_out => wb_uart0_out.ack
549 wb_uart0_out.dat <= x"000000" & uart_dat8;
550 wb_uart0_out.stall <= not wb_uart0_out.ack;
552 spiflash_gen: if HAS_SPI_FLASH generate
553 spiflash: entity work.spi_flash_ctrl
555 DATA_LINES => SPI_FLASH_DLINES,
556 DEF_CLK_DIV => SPI_FLASH_DEF_CKDV,
557 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
562 wb_in => wb_spiflash_in,
563 wb_out => wb_spiflash_out,
564 wb_sel_reg => wb_spiflash_is_reg,
565 wb_sel_map => wb_spiflash_is_map,
566 sck => spi_flash_sck,
567 cs_n => spi_flash_cs_n,
568 sdat_o => spi_flash_sdat_o,
569 sdat_oe => spi_flash_sdat_oe,
570 sdat_i => spi_flash_sdat_i
574 no_spi0_gen: if not HAS_SPI_FLASH generate
575 wb_spiflash_out.dat <= (others => '1');
576 wb_spiflash_out.ack <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
577 wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
580 xics0: entity work.xics
587 wb_in => wb_xics0_in,
588 wb_out => wb_xics0_out,
589 int_level_in => int_level_in,
590 core_irq_out => core_ext_irq
594 bram: if MEMORY_SIZE /= 0 generate
595 bram0: entity work.wishbone_bram_wrapper
597 MEMORY_SIZE => MEMORY_SIZE,
598 RAM_INIT_FILE => RAM_INIT_FILE
603 wishbone_in => wb_bram_in,
604 wishbone_out => wb_bram_out
608 no_bram: if MEMORY_SIZE = 0 generate
609 wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
610 wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
611 wb_bram_out.stall <= not wb_bram_out.ack;
614 -- DMI(debug bus) <-> JTAG bridge
615 dtm: entity work.dmi_dtm
621 sys_clk => system_clk,
622 sys_reset => rst_dtm,
623 dmi_addr => dmi_addr,
625 dmi_dout => dmi_dout,
632 dmi_intercon: process(dmi_addr, dmi_req,
633 dmi_wb_ack, dmi_wb_dout,
634 dmi_core_ack, dmi_core_dout)
636 -- DMI address map (each address is a full 64-bit register)
638 -- Offset: Size: Slave:
642 type slave_type is (SLAVE_WB,
645 variable slave : slave_type;
647 -- Simple address decoder
649 if std_match(dmi_addr, "000000--") then
651 elsif std_match(dmi_addr, "0001----") then
660 dmi_wb_req <= dmi_req;
661 dmi_ack <= dmi_wb_ack;
662 dmi_din <= dmi_wb_dout;
664 dmi_core_req <= dmi_req;
665 dmi_ack <= dmi_core_ack;
666 dmi_din <= dmi_core_dout;
669 dmi_din <= (others => '1');
673 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
678 -- Wishbone debug master (TODO: Add a DMI address decoder)
679 wishbone_debug: entity work.wishbone_debug_master
680 port map(clk => system_clk,
682 dmi_addr => dmi_addr(1 downto 0),
683 dmi_dout => dmi_wb_dout,
686 dmi_ack => dmi_wb_ack,
687 dmi_req => dmi_wb_req,
688 wb_in => wishbone_debug_in,
689 wb_out => wishbone_debug_out);
692 end architecture behaviour;