2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
10 use work.wishbone_types.all;
13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
17 -- 0x40000000: DRAM (when present)
18 -- 0x80000000: Block RAM (aliased & repeated)
23 -- 0xc0003000: UART1 (if any)
24 -- 0xc0004000: XICS ICP
25 -- 0xc0005000: XICS ICS
26 -- 0xc0006000: SPI Flash controller
27 -- 0xc8nnnnnn: External IO bus
28 -- 0xf0000000: Flash "ROM" mapping
29 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
32 -- 0xc8000000: LiteDRAM control (CSRs)
33 -- 0xc8020000: LiteEth CSRs (*)
34 -- 0xc8030000: LiteEth MMIO (*)
36 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
37 -- are actually decoded as a single wishbone which LiteEth will
38 -- internally split based on bit 16.
40 -- (**) DRAM init code is currently special and goes to the external
41 -- IO bus, this will be fixed when it's moved out of litedram and
42 -- into the main SoC once we have a common "firmware".
51 MEMORY_SIZE : natural;
52 RAM_INIT_FILE : string;
55 DISABLE_FLATTEN_CORE : boolean := false;
56 HAS_DRAM : boolean := false;
57 DRAM_SIZE : integer := 0;
58 DRAM_INIT_SIZE : integer := 0;
59 HAS_SPI_FLASH : boolean := false;
60 SPI_FLASH_DLINES : positive := 1;
61 SPI_FLASH_OFFSET : integer := 0;
62 SPI_FLASH_DEF_CKDV : natural := 2;
63 SPI_FLASH_DEF_QUAD : boolean := false;
64 LOG_LENGTH : natural := 512;
65 HAS_LITEETH : boolean := false;
66 UART0_IS_16550 : boolean := true;
67 HAS_UART1 : boolean := false
71 system_clk : in std_ulogic;
73 -- "Large" (64-bit) DRAM wishbone
74 wb_dram_in : out wishbone_master_out;
75 wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
77 -- "Small" (32-bit) external IO wishbone
78 wb_ext_io_in : out wb_io_master_out;
79 wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
80 wb_ext_is_dram_csr : out std_ulogic;
81 wb_ext_is_dram_init : out std_ulogic;
82 wb_ext_is_eth : out std_ulogic;
84 -- External interrupts
85 ext_irq_eth : in std_ulogic := '0';
88 uart0_txd : out std_ulogic;
89 uart0_rxd : in std_ulogic := '0';
92 uart1_txd : out std_ulogic;
93 uart1_rxd : in std_ulogic := '0';
96 spi_flash_sck : out std_ulogic;
97 spi_flash_cs_n : out std_ulogic;
98 spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
99 spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
100 spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
102 -- DRAM controller signals
103 alt_reset : in std_ulogic := '0'
107 architecture behaviour of soc is
109 -- Wishbone master signals:
110 signal wishbone_dcore_in : wishbone_slave_out;
111 signal wishbone_dcore_out : wishbone_master_out;
112 signal wishbone_icore_in : wishbone_slave_out;
113 signal wishbone_icore_out : wishbone_master_out;
114 signal wishbone_debug_in : wishbone_slave_out;
115 signal wishbone_debug_out : wishbone_master_out;
117 -- Arbiter array (ghdl doesnt' support assigning the array
118 -- elements in the entity instantiation)
119 constant NUM_WB_MASTERS : positive := 3;
120 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
121 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
123 -- Wishbone master (output of arbiter):
124 signal wb_master_in : wishbone_slave_out;
125 signal wb_master_out : wishbone_master_out;
127 -- Main "IO" bus, from main slave decoder to the latch
128 signal wb_io_in : wishbone_master_out;
129 signal wb_io_out : wishbone_slave_out;
131 -- Secondary (smaller) IO bus after the IO bus latch
132 signal wb_sio_out : wb_io_master_out;
133 signal wb_sio_in : wb_io_slave_out;
136 signal dram_at_0 : std_ulogic;
137 signal do_core_reset : std_ulogic;
138 signal wb_syscon_in : wb_io_master_out;
139 signal wb_syscon_out : wb_io_slave_out;
142 signal wb_uart0_in : wb_io_master_out;
143 signal wb_uart0_out : wb_io_slave_out;
144 signal uart0_dat8 : std_ulogic_vector(7 downto 0);
145 signal uart0_irq : std_ulogic;
148 signal wb_uart1_in : wb_io_master_out;
149 signal wb_uart1_out : wb_io_slave_out;
150 signal uart1_dat8 : std_ulogic_vector(7 downto 0);
151 signal uart1_irq : std_ulogic;
153 -- SPI Flash controller signals:
154 signal wb_spiflash_in : wb_io_master_out;
155 signal wb_spiflash_out : wb_io_slave_out;
156 signal wb_spiflash_is_reg : std_ulogic;
157 signal wb_spiflash_is_map : std_ulogic;
160 signal wb_xics_icp_in : wb_io_master_out;
161 signal wb_xics_icp_out : wb_io_slave_out;
162 signal wb_xics_ics_in : wb_io_master_out;
163 signal wb_xics_ics_out : wb_io_slave_out;
164 signal int_level_in : std_ulogic_vector(15 downto 0);
165 signal ics_to_icp : ics_to_icp_t;
166 signal core_ext_irq : std_ulogic;
168 -- Main memory signals:
169 signal wb_bram_in : wishbone_master_out;
170 signal wb_bram_out : wishbone_slave_out;
172 -- DMI debug bus signals
173 signal dmi_addr : std_ulogic_vector(7 downto 0);
174 signal dmi_din : std_ulogic_vector(63 downto 0);
175 signal dmi_dout : std_ulogic_vector(63 downto 0);
176 signal dmi_req : std_ulogic;
177 signal dmi_wr : std_ulogic;
178 signal dmi_ack : std_ulogic;
180 -- Per slave DMI signals
181 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
182 signal dmi_wb_req : std_ulogic;
183 signal dmi_wb_ack : std_ulogic;
184 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
185 signal dmi_core_req : std_ulogic;
186 signal dmi_core_ack : std_ulogic;
188 -- Delayed/latched resets and alt_reset
189 signal rst_core : std_ulogic := '1';
190 signal rst_uart : std_ulogic := '1';
191 signal rst_xics : std_ulogic := '1';
192 signal rst_spi : std_ulogic := '1';
193 signal rst_bram : std_ulogic := '1';
194 signal rst_dtm : std_ulogic := '1';
195 signal rst_wbar : std_ulogic := '1';
196 signal rst_wbdb : std_ulogic := '1';
197 signal alt_reset_d : std_ulogic;
200 type slave_io_type is (SLAVE_IO_SYSCON,
205 SLAVE_IO_SPI_FLASH_REG,
206 SLAVE_IO_SPI_FLASH_MAP,
209 signal slave_io_dbg : slave_io_type;
211 -- This is the component exported by the 16550 compatible
212 -- UART from FuseSoC.
214 component uart_top port (
215 wb_clk_i : in std_ulogic;
216 wb_rst_i : in std_ulogic;
217 wb_adr_i : in std_ulogic_vector(2 downto 0);
218 wb_dat_i : in std_ulogic_vector(7 downto 0);
219 wb_dat_o : out std_ulogic_vector(7 downto 0);
220 wb_we_i : in std_ulogic;
221 wb_stb_i : in std_ulogic;
222 wb_cyc_i : in std_ulogic;
223 wb_ack_o : out std_ulogic;
224 int_o : out std_ulogic;
225 stx_pad_o : out std_ulogic;
226 srx_pad_i : in std_ulogic;
227 rts_pad_o : out std_ulogic;
228 cts_pad_i : in std_ulogic;
229 dtr_pad_o : out std_ulogic;
230 dsr_pad_i : in std_ulogic;
231 ri_pad_i : in std_ulogic;
232 dcd_pad_i : in std_ulogic
237 resets: process(system_clk)
239 if rising_edge(system_clk) then
240 rst_core <= rst or do_core_reset;
248 alt_reset_d <= alt_reset;
253 processor: entity work.core
256 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
257 ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
258 LOG_LENGTH => LOG_LENGTH
263 alt_reset => alt_reset_d,
264 wishbone_insn_in => wishbone_icore_in,
265 wishbone_insn_out => wishbone_icore_out,
266 wishbone_data_in => wishbone_dcore_in,
267 wishbone_data_out => wishbone_dcore_out,
268 dmi_addr => dmi_addr(3 downto 0),
269 dmi_dout => dmi_core_dout,
272 dmi_ack => dmi_core_ack,
273 dmi_req => dmi_core_req,
274 ext_irq => core_ext_irq
277 -- Wishbone bus master arbiter & mux
278 wb_masters_out <= (0 => wishbone_dcore_out,
279 1 => wishbone_icore_out,
280 2 => wishbone_debug_out);
281 wishbone_dcore_in <= wb_masters_in(0);
282 wishbone_icore_in <= wb_masters_in(1);
283 wishbone_debug_in <= wb_masters_in(2);
284 wishbone_arbiter_0: entity work.wishbone_arbiter
286 NUM_MASTERS => NUM_WB_MASTERS
291 wb_masters_in => wb_masters_out,
292 wb_masters_out => wb_masters_in,
293 wb_slave_out => wb_master_out,
294 wb_slave_in => wb_master_in
297 -- Top level Wishbone slaves address decoder & mux
299 -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
306 slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
307 type slave_top_type is (SLAVE_TOP_BRAM,
310 variable slave_top : slave_top_type;
311 variable top_decode : std_ulogic_vector(3 downto 0);
313 -- Top-level address decoder
314 top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
315 slave_top := SLAVE_TOP_BRAM;
316 if std_match(top_decode, "0000") then
317 slave_top := SLAVE_TOP_BRAM;
318 elsif std_match(top_decode, "0001") then
319 slave_top := SLAVE_TOP_DRAM;
320 elsif std_match(top_decode, "01--") then
321 slave_top := SLAVE_TOP_DRAM;
322 elsif std_match(top_decode, "10--") then
323 slave_top := SLAVE_TOP_BRAM;
324 elsif std_match(top_decode, "11--") then
325 slave_top := SLAVE_TOP_IO;
328 -- Top level wishbone muxing.
329 wb_bram_in <= wb_master_out;
330 wb_bram_in.cyc <= '0';
331 wb_dram_in <= wb_master_out;
332 wb_dram_in.cyc <= '0';
333 wb_io_in <= wb_master_out;
336 when SLAVE_TOP_BRAM =>
337 wb_bram_in.cyc <= wb_master_out.cyc;
338 wb_master_in <= wb_bram_out;
339 when SLAVE_TOP_DRAM =>
341 wb_dram_in.cyc <= wb_master_out.cyc;
342 wb_master_in <= wb_dram_out;
344 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
345 wb_master_in.dat <= (others => '1');
346 wb_master_in.stall <= '0';
349 wb_io_in.cyc <= wb_master_out.cyc;
350 wb_master_in <= wb_io_out;
353 end process slave_top_intercon;
355 -- IO wishbone slave 64->32 bits converter
357 -- For timing reasons, this adds a one cycle latch on the way both
358 -- in and out. This relaxes timing and routing pressure on the "main"
359 -- memory bus by moving all simple IOs to a slower 32-bit bus.
361 -- This implementation is rather dumb at the moment, no stash buffer,
362 -- so we stall whenever that latch is busy. This can be improved.
364 slave_io_latch: process(system_clk)
366 type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
367 variable state : state_t;
370 variable has_top : boolean;
371 variable has_bot : boolean;
373 if rising_edge(system_clk) then
376 wb_io_out.ack <= '0';
377 wb_io_out.stall <= '0';
378 wb_sio_out.cyc <= '0';
379 wb_sio_out.stb <= '0';
385 -- Clear ACK in case it was set
386 wb_io_out.ack <= '0';
388 -- Do we have a cycle ?
389 if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
390 -- Stall master until we are done, we are't (yet) pipelining
391 -- this, it's all slow IOs.
392 wb_io_out.stall <= '1';
394 -- Start cycle downstream
395 wb_sio_out.cyc <= '1';
396 wb_sio_out.stb <= '1';
398 -- Copy write enable to IO out, copy address as well
399 wb_sio_out.we <= wb_io_in.we;
400 wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
402 -- Do we have a top word and/or a bottom word ?
403 has_top := wb_io_in.sel(7 downto 4) /= "0000";
404 has_bot := wb_io_in.sel(3 downto 0) /= "0000";
406 -- If we have a bottom word, handle it first, otherwise
407 -- send the top word down. XXX Split the actual mux out
408 -- and only generate a control signal.
410 if wb_io_in.we = '1' then
411 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
413 wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
416 state := WAIT_ACK_BOT;
418 if wb_io_in.we = '1' then
419 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
421 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
424 wb_sio_out.adr(2) <= '1';
427 state := WAIT_ACK_TOP;
431 -- If we aren't stalled by the device, clear stb
432 if wb_sio_in.stall = '0' then
433 wb_sio_out.stb <= '0';
437 if wb_sio_in.ack = '1' then
438 -- If it's a read, latch the data
439 if wb_sio_out.we = '0' then
440 wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
443 -- Do we have a "top" part as well ?
446 if wb_io_in.we = '1' then
447 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
449 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
451 -- Bump address and set STB
452 wb_sio_out.adr(2) <= '1';
453 wb_sio_out.stb <= '1';
456 state := WAIT_ACK_TOP;
458 -- We are done, ack up, clear cyc downstram
459 wb_sio_out.cyc <= '0';
461 -- And ack & unstall upstream
462 wb_io_out.ack <= '1';
463 wb_io_out.stall <= '0';
470 -- If we aren't stalled by the device, clear stb
471 if wb_sio_in.stall = '0' then
472 wb_sio_out.stb <= '0';
476 if wb_sio_in.ack = '1' then
477 -- If it's a read, latch the data
478 if wb_sio_out.we = '0' then
479 wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
482 -- We are done, ack up, clear cyc downstram
483 wb_sio_out.cyc <= '0';
485 -- And ack & unstall upstream
486 wb_io_out.ack <= '1';
487 wb_io_out.stall <= '0';
497 -- IO wishbone slave intercon.
499 slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
500 wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
502 variable slave_io : slave_io_type;
504 variable match : std_ulogic_vector(31 downto 12);
505 variable ext_valid : boolean;
508 -- Simple address decoder.
509 slave_io := SLAVE_IO_NONE;
510 match := "11" & wb_sio_out.adr(29 downto 12);
511 if std_match(match, x"FF---") and HAS_DRAM then
512 slave_io := SLAVE_IO_EXTERNAL;
513 elsif std_match(match, x"F----") then
514 slave_io := SLAVE_IO_SPI_FLASH_MAP;
515 elsif std_match(match, x"C0000") then
516 slave_io := SLAVE_IO_SYSCON;
517 elsif std_match(match, x"C0002") then
518 slave_io := SLAVE_IO_UART;
519 elsif std_match(match, x"C0003") then
520 slave_io := SLAVE_IO_UART1;
521 elsif std_match(match, x"C8---") then
522 slave_io := SLAVE_IO_EXTERNAL;
523 elsif std_match(match, x"C0004") then
524 slave_io := SLAVE_IO_ICP;
525 elsif std_match(match, x"C0005") then
526 slave_io := SLAVE_IO_ICS;
527 elsif std_match(match, x"C0006") then
528 slave_io := SLAVE_IO_SPI_FLASH_REG;
530 slave_io_dbg <= slave_io;
531 wb_uart0_in <= wb_sio_out;
532 wb_uart0_in.cyc <= '0';
533 wb_uart1_in <= wb_sio_out;
534 wb_uart1_in.cyc <= '0';
535 wb_spiflash_in <= wb_sio_out;
536 wb_spiflash_in.cyc <= '0';
537 wb_spiflash_is_reg <= '0';
538 wb_spiflash_is_map <= '0';
540 -- Only give xics 8 bits of wb addr (for now...)
541 wb_xics_icp_in <= wb_sio_out;
542 wb_xics_icp_in.adr <= (others => '0');
543 wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
544 wb_xics_icp_in.cyc <= '0';
545 wb_xics_ics_in <= wb_sio_out;
546 wb_xics_ics_in.adr <= (others => '0');
547 wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
548 wb_xics_ics_in.cyc <= '0';
550 wb_ext_io_in <= wb_sio_out;
551 wb_ext_io_in.cyc <= '0';
553 wb_syscon_in <= wb_sio_out;
554 wb_syscon_in.cyc <= '0';
556 wb_ext_is_dram_csr <= '0';
557 wb_ext_is_dram_init <= '0';
558 wb_ext_is_eth <= '0';
560 -- Default response, ack & return all 1's
561 wb_sio_in.dat <= (others => '1');
562 wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
563 wb_sio_in.stall <= '0';
566 when SLAVE_IO_EXTERNAL =>
567 -- Ext IO "chip selects"
569 -- DRAM init is special at 0xFF* so we just test the top
570 -- bit. Everything else is at 0xC8* so we test only bits
574 if wb_sio_out.adr(29) = '1' and HAS_DRAM then -- DRAM init is special
575 wb_ext_is_dram_init <= '1';
577 elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
578 wb_ext_is_dram_csr <= '1';
580 elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
581 wb_ext_is_eth <= '1';
583 elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
584 wb_ext_is_eth <= '1';
588 wb_ext_io_in.cyc <= wb_sio_out.cyc;
589 wb_sio_in <= wb_ext_io_out;
592 when SLAVE_IO_SYSCON =>
593 wb_syscon_in.cyc <= wb_sio_out.cyc;
594 wb_sio_in <= wb_syscon_out;
595 when SLAVE_IO_UART =>
596 wb_uart0_in.cyc <= wb_sio_out.cyc;
597 wb_sio_in <= wb_uart0_out;
599 wb_xics_icp_in.cyc <= wb_sio_out.cyc;
600 wb_sio_in <= wb_xics_icp_out;
602 wb_xics_ics_in.cyc <= wb_sio_out.cyc;
603 wb_sio_in <= wb_xics_ics_out;
604 when SLAVE_IO_UART1 =>
605 wb_uart1_in.cyc <= wb_sio_out.cyc;
606 wb_sio_in <= wb_uart1_out;
607 when SLAVE_IO_SPI_FLASH_MAP =>
608 -- Clear top bits so they don't make their way to the
610 wb_spiflash_in.adr(29 downto 28) <= "00";
611 wb_spiflash_in.cyc <= wb_sio_out.cyc;
612 wb_sio_in <= wb_spiflash_out;
613 wb_spiflash_is_map <= '1';
614 when SLAVE_IO_SPI_FLASH_REG =>
615 wb_spiflash_in.cyc <= wb_sio_out.cyc;
616 wb_sio_in <= wb_spiflash_out;
617 wb_spiflash_is_reg <= '1';
624 syscon0: entity work.syscon
627 HAS_DRAM => HAS_DRAM,
628 BRAM_SIZE => MEMORY_SIZE,
629 DRAM_SIZE => DRAM_SIZE,
630 DRAM_INIT_SIZE => DRAM_INIT_SIZE,
631 CLK_FREQ => CLK_FREQ,
632 HAS_SPI_FLASH => HAS_SPI_FLASH,
633 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
634 HAS_LITEETH => HAS_LITEETH,
635 UART0_IS_16550 => UART0_IS_16550,
636 HAS_UART1 => HAS_UART1
641 wishbone_in => wb_syscon_in,
642 wishbone_out => wb_syscon_out,
643 dram_at_0 => dram_at_0,
644 core_reset => do_core_reset,
645 soc_reset => open -- XXX TODO
651 -- Either potato (legacy) or 16550
653 uart0_pp: if not UART0_IS_16550 generate
654 uart0: entity work.pp_soc_uart
664 wb_adr_in => wb_uart0_in.adr(11 downto 0),
665 wb_dat_in => wb_uart0_in.dat(7 downto 0),
666 wb_dat_out => uart0_dat8,
667 wb_cyc_in => wb_uart0_in.cyc,
668 wb_stb_in => wb_uart0_in.stb,
669 wb_we_in => wb_uart0_in.we,
670 wb_ack_out => wb_uart0_out.ack
674 uart0_16550 : if UART0_IS_16550 generate
675 signal irq_l : std_ulogic;
679 wb_clk_i => system_clk,
680 wb_rst_i => rst_uart,
681 wb_adr_i => wb_uart0_in.adr(4 downto 2),
682 wb_dat_i => wb_uart0_in.dat(7 downto 0),
683 wb_dat_o => uart0_dat8,
684 wb_we_i => wb_uart0_in.we,
685 wb_stb_i => wb_uart0_in.stb,
686 wb_cyc_i => wb_uart0_in.cyc,
687 wb_ack_o => wb_uart0_out.ack,
689 stx_pad_o => uart0_txd,
690 srx_pad_i => uart0_rxd,
699 -- Add a register on the irq out, helps timing
700 uart0_irq_latch: process(system_clk)
702 if rising_edge(system_clk) then
708 wb_uart0_out.dat <= x"000000" & uart0_dat8;
709 wb_uart0_out.stall <= not wb_uart0_out.ack;
714 -- Always 16550 if it exists
716 uart1: if HAS_UART1 generate
717 signal irq_l : std_ulogic;
721 wb_clk_i => system_clk,
722 wb_rst_i => rst_uart,
723 wb_adr_i => wb_uart1_in.adr(4 downto 2),
724 wb_dat_i => wb_uart1_in.dat(7 downto 0),
725 wb_dat_o => uart1_dat8,
726 wb_we_i => wb_uart1_in.we,
727 wb_stb_i => wb_uart1_in.stb,
728 wb_cyc_i => wb_uart1_in.cyc,
729 wb_ack_o => wb_uart1_out.ack,
731 stx_pad_o => uart1_txd,
732 srx_pad_i => uart1_rxd,
740 -- Add a register on the irq out, helps timing
741 uart0_irq_latch: process(system_clk)
743 if rising_edge(system_clk) then
747 wb_uart1_out.dat <= x"000000" & uart1_dat8;
748 wb_uart1_out.stall <= not wb_uart1_out.ack;
751 no_uart1 : if not HAS_UART1 generate
752 wb_uart1_out.dat <= x"00000000";
753 wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
754 wb_uart1_out.stall <= '0';
757 spiflash_gen: if HAS_SPI_FLASH generate
758 spiflash: entity work.spi_flash_ctrl
760 DATA_LINES => SPI_FLASH_DLINES,
761 DEF_CLK_DIV => SPI_FLASH_DEF_CKDV,
762 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
767 wb_in => wb_spiflash_in,
768 wb_out => wb_spiflash_out,
769 wb_sel_reg => wb_spiflash_is_reg,
770 wb_sel_map => wb_spiflash_is_map,
771 sck => spi_flash_sck,
772 cs_n => spi_flash_cs_n,
773 sdat_o => spi_flash_sdat_o,
774 sdat_oe => spi_flash_sdat_oe,
775 sdat_i => spi_flash_sdat_i
779 no_spi0_gen: if not HAS_SPI_FLASH generate
780 wb_spiflash_out.dat <= (others => '1');
781 wb_spiflash_out.ack <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
782 wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
785 xics_icp: entity work.xics_icp
789 wb_in => wb_xics_icp_in,
790 wb_out => wb_xics_icp_out,
791 ics_in => ics_to_icp,
792 core_irq_out => core_ext_irq
795 xics_ics: entity work.xics_ics
803 wb_in => wb_xics_ics_in,
804 wb_out => wb_xics_ics_out,
805 int_level_in => int_level_in,
806 icp_out => ics_to_icp
809 -- Assign external interrupts
810 interrupts: process(all)
812 int_level_in <= (others => '0');
813 int_level_in(0) <= uart0_irq;
814 int_level_in(1) <= ext_irq_eth;
815 int_level_in(2) <= uart1_irq;
819 bram: if MEMORY_SIZE /= 0 generate
820 bram0: entity work.wishbone_bram_wrapper
822 MEMORY_SIZE => MEMORY_SIZE,
823 RAM_INIT_FILE => RAM_INIT_FILE
828 wishbone_in => wb_bram_in,
829 wishbone_out => wb_bram_out
833 no_bram: if MEMORY_SIZE = 0 generate
834 wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
835 wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
836 wb_bram_out.stall <= not wb_bram_out.ack;
839 -- DMI(debug bus) <-> JTAG bridge
840 dtm: entity work.dmi_dtm
846 sys_clk => system_clk,
847 sys_reset => rst_dtm,
848 dmi_addr => dmi_addr,
850 dmi_dout => dmi_dout,
857 dmi_intercon: process(dmi_addr, dmi_req,
858 dmi_wb_ack, dmi_wb_dout,
859 dmi_core_ack, dmi_core_dout)
861 -- DMI address map (each address is a full 64-bit register)
863 -- Offset: Size: Slave:
867 type slave_type is (SLAVE_WB,
870 variable slave : slave_type;
872 -- Simple address decoder
874 if std_match(dmi_addr, "000000--") then
876 elsif std_match(dmi_addr, "0001----") then
885 dmi_wb_req <= dmi_req;
886 dmi_ack <= dmi_wb_ack;
887 dmi_din <= dmi_wb_dout;
889 dmi_core_req <= dmi_req;
890 dmi_ack <= dmi_core_ack;
891 dmi_din <= dmi_core_dout;
894 dmi_din <= (others => '1');
898 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
903 -- Wishbone debug master (TODO: Add a DMI address decoder)
904 wishbone_debug: entity work.wishbone_debug_master
905 port map(clk => system_clk,
907 dmi_addr => dmi_addr(1 downto 0),
908 dmi_dout => dmi_wb_dout,
911 dmi_ack => dmi_wb_ack,
912 dmi_req => dmi_wb_req,
913 wb_in => wishbone_debug_in,
914 wb_out => wishbone_debug_out);
917 end architecture behaviour;