soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5 use std.textio.all;
   6 use std.env.stop;
   7
   8 library work;
   9 use work.common.all;
  10 use work.wishbone_types.all;
  11
  12
  13 -- 0x00000000: Main memory (1 MB)
  14 -- 0xc0002000: UART0 (for host communication)
  15 -- 0xc0004000: XICS ICP
  16 entity soc is
  17     generic (
  18         MEMORY_SIZE   : positive;
  19         RAM_INIT_FILE : string;
  20         RESET_LOW     : boolean;
  21         SIM           : boolean;
  22         DISABLE_FLATTEN_CORE : boolean := false
  23         );
  24     port(
  25         rst          : in  std_ulogic;
  26         system_clk   : in  std_ulogic;
  27
  28         -- UART0 signals:
  29         uart0_txd    : out std_ulogic;
  30         uart0_rxd    : in  std_ulogic;
  31         alt_reset    : in std_ulogic
  32         );
  33 end entity soc;
  34
  35 architecture behaviour of soc is
  36
  37     -- Wishbone master signals:
  38     signal wishbone_dcore_in : wishbone_slave_out;
  39     signal wishbone_dcore_out : wishbone_master_out;
  40     signal wishbone_icore_in : wishbone_slave_out;
  41     signal wishbone_icore_out : wishbone_master_out;
  42     signal wishbone_debug_in : wishbone_slave_out;
  43     signal wishbone_debug_out : wishbone_master_out;
  44
  45     -- Arbiter array (ghdl doesnt' support assigning the array
  46     -- elements in the entity instantiation)
  47     constant NUM_WB_MASTERS : positive := 3;
  48     signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
  49     signal wb_masters_in  : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
  50
  51     -- Wishbone master (output of arbiter):
  52     signal wb_master_in : wishbone_slave_out;
  53     signal wb_master_out : wishbone_master_out;
  54
  55     -- UART0 signals:
  56     signal wb_uart0_in   : wishbone_master_out;
  57     signal wb_uart0_out  : wishbone_slave_out;
  58     signal uart_dat8     : std_ulogic_vector(7 downto 0);
  59
  60     -- XICS0 signals:
  61     signal wb_xics0_in   : wishbone_master_out;
  62     signal wb_xics0_out  : wishbone_slave_out;
  63     signal int_level_in  : std_ulogic_vector(15 downto 0);
  64
  65     signal xics_to_execute1 : XicsToExecute1Type;
  66
  67     -- Main memory signals:
  68     signal wb_bram_in     : wishbone_master_out;
  69     signal wb_bram_out    : wishbone_slave_out;
  70     constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
  71
  72     -- DMI debug bus signals
  73     signal dmi_addr     : std_ulogic_vector(7 downto 0);
  74     signal dmi_din      : std_ulogic_vector(63 downto 0);
  75     signal dmi_dout     : std_ulogic_vector(63 downto 0);
  76     signal dmi_req      : std_ulogic;
  77     signal dmi_wr       : std_ulogic;
  78     signal dmi_ack      : std_ulogic;
  79
  80     -- Per slave DMI signals
  81     signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
  82     signal dmi_wb_req   : std_ulogic;
  83     signal dmi_wb_ack   : std_ulogic;
  84     signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
  85     signal dmi_core_req   : std_ulogic;
  86     signal dmi_core_ack   : std_ulogic;
  87 begin
  88
  89     -- Processor core
  90     processor: entity work.core
  91         generic map(
  92             SIM => SIM,
  93             DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
  94             ALT_RESET_ADDRESS => (15 downto 0 => '0', others => '1')
  95             )
  96         port map(
  97             clk => system_clk,
  98             rst => rst,
  99             alt_reset => alt_reset,
 100             wishbone_insn_in => wishbone_icore_in,
 101             wishbone_insn_out => wishbone_icore_out,
 102             wishbone_data_in => wishbone_dcore_in,
 103             wishbone_data_out => wishbone_dcore_out,
 104             dmi_addr => dmi_addr(3 downto 0),
 105             dmi_dout => dmi_core_dout,
 106             dmi_din => dmi_dout,
 107             dmi_wr => dmi_wr,
 108             dmi_ack => dmi_core_ack,
 109             dmi_req => dmi_core_req,
 110             xics_in => xics_to_execute1
 111             );
 112
 113     -- Wishbone bus master arbiter & mux
 114     wb_masters_out <= (0 => wishbone_dcore_out,
 115                        1 => wishbone_icore_out,
 116                        2 => wishbone_debug_out);
 117     wishbone_dcore_in <= wb_masters_in(0);
 118     wishbone_icore_in <= wb_masters_in(1);
 119     wishbone_debug_in <= wb_masters_in(2);
 120     wishbone_arbiter_0: entity work.wishbone_arbiter
 121         generic map(
 122             NUM_MASTERS => NUM_WB_MASTERS
 123             )
 124         port map(
 125             clk => system_clk, rst => rst,
 126             wb_masters_in => wb_masters_out,
 127             wb_masters_out => wb_masters_in,
 128             wb_slave_out => wb_master_out,
 129             wb_slave_in => wb_master_in
 130             );
 131
 132     -- Wishbone slaves address decoder & mux
 133     slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
 134         -- Selected slave
 135         type slave_type is (SLAVE_UART_0,
 136                             SLAVE_MEMORY,
 137                             SLAVE_ICP_0,
 138                             SLAVE_NONE);
 139         variable slave : slave_type;
 140     begin
 141         -- Simple address decoder.
 142         slave := SLAVE_NONE;
 143         if wb_master_out.adr(31 downto 24) = x"00" then
 144             slave := SLAVE_MEMORY;
 145         elsif wb_master_out.adr(31 downto 24) = x"c0" then
 146             if wb_master_out.adr(23 downto 12) = x"002" then
 147                 slave := SLAVE_UART_0;
 148             end if;
 149             if wb_master_out.adr(23 downto 12) = x"004" then
 150                 slave := SLAVE_ICP_0;
 151             end if;
 152         end if;
 153
 154         -- Wishbone muxing. Defaults:
 155         wb_bram_in <= wb_master_out;
 156         wb_bram_in.cyc  <= '0';
 157         wb_uart0_in <= wb_master_out;
 158         wb_uart0_in.cyc <= '0';
 159
 160          -- Only give xics 8 bits of wb addr
 161         wb_xics0_in <= wb_master_out;
 162         wb_xics0_in.adr <= (others => '0');
 163         wb_xics0_in.adr(7 downto 0) <= wb_master_out.adr(7 downto 0);
 164         wb_xics0_in.cyc  <= '0';
 165         case slave is
 166         when SLAVE_MEMORY =>
 167             wb_bram_in.cyc <= wb_master_out.cyc;
 168             wb_master_in <= wb_bram_out;
 169         when SLAVE_UART_0 =>
 170             wb_uart0_in.cyc <= wb_master_out.cyc;
 171             wb_master_in <= wb_uart0_out;
 172         when SLAVE_ICP_0 =>
 173             wb_xics0_in.cyc <= wb_master_out.cyc;
 174             wb_master_in <= wb_xics0_out;
 175         when others =>
 176             wb_master_in.dat <= (others => '1');
 177             wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
 178             wb_master_in.stall <= '0';
 179         end case;
 180     end process slave_intercon;
 181
 182     -- Simulated memory and UART
 183
 184     -- UART0 wishbone slave
 185     -- XXX FIXME: Need a proper wb64->wb8 adapter that
 186     --            converts SELs into low address bits and muxes
 187     --            data accordingly (either that or rejects large
 188     --            cycles).
 189     uart0: entity work.pp_soc_uart
 190         generic map(
 191             FIFO_DEPTH => 32
 192             )
 193         port map(
 194             clk => system_clk,
 195             reset => rst,
 196             txd => uart0_txd,
 197             rxd => uart0_rxd,
 198             irq => int_level_in(0),
 199             wb_adr_in => wb_uart0_in.adr(11 downto 0),
 200             wb_dat_in => wb_uart0_in.dat(7 downto 0),
 201             wb_dat_out => uart_dat8,
 202             wb_cyc_in => wb_uart0_in.cyc,
 203             wb_stb_in => wb_uart0_in.stb,
 204             wb_we_in => wb_uart0_in.we,
 205             wb_ack_out => wb_uart0_out.ack
 206             );
 207     wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
 208     wb_uart0_out.stall <= '0' when wb_uart0_in.cyc = '0' else not wb_uart0_out.ack;
 209
 210     xics0: entity work.xics
 211         generic map(
 212             LEVEL_NUM => 16
 213             )
 214         port map(
 215             clk => system_clk,
 216             rst => rst,
 217             wb_in => wb_xics0_in,
 218             wb_out => wb_xics0_out,
 219             int_level_in => int_level_in,
 220             e_out => xics_to_execute1
 221             );
 222
 223     -- BRAM Memory slave
 224     bram0: entity work.wishbone_bram_wrapper
 225         generic map(
 226             MEMORY_SIZE   => MEMORY_SIZE,
 227             RAM_INIT_FILE => RAM_INIT_FILE
 228             )
 229         port map(
 230             clk => system_clk,
 231             rst => rst,
 232             wishbone_in => wb_bram_in,
 233             wishbone_out => wb_bram_out
 234             );
 235
 236     -- DMI(debug bus) <-> JTAG bridge
 237     dtm: entity work.dmi_dtm
 238         generic map(
 239             ABITS => 8,
 240             DBITS => 64
 241             )
 242         port map(
 243             sys_clk     => system_clk,
 244             sys_reset   => rst,
 245             dmi_addr    => dmi_addr,
 246             dmi_din     => dmi_din,
 247             dmi_dout    => dmi_dout,
 248             dmi_req     => dmi_req,
 249             dmi_wr      => dmi_wr,
 250             dmi_ack     => dmi_ack
 251             );
 252
 253     -- DMI interconnect
 254     dmi_intercon: process(dmi_addr, dmi_req,
 255                           dmi_wb_ack, dmi_wb_dout,
 256                           dmi_core_ack, dmi_core_dout)
 257
 258         -- DMI address map (each address is a full 64-bit register)
 259         --
 260         -- Offset:   Size:    Slave:
 261         --  0         4       Wishbone
 262         -- 10        16       Core
 263
 264         type slave_type is (SLAVE_WB,
 265                             SLAVE_CORE,
 266                             SLAVE_NONE);
 267         variable slave : slave_type;
 268     begin
 269         -- Simple address decoder
 270         slave := SLAVE_NONE;
 271         if std_match(dmi_addr, "000000--") then
 272             slave := SLAVE_WB;
 273         elsif std_match(dmi_addr, "0001----") then
 274             slave := SLAVE_CORE;
 275         end if;
 276
 277         -- DMI muxing
 278         dmi_wb_req <= '0';
 279         dmi_core_req <= '0';
 280         case slave is
 281         when SLAVE_WB =>
 282             dmi_wb_req <= dmi_req;
 283             dmi_ack <= dmi_wb_ack;
 284             dmi_din <= dmi_wb_dout;
 285         when SLAVE_CORE =>
 286             dmi_core_req <= dmi_req;
 287             dmi_ack <= dmi_core_ack;
 288             dmi_din <= dmi_core_dout;
 289         when others =>
 290             dmi_ack <= dmi_req;
 291             dmi_din <= (others => '1');
 292         end case;
 293
 294         -- SIM magic exit
 295         if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
 296             stop;
 297         end if;
 298     end process;
 299
 300     -- Wishbone debug master (TODO: Add a DMI address decoder)
 301     wishbone_debug: entity work.wishbone_debug_master
 302         port map(clk => system_clk, rst => rst,
 303                  dmi_addr => dmi_addr(1 downto 0),
 304                  dmi_dout => dmi_wb_dout,
 305                  dmi_din => dmi_dout,
 306                  dmi_wr => dmi_wr,
 307                  dmi_ack => dmi_wb_ack,
 308                  dmi_req => dmi_wb_req,
 309                  wb_in => wishbone_debug_in,
 310                  wb_out => wishbone_debug_out);
 311
 312
 313 end architecture behaviour;