2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
10 use work.wishbone_types.all;
13 -- 0x00000000: Main memory (1 MB)
14 -- 0xc0002000: UART0 (for host communication)
17 MEMORY_SIZE : positive;
18 RAM_INIT_FILE : string;
24 system_clk : in std_ulogic;
27 uart0_txd : out std_ulogic;
28 uart0_rxd : in std_ulogic;
30 -- Misc (to use for things like LEDs)
31 core_terminated : out std_ulogic
35 architecture behaviour of soc is
37 -- Wishbone master signals:
38 signal wishbone_dcore_in : wishbone_slave_out;
39 signal wishbone_dcore_out : wishbone_master_out;
40 signal wishbone_icore_in : wishbone_slave_out;
41 signal wishbone_icore_out : wishbone_master_out;
42 signal wishbone_debug_in : wishbone_slave_out;
43 signal wishbone_debug_out : wishbone_master_out;
45 -- Wishbone master (output of arbiter):
46 signal wb_master_in : wishbone_slave_out;
47 signal wb_master_out : wishbone_master_out;
50 signal wb_uart0_in : wishbone_master_out;
51 signal wb_uart0_out : wishbone_slave_out;
52 signal uart_dat8 : std_ulogic_vector(7 downto 0);
54 -- Main memory signals:
55 signal wb_bram_in : wishbone_master_out;
56 signal wb_bram_out : wishbone_slave_out;
57 constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
59 -- DMI debug bus signals
60 signal dmi_addr : std_ulogic_vector(7 downto 0);
61 signal dmi_din : std_ulogic_vector(63 downto 0);
62 signal dmi_dout : std_ulogic_vector(63 downto 0);
63 signal dmi_req : std_ulogic;
64 signal dmi_wr : std_ulogic;
65 signal dmi_ack : std_ulogic;
67 -- Per slave DMI signals
68 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
69 signal dmi_wb_req : std_ulogic;
70 signal dmi_wb_ack : std_ulogic;
71 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
72 signal dmi_core_req : std_ulogic;
73 signal dmi_core_ack : std_ulogic;
77 processor: entity work.core
84 wishbone_insn_in => wishbone_icore_in,
85 wishbone_insn_out => wishbone_icore_out,
86 wishbone_data_in => wishbone_dcore_in,
87 wishbone_data_out => wishbone_dcore_out,
88 dmi_addr => dmi_addr(3 downto 0),
89 dmi_dout => dmi_core_dout,
92 dmi_ack => dmi_core_ack,
93 dmi_req => dmi_core_req
96 -- Wishbone bus master arbiter & mux
97 wishbone_arbiter_0: entity work.wishbone_arbiter
99 clk => system_clk, rst => rst,
100 wb1_in => wishbone_dcore_out, wb1_out => wishbone_dcore_in,
101 wb2_in => wishbone_icore_out, wb2_out => wishbone_icore_in,
102 wb3_in => wishbone_debug_out, wb3_out => wishbone_debug_in,
103 wb_out => wb_master_out, wb_in => wb_master_in
106 -- Wishbone slaves address decoder & mux
107 slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
109 type slave_type is (SLAVE_UART,
112 variable slave : slave_type;
114 -- Simple address decoder
116 if wb_master_out.adr(63 downto 24) = x"0000000000" then
117 slave := SLAVE_MEMORY;
118 elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then
119 if wb_master_out.adr(15 downto 12) = x"2" then
124 -- Wishbone muxing. Defaults:
125 wb_bram_in <= wb_master_out;
126 wb_bram_in.cyc <= '0';
127 wb_uart0_in <= wb_master_out;
128 wb_uart0_in.cyc <= '0';
131 wb_bram_in.cyc <= wb_master_out.cyc;
132 wb_master_in <= wb_bram_out;
134 wb_uart0_in.cyc <= wb_master_out.cyc;
135 wb_master_in <= wb_uart0_out;
137 wb_master_in.dat <= (others => '1');
138 wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
140 end process slave_intercon;
142 -- Simulated memory and UART
144 -- UART0 wishbone slave
145 -- XXX FIXME: Need a proper wb64->wb8 adapter that
146 -- converts SELs into low address bits and muxes
147 -- data accordingly (either that or rejects large
149 uart0: entity work.pp_soc_uart
158 wb_adr_in => wb_uart0_in.adr(11 downto 0),
159 wb_dat_in => wb_uart0_in.dat(7 downto 0),
160 wb_dat_out => uart_dat8,
161 wb_cyc_in => wb_uart0_in.cyc,
162 wb_stb_in => wb_uart0_in.stb,
163 wb_we_in => wb_uart0_in.we,
164 wb_ack_out => wb_uart0_out.ack
166 wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
169 bram0: entity work.mw_soc_memory
171 MEMORY_SIZE => MEMORY_SIZE,
172 RAM_INIT_FILE => RAM_INIT_FILE
177 wishbone_in => wb_bram_in,
178 wishbone_out => wb_bram_out
181 -- DMI(debug bus) <-> JTAG bridge
182 dtm: entity work.dmi_dtm
188 sys_clk => system_clk,
190 dmi_addr => dmi_addr,
192 dmi_dout => dmi_dout,
199 dmi_intercon: process(dmi_addr, dmi_req,
200 dmi_wb_ack, dmi_wb_dout,
201 dmi_core_ack, dmi_core_dout)
203 -- DMI address map (each address is a full 64-bit register)
205 -- Offset: Size: Slave:
209 type slave_type is (SLAVE_WB,
212 variable slave : slave_type;
214 -- Simple address decoder
216 if std_match(dmi_addr, "000000--") then
218 elsif std_match(dmi_addr, "0001----") then
227 dmi_wb_req <= dmi_req;
228 dmi_ack <= dmi_wb_ack;
229 dmi_din <= dmi_wb_dout;
231 dmi_core_req <= dmi_req;
232 dmi_ack <= dmi_core_ack;
233 dmi_din <= dmi_core_dout;
236 dmi_din <= (others => '1');
240 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
245 -- Wishbone debug master (TODO: Add a DMI address decoder)
246 wishbone_debug: entity work.wishbone_debug_master
247 port map(clk => system_clk, rst => rst,
248 dmi_addr => dmi_addr(1 downto 0),
249 dmi_dout => dmi_wb_dout,
252 dmi_ack => dmi_wb_ack,
253 dmi_req => dmi_wb_req,
254 wb_in => wishbone_debug_in,
255 wb_out => wishbone_debug_out);
258 end architecture behaviour;