soc.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5 use std.textio.all;
   6 use std.env.stop;
   7
   8 library work;
   9 use work.common.all;
  10 use work.wishbone_types.all;
  11
  12
  13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
  14 --
  15 -- Main bus:
  16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
  17 -- 0x40000000: DRAM (when present)
  18 -- 0x80000000: Block RAM (aliased & repeated)
  19
  20 -- IO Bus:
  21 -- 0xc0000000: SYSCON
  22 -- 0xc0002000: UART0
  23 -- 0xc0004000: XICS ICP
  24 -- 0xc0006000: SPI Flash controller
  25 -- 0xc0100000: LiteDRAM control (CSRs)
  26 -- 0xf0000000: Flash "ROM" mapping
  27 -- 0xff000000: DRAM init code (if any) or flash ROM
  28
  29 entity soc is
  30     generic (
  31         MEMORY_SIZE        : natural;
  32         RAM_INIT_FILE      : string;
  33         RESET_LOW          : boolean;
  34         CLK_FREQ           : positive;
  35         SIM                : boolean;
  36         DISABLE_FLATTEN_CORE : boolean := false;
  37         HAS_DRAM           : boolean  := false;
  38         DRAM_SIZE          : integer := 0;
  39         DRAM_INIT_SIZE     : integer := 0;
  40         HAS_SPI_FLASH      : boolean := false;
  41         SPI_FLASH_DLINES   : positive := 1;
  42         SPI_FLASH_OFFSET   : integer := 0;
  43         SPI_FLASH_DEF_CKDV : natural := 2;
  44         SPI_FLASH_DEF_QUAD : boolean := false
  45         );
  46     port(
  47         rst          : in  std_ulogic;
  48         system_clk   : in  std_ulogic;
  49
  50         -- DRAM controller signals
  51         wb_dram_in       : out wishbone_master_out;
  52         wb_dram_out      : in wishbone_slave_out;
  53         wb_dram_ctrl_in  : out wb_io_master_out;
  54         wb_dram_ctrl_out : in wb_io_slave_out;
  55         wb_dram_is_csr   : out std_ulogic;
  56         wb_dram_is_init  : out std_ulogic;
  57
  58         -- UART0 signals:
  59         uart0_txd    : out std_ulogic;
  60         uart0_rxd    : in  std_ulogic;
  61
  62         -- SPI Flash signals
  63         spi_flash_sck     : out std_ulogic;
  64         spi_flash_cs_n    : out std_ulogic;
  65         spi_flash_sdat_o  : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
  66         spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
  67         spi_flash_sdat_i  : in  std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
  68
  69         -- DRAM controller signals
  70         alt_reset    : in std_ulogic
  71         );
  72 end entity soc;
  73
  74 architecture behaviour of soc is
  75
  76     -- Wishbone master signals:
  77     signal wishbone_dcore_in  : wishbone_slave_out;
  78     signal wishbone_dcore_out : wishbone_master_out;
  79     signal wishbone_icore_in  : wishbone_slave_out;
  80     signal wishbone_icore_out : wishbone_master_out;
  81     signal wishbone_debug_in : wishbone_slave_out;
  82     signal wishbone_debug_out : wishbone_master_out;
  83
  84     -- Arbiter array (ghdl doesnt' support assigning the array
  85     -- elements in the entity instantiation)
  86     constant NUM_WB_MASTERS : positive := 3;
  87     signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
  88     signal wb_masters_in  : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
  89
  90     -- Wishbone master (output of arbiter):
  91     signal wb_master_in       : wishbone_slave_out;
  92     signal wb_master_out      : wishbone_master_out;
  93
  94     -- Main "IO" bus, from main slave decoder to the latch
  95     signal wb_io_in     : wishbone_master_out;
  96     signal wb_io_out    : wishbone_slave_out;
  97
  98     -- Secondary (smaller) IO bus after the IO bus latch
  99     signal wb_sio_out    : wb_io_master_out;
 100     signal wb_sio_in     : wb_io_slave_out;
 101
 102     -- Syscon signals
 103     signal dram_at_0     : std_ulogic;
 104     signal do_core_reset    : std_ulogic;
 105     signal wb_syscon_in  : wb_io_master_out;
 106     signal wb_syscon_out : wb_io_slave_out;
 107
 108     -- UART0 signals:
 109     signal wb_uart0_in   : wb_io_master_out;
 110     signal wb_uart0_out  : wb_io_slave_out;
 111     signal uart_dat8     : std_ulogic_vector(7 downto 0);
 112
 113     -- SPI Flash controller signals:
 114     signal wb_spiflash_in     : wb_io_master_out;
 115     signal wb_spiflash_out    : wb_io_slave_out;
 116     signal wb_spiflash_is_reg : std_ulogic;
 117     signal wb_spiflash_is_map : std_ulogic;
 118
 119     -- XICS0 signals:
 120     signal wb_xics0_in   : wb_io_master_out;
 121     signal wb_xics0_out  : wb_io_slave_out;
 122     signal int_level_in  : std_ulogic_vector(15 downto 0);
 123
 124     signal core_ext_irq  : std_ulogic;
 125
 126     -- Main memory signals:
 127     signal wb_bram_in     : wishbone_master_out;
 128     signal wb_bram_out    : wishbone_slave_out;
 129
 130     -- DMI debug bus signals
 131     signal dmi_addr     : std_ulogic_vector(7 downto 0);
 132     signal dmi_din      : std_ulogic_vector(63 downto 0);
 133     signal dmi_dout     : std_ulogic_vector(63 downto 0);
 134     signal dmi_req      : std_ulogic;
 135     signal dmi_wr       : std_ulogic;
 136     signal dmi_ack      : std_ulogic;
 137
 138     -- Per slave DMI signals
 139     signal dmi_wb_dout  : std_ulogic_vector(63 downto 0);
 140     signal dmi_wb_req   : std_ulogic;
 141     signal dmi_wb_ack   : std_ulogic;
 142     signal dmi_core_dout  : std_ulogic_vector(63 downto 0);
 143     signal dmi_core_req   : std_ulogic;
 144     signal dmi_core_ack   : std_ulogic;
 145
 146     -- Delayed/latched resets and alt_reset
 147     signal rst_core    : std_ulogic := '1';
 148     signal rst_uart    : std_ulogic := '1';
 149     signal rst_xics    : std_ulogic := '1';
 150     signal rst_spi     : std_ulogic := '1';
 151     signal rst_bram    : std_ulogic := '1';
 152     signal rst_dtm     : std_ulogic := '1';
 153     signal rst_wbar    : std_ulogic := '1';
 154     signal rst_wbdb    : std_ulogic := '1';
 155     signal alt_reset_d : std_ulogic;
 156
 157         -- IO branch split:
 158         type slave_io_type is (SLAVE_IO_SYSCON,
 159                                SLAVE_IO_UART,
 160                                SLAVE_IO_DRAM_INIT,
 161                                SLAVE_IO_DRAM_CSR,
 162                                SLAVE_IO_ICP_0,
 163                                SLAVE_IO_SPI_FLASH_REG,
 164                                SLAVE_IO_SPI_FLASH_MAP,
 165                                SLAVE_IO_NONE);
 166     signal slave_io_dbg : slave_io_type;
 167 begin
 168
 169     resets: process(system_clk)
 170     begin
 171         if rising_edge(system_clk) then
 172             rst_core    <= rst or do_core_reset;
 173             rst_uart    <= rst;
 174             rst_spi     <= rst;
 175             rst_xics    <= rst;
 176             rst_bram    <= rst;
 177             rst_dtm     <= rst;
 178             rst_wbar    <= rst;
 179             rst_wbdb    <= rst;
 180             alt_reset_d <= alt_reset;
 181         end if;
 182     end process;
 183
 184     -- Processor core
 185     processor: entity work.core
 186         generic map(
 187             SIM => SIM,
 188             DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
 189             ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1')
 190             )
 191         port map(
 192             clk => system_clk,
 193             rst => rst_core,
 194             alt_reset => alt_reset_d,
 195             wishbone_insn_in => wishbone_icore_in,
 196             wishbone_insn_out => wishbone_icore_out,
 197             wishbone_data_in => wishbone_dcore_in,
 198             wishbone_data_out => wishbone_dcore_out,
 199             dmi_addr => dmi_addr(3 downto 0),
 200             dmi_dout => dmi_core_dout,
 201             dmi_din => dmi_dout,
 202             dmi_wr => dmi_wr,
 203             dmi_ack => dmi_core_ack,
 204             dmi_req => dmi_core_req,
 205             ext_irq => core_ext_irq
 206             );
 207
 208     -- Wishbone bus master arbiter & mux
 209     wb_masters_out <= (0 => wishbone_dcore_out,
 210                        1 => wishbone_icore_out,
 211                        2 => wishbone_debug_out);
 212     wishbone_dcore_in <= wb_masters_in(0);
 213     wishbone_icore_in <= wb_masters_in(1);
 214     wishbone_debug_in <= wb_masters_in(2);
 215     wishbone_arbiter_0: entity work.wishbone_arbiter
 216         generic map(
 217             NUM_MASTERS => NUM_WB_MASTERS
 218             )
 219         port map(
 220             clk => system_clk,
 221             rst => rst_wbar,
 222             wb_masters_in => wb_masters_out,
 223             wb_masters_out => wb_masters_in,
 224             wb_slave_out => wb_master_out,
 225             wb_slave_in => wb_master_in
 226             );
 227
 228     -- Top level Wishbone slaves address decoder & mux
 229     --
 230     -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
 231     -- 0000  - BRAM
 232     -- 0001  - DRAM
 233     -- 01xx  - DRAM
 234     -- 10xx  - BRAM
 235     -- 11xx  - IO
 236     --
 237     slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
 238         type slave_top_type is (SLAVE_TOP_BRAM,
 239                                 SLAVE_TOP_DRAM,
 240                                 SLAVE_TOP_IO);
 241         variable slave_top : slave_top_type;
 242         variable top_decode : std_ulogic_vector(3 downto 0);
 243     begin
 244         -- Top-level address decoder
 245         top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
 246         slave_top := SLAVE_TOP_BRAM;
 247         if    std_match(top_decode, "0000") then
 248             slave_top := SLAVE_TOP_BRAM;
 249         elsif std_match(top_decode, "0001") then
 250             slave_top := SLAVE_TOP_DRAM;
 251         elsif std_match(top_decode, "01--") then
 252             slave_top := SLAVE_TOP_DRAM;
 253         elsif std_match(top_decode, "10--") then
 254             slave_top := SLAVE_TOP_BRAM;
 255         elsif std_match(top_decode, "11--") then
 256             slave_top := SLAVE_TOP_IO;
 257         end if;
 258
 259         -- Top level wishbone muxing.
 260         wb_bram_in <= wb_master_out;
 261         wb_bram_in.cyc  <= '0';
 262         wb_dram_in <= wb_master_out;
 263         wb_dram_in.cyc  <= '0';
 264         wb_io_in <= wb_master_out;
 265         wb_io_in.cyc  <= '0';
 266         case slave_top is
 267         when SLAVE_TOP_BRAM =>
 268             wb_bram_in.cyc <= wb_master_out.cyc;
 269             wb_master_in <= wb_bram_out;
 270         when SLAVE_TOP_DRAM =>
 271             wb_dram_in.cyc <= wb_master_out.cyc;
 272             wb_master_in <= wb_dram_out;
 273         when SLAVE_TOP_IO =>
 274             wb_io_in.cyc <= wb_master_out.cyc;
 275             wb_master_in <= wb_io_out;
 276         end case;
 277     end process slave_top_intercon;
 278
 279     -- IO wishbone slave 64->32 bits converter
 280     --
 281     -- For timing reasons, this adds a one cycle latch on the way both
 282     -- in and out. This relaxes timing and routing pressure on the "main"
 283     -- memory bus by moving all simple IOs to a slower 32-bit bus.
 284     --
 285     -- This implementation is rather dumb at the moment, no stash buffer,
 286     -- so we stall whenever that latch is busy. This can be improved.
 287     --
 288     slave_io_latch: process(system_clk)
 289         -- State
 290         type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
 291         variable state : state_t;
 292
 293         -- Misc
 294         variable has_top : boolean;
 295         variable has_bot : boolean;
 296     begin
 297         if rising_edge(system_clk) then
 298             if (rst) then
 299                 state := IDLE;
 300                 wb_io_out.ack <= '0';
 301                 wb_io_out.stall <= '0';
 302                 wb_sio_out.cyc <= '0';
 303                 wb_sio_out.stb <= '0';
 304                 has_top := false;
 305                 has_bot := false;
 306             else
 307                 case state is
 308                 when IDLE =>
 309                     -- Clear ACK in case it was set
 310                     wb_io_out.ack <= '0';
 311
 312                     -- Do we have a cycle ?
 313                     if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
 314                         -- Stall master until we are done, we are't (yet) pipelining
 315                         -- this, it's all slow IOs.
 316                         wb_io_out.stall <= '1';
 317
 318                         -- Start cycle downstream
 319                         wb_sio_out.cyc <= '1';
 320                         wb_sio_out.stb <= '1';
 321
 322                         -- Copy write enable to IO out, copy address as well
 323                         wb_sio_out.we <= wb_io_in.we;
 324                         wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
 325
 326                         -- Do we have a top word and/or a bottom word ?
 327                         has_top := wb_io_in.sel(7 downto 4) /= "0000";
 328                         has_bot := wb_io_in.sel(3 downto 0) /= "0000";
 329
 330                         -- If we have a bottom word, handle it first, otherwise
 331                         -- send the top word down. XXX Split the actual mux out
 332                         -- and only generate a control signal.
 333                         if has_bot then
 334                             if wb_io_in.we = '1' then
 335                                 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
 336                             end if;
 337                             wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
 338
 339                             -- Wait for ack
 340                             state := WAIT_ACK_BOT;
 341                         else
 342                             if wb_io_in.we = '1' then
 343                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 344                             end if;
 345                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 346
 347                             -- Bump address
 348                             wb_sio_out.adr(2) <= '1';
 349
 350                             -- Wait for ack
 351                             state := WAIT_ACK_TOP;
 352                         end if;
 353                     end if;
 354                 when WAIT_ACK_BOT =>
 355                     -- If we aren't stalled by the device, clear stb
 356                     if wb_sio_in.stall = '0' then
 357                         wb_sio_out.stb <= '0';
 358                     end if;
 359
 360                     -- Handle ack
 361                     if wb_sio_in.ack = '1' then
 362                         -- If it's a read, latch the data
 363                         if wb_sio_out.we = '0' then
 364                             wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
 365                         end if;
 366
 367                         -- Do we have a "top" part as well ?
 368                         if has_top then
 369                             -- Latch data & sel
 370                             if wb_io_in.we = '1' then
 371                                 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
 372                             end if;
 373                             wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
 374
 375                             -- Bump address and set STB
 376                             wb_sio_out.adr(2) <= '1';
 377                             wb_sio_out.stb <= '1';
 378
 379                             -- Wait for new ack
 380                             state := WAIT_ACK_TOP;
 381                         else
 382                             -- We are done, ack up, clear cyc downstram
 383                             wb_sio_out.cyc <= '0';
 384
 385                             -- And ack & unstall upstream
 386                             wb_io_out.ack <= '1';
 387                             wb_io_out.stall <= '0';
 388
 389                             -- Wait for next one
 390                             state := IDLE;
 391                         end if;
 392                     end if;
 393                 when WAIT_ACK_TOP =>
 394                     -- If we aren't stalled by the device, clear stb
 395                     if wb_sio_in.stall = '0' then
 396                         wb_sio_out.stb <= '0';
 397                     end if;
 398
 399                     -- Handle ack
 400                     if wb_sio_in.ack = '1' then
 401                         -- If it's a read, latch the data
 402                         if wb_sio_out.we = '0' then
 403                             wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
 404                         end if;
 405
 406                         -- We are done, ack up, clear cyc downstram
 407                         wb_sio_out.cyc <= '0';
 408
 409                         -- And ack & unstall upstream
 410                         wb_io_out.ack <= '1';
 411                         wb_io_out.stall <= '0';
 412
 413                         -- Wait for next one
 414                         state := IDLE;
 415                     end if;
 416                 end case;
 417             end if;
 418         end if;
 419     end process;
 420
 421     -- IO wishbone slave intercon.
 422     --
 423     slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out,
 424                                wb_dram_ctrl_out, wb_xics0_out, wb_spiflash_out)
 425         variable slave_io : slave_io_type;
 426
 427         variable match : std_ulogic_vector(31 downto 12);
 428     begin
 429
 430         -- Simple address decoder.
 431         slave_io := SLAVE_IO_NONE;
 432         match := "11" & wb_sio_out.adr(29 downto 12);
 433         if    std_match(match, x"FF---") and HAS_DRAM then
 434             slave_io := SLAVE_IO_DRAM_INIT;
 435         elsif std_match(match, x"F----") then
 436             slave_io := SLAVE_IO_SPI_FLASH_MAP;
 437         elsif std_match(match, x"C0000") then
 438             slave_io := SLAVE_IO_SYSCON;
 439         elsif std_match(match, x"C0002") then
 440             slave_io := SLAVE_IO_UART;
 441         elsif std_match(match, x"C01--") then
 442             slave_io := SLAVE_IO_DRAM_CSR;
 443         elsif std_match(match, x"C0004") then
 444             slave_io := SLAVE_IO_ICP_0;
 445         elsif std_match(match, x"C0006") then
 446             slave_io := SLAVE_IO_SPI_FLASH_REG;
 447         end if;
 448         slave_io_dbg <= slave_io;
 449         wb_uart0_in <= wb_sio_out;
 450         wb_uart0_in.cyc <= '0';
 451         wb_spiflash_in <= wb_sio_out;
 452         wb_spiflash_in.cyc <= '0';
 453         wb_spiflash_is_reg <= '0';
 454         wb_spiflash_is_map <= '0';
 455
 456          -- Only give xics 8 bits of wb addr
 457         wb_xics0_in <= wb_sio_out;
 458         wb_xics0_in.adr <= (others => '0');
 459         wb_xics0_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
 460         wb_xics0_in.cyc  <= '0';
 461
 462         wb_dram_ctrl_in <= wb_sio_out;
 463         wb_dram_ctrl_in.cyc <= '0';
 464         wb_dram_is_csr <= '0';
 465         wb_dram_is_init <= '0';
 466
 467         wb_syscon_in <= wb_sio_out;
 468         wb_syscon_in.cyc <= '0';
 469
 470         case slave_io is
 471         when SLAVE_IO_DRAM_INIT =>
 472             wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
 473             wb_sio_in <= wb_dram_ctrl_out;
 474             wb_dram_is_init <= '1';
 475         when SLAVE_IO_DRAM_CSR =>
 476             wb_dram_ctrl_in.cyc <= wb_sio_out.cyc;
 477             wb_sio_in <= wb_dram_ctrl_out;
 478             wb_dram_is_csr <= '1';
 479         when SLAVE_IO_SYSCON =>
 480             wb_syscon_in.cyc <= wb_sio_out.cyc;
 481             wb_sio_in <= wb_syscon_out;
 482         when SLAVE_IO_UART =>
 483             wb_uart0_in.cyc <= wb_sio_out.cyc;
 484             wb_sio_in <= wb_uart0_out;
 485         when SLAVE_IO_ICP_0 =>
 486             wb_xics0_in.cyc <= wb_sio_out.cyc;
 487             wb_sio_in <= wb_xics0_out;
 488         when SLAVE_IO_SPI_FLASH_MAP =>
 489             -- Clear top bits so they don't make their way to the
 490             -- fash chip.
 491             wb_spiflash_in.adr(29 downto 28) <= "00";
 492             wb_spiflash_in.cyc <= wb_sio_out.cyc;
 493             wb_sio_in <= wb_spiflash_out;
 494             wb_spiflash_is_map <= '1';
 495         when SLAVE_IO_SPI_FLASH_REG =>
 496             wb_spiflash_in.cyc <= wb_sio_out.cyc;
 497             wb_sio_in <= wb_spiflash_out;
 498             wb_spiflash_is_reg <= '1';
 499         when others =>
 500             wb_sio_in.dat <= (others => '1');
 501             wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
 502             wb_sio_in.stall <= '0';
 503         end case;
 504
 505     end process;
 506
 507     -- Syscon slave
 508     syscon0: entity work.syscon
 509         generic map(
 510             HAS_UART => true,
 511             HAS_DRAM => HAS_DRAM,
 512             BRAM_SIZE => MEMORY_SIZE,
 513             DRAM_SIZE => DRAM_SIZE,
 514             DRAM_INIT_SIZE => DRAM_INIT_SIZE,
 515             CLK_FREQ => CLK_FREQ,
 516             HAS_SPI_FLASH => HAS_SPI_FLASH,
 517             SPI_FLASH_OFFSET => SPI_FLASH_OFFSET
 518         )
 519         port map(
 520             clk => system_clk,
 521             rst => rst,
 522             wishbone_in => wb_syscon_in,
 523             wishbone_out => wb_syscon_out,
 524             dram_at_0 => dram_at_0,
 525             core_reset => do_core_reset,
 526             soc_reset => open -- XXX TODO
 527             );
 528
 529     -- Simulated memory and UART
 530
 531     -- UART0 wishbone slave
 532     uart0: entity work.pp_soc_uart
 533         generic map(
 534             FIFO_DEPTH => 32
 535             )
 536         port map(
 537             clk => system_clk,
 538             reset => rst_uart,
 539             txd => uart0_txd,
 540             rxd => uart0_rxd,
 541             irq => int_level_in(0),
 542             wb_adr_in => wb_uart0_in.adr(11 downto 0),
 543             wb_dat_in => wb_uart0_in.dat(7 downto 0),
 544             wb_dat_out => uart_dat8,
 545             wb_cyc_in => wb_uart0_in.cyc,
 546             wb_stb_in => wb_uart0_in.stb,
 547             wb_we_in => wb_uart0_in.we,
 548             wb_ack_out => wb_uart0_out.ack
 549             );
 550     wb_uart0_out.dat <= x"000000" & uart_dat8;
 551     wb_uart0_out.stall <= '0' when wb_uart0_in.cyc = '0' else not wb_uart0_out.ack;
 552
 553     spiflash_gen: if HAS_SPI_FLASH generate
 554         spiflash: entity work.spi_flash_ctrl
 555             generic map (
 556                 DATA_LINES    => SPI_FLASH_DLINES,
 557                 DEF_CLK_DIV   => SPI_FLASH_DEF_CKDV,
 558                 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
 559                 )
 560             port map(
 561                 rst => rst_spi,
 562                 clk => system_clk,
 563                 wb_in => wb_spiflash_in,
 564                 wb_out => wb_spiflash_out,
 565                 wb_sel_reg => wb_spiflash_is_reg,
 566                 wb_sel_map => wb_spiflash_is_map,
 567                 sck => spi_flash_sck,
 568                 cs_n => spi_flash_cs_n,
 569                 sdat_o => spi_flash_sdat_o,
 570                 sdat_oe => spi_flash_sdat_oe,
 571                 sdat_i => spi_flash_sdat_i
 572                 );
 573     end generate;
 574
 575     no_spi0_gen: if not HAS_SPI_FLASH generate
 576         wb_spiflash_out.dat   <= (others => '1');
 577         wb_spiflash_out.ack   <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
 578         wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
 579     end generate;
 580
 581     xics0: entity work.xics
 582         generic map(
 583             LEVEL_NUM => 16
 584             )
 585         port map(
 586             clk => system_clk,
 587             rst => rst_xics,
 588             wb_in => wb_xics0_in,
 589             wb_out => wb_xics0_out,
 590             int_level_in => int_level_in,
 591             core_irq_out => core_ext_irq
 592             );
 593
 594     -- BRAM Memory slave
 595     bram: if MEMORY_SIZE /= 0 generate
 596         bram0: entity work.wishbone_bram_wrapper
 597             generic map(
 598                 MEMORY_SIZE   => MEMORY_SIZE,
 599                 RAM_INIT_FILE => RAM_INIT_FILE
 600                 )
 601             port map(
 602                 clk => system_clk,
 603                 rst => rst_bram,
 604                 wishbone_in => wb_bram_in,
 605                 wishbone_out => wb_bram_out
 606                 );
 607     end generate;
 608
 609     no_bram: if MEMORY_SIZE = 0 generate
 610         wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
 611         wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
 612         wb_bram_out.stall <= wb_bram_in.cyc and not wb_bram_out.ack;
 613     end generate;
 614
 615     -- DMI(debug bus) <-> JTAG bridge
 616     dtm: entity work.dmi_dtm
 617         generic map(
 618             ABITS => 8,
 619             DBITS => 64
 620             )
 621         port map(
 622             sys_clk     => system_clk,
 623             sys_reset   => rst_dtm,
 624             dmi_addr    => dmi_addr,
 625             dmi_din     => dmi_din,
 626             dmi_dout    => dmi_dout,
 627             dmi_req     => dmi_req,
 628             dmi_wr      => dmi_wr,
 629             dmi_ack     => dmi_ack
 630             );
 631
 632     -- DMI interconnect
 633     dmi_intercon: process(dmi_addr, dmi_req,
 634                           dmi_wb_ack, dmi_wb_dout,
 635                           dmi_core_ack, dmi_core_dout)
 636
 637         -- DMI address map (each address is a full 64-bit register)
 638         --
 639         -- Offset:   Size:    Slave:
 640         --  0         4       Wishbone
 641         -- 10        16       Core
 642
 643         type slave_type is (SLAVE_WB,
 644                             SLAVE_CORE,
 645                             SLAVE_NONE);
 646         variable slave : slave_type;
 647     begin
 648         -- Simple address decoder
 649         slave := SLAVE_NONE;
 650         if std_match(dmi_addr, "000000--") then
 651             slave := SLAVE_WB;
 652         elsif std_match(dmi_addr, "0001----") then
 653             slave := SLAVE_CORE;
 654         end if;
 655
 656         -- DMI muxing
 657         dmi_wb_req <= '0';
 658         dmi_core_req <= '0';
 659         case slave is
 660         when SLAVE_WB =>
 661             dmi_wb_req <= dmi_req;
 662             dmi_ack <= dmi_wb_ack;
 663             dmi_din <= dmi_wb_dout;
 664         when SLAVE_CORE =>
 665             dmi_core_req <= dmi_req;
 666             dmi_ack <= dmi_core_ack;
 667             dmi_din <= dmi_core_dout;
 668         when others =>
 669             dmi_ack <= dmi_req;
 670             dmi_din <= (others => '1');
 671         end case;
 672
 673         -- SIM magic exit
 674         if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
 675             stop;
 676         end if;
 677     end process;
 678
 679     -- Wishbone debug master (TODO: Add a DMI address decoder)
 680     wishbone_debug: entity work.wishbone_debug_master
 681         port map(clk => system_clk,
 682                  rst => rst_wbdb,
 683                  dmi_addr => dmi_addr(1 downto 0),
 684                  dmi_dout => dmi_wb_dout,
 685                  dmi_din => dmi_dout,
 686                  dmi_wr => dmi_wr,
 687                  dmi_ack => dmi_wb_ack,
 688                  dmi_req => dmi_wb_req,
 689                  wb_in => wishbone_debug_in,
 690                  wb_out => wishbone_debug_out);
 691
 692
 693 end architecture behaviour;