2 use ieee.std_logic_1164.all;
3 use ieee.math_real.all;
9 use work.wishbone_types.all;
12 -- 0x00000000: Main memory (1 MB)
13 -- 0xc0002000: UART0 (for host communication)
16 MEMORY_SIZE : positive;
17 RAM_INIT_FILE : string;
23 system_clk : in std_ulogic;
26 uart0_txd : out std_ulogic;
27 uart0_rxd : in std_ulogic
31 architecture behaviour of soc is
33 -- Wishbone master signals:
34 signal wishbone_dcore_in : wishbone_slave_out;
35 signal wishbone_dcore_out : wishbone_master_out;
36 signal wishbone_icore_in : wishbone_slave_out;
37 signal wishbone_icore_out : wishbone_master_out;
39 -- Wishbone master (output of arbiter):
40 signal wb_master_in : wishbone_slave_out;
41 signal wb_master_out : wishbone_master_out;
44 signal wb_uart0_in : wishbone_master_out;
45 signal wb_uart0_out : wishbone_slave_out;
46 signal uart_dat8 : std_ulogic_vector(7 downto 0);
48 -- Main memory signals:
49 signal wb_bram_in : wishbone_master_out;
50 signal wb_bram_out : wishbone_slave_out;
51 constant mem_adr_bits : positive := positive(ceil(log2(real(MEMORY_SIZE))));
53 -- Debug signals (used in SIM only)
54 signal registers : regfile;
55 signal terminate : std_ulogic;
60 processor: entity work.core
67 wishbone_insn_in => wishbone_icore_in,
68 wishbone_insn_out => wishbone_icore_out,
69 wishbone_data_in => wishbone_dcore_in,
70 wishbone_data_out => wishbone_dcore_out,
71 registers => registers,
72 terminate_out => terminate
75 -- Wishbone bus master arbiter & mux
76 wishbone_arbiter_0: entity work.wishbone_arbiter
80 wb1_in => wishbone_dcore_out,
81 wb1_out => wishbone_dcore_in,
82 wb2_in => wishbone_icore_out,
83 wb2_out => wishbone_icore_in,
84 wb_out => wb_master_out,
88 -- Wishbone slaves address decoder & mux
89 slave_intercon: process(wb_master_out, wb_bram_out, wb_uart0_out)
91 type slave_type is (SLAVE_UART,
94 variable slave : slave_type;
96 -- Simple address decoder
98 if wb_master_out.adr(63 downto 24) = x"0000000000" then
99 slave := SLAVE_MEMORY;
100 elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then
101 if wb_master_out.adr(15 downto 12) = x"2" then
106 -- Wishbone muxing. Defaults:
107 wb_bram_in <= wb_master_out;
108 wb_bram_in.cyc <= '0';
109 wb_uart0_in <= wb_master_out;
110 wb_uart0_in.cyc <= '0';
113 wb_bram_in.cyc <= wb_master_out.cyc;
114 wb_master_in <= wb_bram_out;
116 wb_uart0_in.cyc <= wb_master_out.cyc;
117 wb_master_in <= wb_uart0_out;
119 wb_master_in.dat <= (others => '1');
120 wb_master_in.ack <= wb_master_out.stb and wb_master_out.cyc;
122 end process slave_intercon;
124 -- Simulated memory and UART
125 sim_terminate_test: if SIM generate
127 -- Dump registers if core terminates
128 dump_registers: process(all)
130 if terminate = '1' then
131 loop_0: for i in 0 to 31 loop
132 report "REG " & to_hstring(registers(i));
134 assert false report "end of test" severity failure;
140 -- UART0 wishbone slave
141 -- XXX FIXME: Need a proper wb64->wb8 adapter that
142 -- converts SELs into low address bits and muxes
143 -- data accordingly (either that or rejects large
145 uart0: entity work.pp_soc_uart
154 wb_adr_in => wb_uart0_in.adr(11 downto 0),
155 wb_dat_in => wb_uart0_in.dat(7 downto 0),
156 wb_dat_out => uart_dat8,
157 wb_cyc_in => wb_uart0_in.cyc,
158 wb_stb_in => wb_uart0_in.stb,
159 wb_we_in => wb_uart0_in.we,
160 wb_ack_out => wb_uart0_out.ack
162 wb_uart0_out.dat <= x"00000000000000" & uart_dat8;
165 bram0: entity work.mw_soc_memory
167 MEMORY_SIZE => MEMORY_SIZE,
168 RAM_INIT_FILE => RAM_INIT_FILE
173 wishbone_in => wb_bram_in,
174 wishbone_out => wb_bram_out
177 end architecture behaviour;