2 sys
.path
.append("../src")
3 sys
.path
.append("../../../TestUtil")
5 from nmigen
.compat
.sim
import run_simulation
10 yield dut
.lu_vaddr_i
.eq(addr
)
11 yield dut
.update_i
.vpn
.eq(addr
>>12)
15 yield dut
.lu_access_i
.eq(1)
16 yield dut
.lu_asid_i
.eq(1)
17 yield dut
.update_i
.valid
.eq(1)
18 yield dut
.update_i
.is_1G
.eq(0)
19 yield dut
.update_i
.is_2M
.eq(0)
20 yield dut
.update_i
.asid
.eq(1)
21 yield dut
.update_i
.content
.ppn
.eq(0)
22 yield dut
.update_i
.content
.rsw
.eq(0)
23 yield dut
.update_i
.content
.r
.eq(1)
28 yield from set_vaddr(addr
)
32 yield from set_vaddr(addr
)
36 yield from set_vaddr(addr
)
40 yield from set_vaddr(addr
)
43 yield from set_vaddr(addr
)
47 yield from set_vaddr(addr
)
51 yield from set_vaddr(addr
)
54 yield dut
.update_i
.is_1G
.eq(1)
56 yield from set_vaddr(addr
)
59 yield dut
.update_i
.is_1G
.eq(1)
61 yield from set_vaddr(addr
)
67 if __name__
== "__main__":
69 run_simulation(dut
, testbench(dut
), vcd_name
="test_tlb.vcd")