f11c48add0949ccd5dd6091e95bc9440b9ae6af6
1 from nmigen
.compat
.sim
import run_simulation
3 from TLB
.Cam
import Cam
5 from TestUtil
.test_helper
import assert_eq
, assert_ne
, assert_op
7 # This function allows for the easy setting of values to the Cam
9 # dut: The Cam being tested
10 # e (Enable): Whether the block is going to be enabled
11 # we (Write Enable): Whether the Cam will write on the next cycle
12 # a (Address): Where the data will be written if write enable is high
13 # d (Data): Either what we are looking for or will write to the address
14 def set_cam(dut
, e
, we
, a
, d
):
15 yield dut
.enable
.eq(e
)
16 yield dut
.write_enable
.eq(we
)
17 yield dut
.address_in
.eq(a
)
18 yield dut
.data_in
.eq(d
)
21 # Checks the multiple match of the Cam
23 # dut: The Cam being tested
24 # mm (Multiple Match): The expected match result
25 # op (Operation): (0 => ==), (1 => !=)
26 def check_multiple_match(dut
, mm
, op
):
27 out_mm
= yield dut
.multiple_match
28 assert_op("Multiple Match", out_mm
, mm
, op
)
30 # Checks the single match of the Cam
32 # dut: The Cam being tested
33 # sm (Single Match): The expected match result
34 # op (Operation): (0 => ==), (1 => !=)
35 def check_single_match(dut
, sm
, op
):
36 out_sm
= yield dut
.single_match
37 assert_op("Single Match", out_sm
, sm
, op
)
39 # Checks the address output of the Cam
41 # dut: The Cam being tested
42 # ma (Match Address): The expected match result
43 # op (Operation): (0 => ==), (1 => !=)
44 def check_match_address(dut
, ma
, op
):
45 out_ma
= yield dut
.match_address
46 assert_op("Match Address", out_ma
, ma
, op
)
48 # Checks the state of the Cam
50 # dut: The Cam being tested
51 # sm (Single Match): The expected match result
52 # mm (Multiple Match): The expected match result
53 # ma: (Match Address): The expected address output
54 # ss_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
55 # mm_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
56 # ma_op (Operation): Operation for the address assertion (0 => ==), (1 => !=)
57 def check_all(dut
, mm
, sm
, ma
, mm_op
, sm_op
, ma_op
):
58 yield from check_multiple_match(dut
, mm
, mm_op
)
59 yield from check_single_match(dut
, sm
, sm_op
)
60 yield from check_match_address(dut
, ma
, ma_op
)
69 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
71 yield from check_single_match(dut
, single_match
, 0)
74 # Note that the default starting entry data bits are all 0
81 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
83 yield from check_multiple_match(dut
, multiple_match
, 0)
86 # Note that the default starting entry data bits are all 0
93 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
95 yield from check_single_match(dut
, single_match
, 0)
104 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
106 yield from check_single_match(dut
, single_match
, 0)
115 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
117 yield from check_all(dut
, multiple_match
, single_match
, address
, 0, 0, 0)
126 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
128 yield from check_all(dut
, multiple_match
, single_match
, address
, 0, 0, 0)
136 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
138 yield from check_single_match(dut
, single_match
, 0)
140 # Multiple Match test
148 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
150 yield from check_single_match(dut
, single_match
, 0)
153 # Same data as Entry 1
160 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
162 yield from check_single_match(dut
, single_match
, 0)
171 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
173 yield from check_all(dut
, multiple_match
, single_match
, address
,0,0,0)
175 # Verify read_warning is not caused
183 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
184 # Note there is no yield we immediately attempt to read in the next cycle
193 yield from set_cam(dut
, enable
, write_enable
, address
, data
)
195 yield from check_single_match(dut
, single_match
, 0)
202 run_simulation(dut
, tbench(dut
), vcd_name
="Waveforms/test_cam.vcd")
203 print("Cam Unit Test Success")
205 if __name__
== "__main__":