1 """ nmigen implementation of buffered pipeline stage, based on zipcpu:
2 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
4 this module requires quite a bit of thought to understand how it works
5 (and why it is needed in the first place). reading the above is
6 *strongly* recommended.
8 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
9 the STB / ACK signals to raise and lower (on separate clocks) before
10 data may proceeed (thus only allowing one piece of data to proceed
11 on *ALTERNATE* cycles), the signalling here is a true pipeline
12 where data will flow on *every* clock when the conditions are right.
14 input acceptance conditions are when:
15 * incoming previous-stage strobe (p.i_valid) is HIGH
16 * outgoing previous-stage ready (p.o_ready) is LOW
18 output transmission conditions are when:
19 * outgoing next-stage strobe (n.o_valid) is HIGH
20 * outgoing next-stage ready (n.i_ready) is LOW
22 the tricky bit is when the input has valid data and the output is not
23 ready to accept it. if it wasn't for the clock synchronisation, it
24 would be possible to tell the input "hey don't send that data, we're
25 not ready". unfortunately, it's not possible to "change the past":
26 the previous stage *has no choice* but to pass on its data.
28 therefore, the incoming data *must* be accepted - and stored: that
29 is the responsibility / contract that this stage *must* accept.
30 on the same clock, it's possible to tell the input that it must
31 not send any more data. this is the "stall" condition.
33 we now effectively have *two* possible pieces of data to "choose" from:
34 the buffered data, and the incoming data. the decision as to which
35 to process and output is based on whether we are in "stall" or not.
36 i.e. when the next stage is no longer ready, the output comes from
37 the buffer if a stall had previously occurred, otherwise it comes
38 direct from processing the input.
40 this allows us to respect a synchronous "travelling STB" with what
41 dan calls a "buffered handshake".
43 it's quite a complex state machine!
46 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
47 from nmigen
.cli
import verilog
, rtlil
48 from collections
.abc
import Sequence
52 """ contains signals that come *from* the previous stage (both in and out)
53 * i_valid: input from previous stage indicating incoming data is valid
54 * o_ready: output to next stage indicating readiness to accept data
55 * i_data : an input - added by the user of this class
59 self
.i_valid
= Signal(name
="p_i_valid") # >>in
60 self
.o_ready
= Signal(name
="p_o_ready") # <<out
62 def connect_in(self
, prev
):
63 """ helper function to connect stage to an input source. do not
64 use to connect stage-to-stage!
66 return [self
.i_valid
.eq(prev
.i_valid
),
67 prev
.o_ready
.eq(self
.o_ready
),
68 eq(self
.data
, prev
.data
),
73 """ contains the signals that go *to* the next stage (both in and out)
74 * o_valid: output indicating to next stage that data is valid
75 * i_ready: input from next stage indicating that it can accept data
76 * o_data : an output - added by the user of this class
79 self
.o_valid
= Signal(name
="n_o_valid") # out>>
80 self
.i_ready
= Signal(name
="n_i_ready") # <<in
82 def connect_to_next(self
, nxt
):
83 """ helper function to connect to the next stage data/valid/ready.
84 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
86 return [nxt
.i_valid
.eq(self
.o_valid
),
87 self
.i_ready
.eq(nxt
.o_ready
),
88 eq(nxt
.data
, self
.data
),
91 def connect_out(self
, nxt
):
92 """ helper function to connect stage to an output source. do not
93 use to connect stage-to-stage!
95 return [nxt
.o_valid
.eq(self
.o_valid
),
96 self
.i_ready
.eq(nxt
.i_ready
),
97 eq(nxt
.data
, self
.data
),
102 if not isinstance(o
, Sequence
):
105 for (ao
, ai
) in zip(o
, i
):
106 res
.append(ao
.eq(ai
))
110 class BufferedPipeline
:
111 """ buffered pipeline stage. data and strobe signals travel in sync.
112 if ever the input is ready and the output is not, processed data
113 is stored in a temporary register.
115 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
116 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
117 stage-1 p.data >>in stage n.data out>> stage+1
123 input data p.data is read (only), is processed and goes into an
124 intermediate result store [process()]. this is updated combinatorially.
126 in a non-stall condition, the intermediate result will go into the
127 output (update_output). however if ever there is a stall, it goes
128 into r_data instead [update_buffer()].
130 when the non-stall condition is released, r_data is the first
131 to be transferred to the output [flush_buffer()], and the stall
134 on the next cycle (as long as stall is not raised again) the
135 input may begin to be processed and transferred directly to output.
137 def __init__(self
, stage
):
138 """ pass in a "stage" which may be either a static class or a class
139 instance, which has three functions:
140 * ispec: returns input signals according to the input specification
141 * ispec: returns output signals to the output specification
142 * process: takes an input instance and returns processed data
144 p.data -> process() -> result --> n.data
151 # set up input and output IO ACK (prev/next ready/valid)
152 self
.p
= PrevControl()
153 self
.n
= NextControl()
155 # set up the input and output data
156 self
.p
.data
= stage
.ispec() # input type
157 self
.r_data
= stage
.ospec() # all these are output type
158 self
.result
= stage
.ospec()
159 self
.n
.data
= stage
.ospec()
161 def connect_to_next(self
, nxt
):
162 """ helper function to connect to the next stage data/valid/ready.
164 return self
.n
.connect_to_next(nxt
.p
)
166 def connect_in(self
, prev
):
167 """ helper function to connect stage to an input source. do not
168 use to connect stage-to-stage!
170 return self
.p
.connect_in(prev
.p
)
172 def connect_out(self
, nxt
):
173 """ helper function to connect stage to an output source. do not
174 use to connect stage-to-stage!
176 return self
.n
.connect_out(nxt
.n
)
178 def set_input(self
, i
):
179 """ helper function to set the input data
181 return eq(self
.p
.data
, i
)
183 def update_buffer(self
):
184 """ copies the result into the intermediate register r_data,
185 which will need to be outputted on a subsequent cycle
186 prior to allowing "normal" operation.
188 return eq(self
.r_data
, self
.result
)
190 def update_output(self
):
191 """ copies the (combinatorial) result into the output
193 return eq(self
.n
.data
, self
.result
)
195 def flush_buffer(self
):
196 """ copies the *intermediate* register r_data into the output
198 return eq(self
.n
.data
, self
.r_data
)
201 return [self
.p
.data
, self
.n
.data
]
203 def elaborate(self
, platform
):
205 if hasattr(self
.stage
, "setup"):
206 self
.stage
.setup(m
, self
.p
.data
)
208 # establish some combinatorial temporaries
209 o_n_validn
= Signal(reset_less
=True)
210 i_p_valid_o_p_ready
= Signal(reset_less
=True)
211 m
.d
.comb
+= [o_n_validn
.eq(~self
.n
.o_valid
),
212 i_p_valid_o_p_ready
.eq(self
.p
.i_valid
& self
.p
.o_ready
),
215 # store result of processing in combinatorial temporary
216 with m
.If(self
.p
.i_valid
): # input is valid: process it
217 m
.d
.comb
+= eq(self
.result
, self
.stage
.process(self
.p
.data
))
218 # if not in stall condition, update the temporary register
219 with m
.If(self
.p
.o_ready
): # not stalled
220 m
.d
.sync
+= self
.update_buffer()
222 #with m.If(self.p.i_rst): # reset
223 # m.d.sync += self.n.o_valid.eq(0)
224 # m.d.sync += self.p.o_ready.eq(0)
225 with m
.If(self
.n
.i_ready
): # next stage is ready
226 with m
.If(self
.p
.o_ready
): # not stalled
227 # nothing in buffer: send (processed) input direct to output
228 m
.d
.sync
+= [self
.n
.o_valid
.eq(self
.p
.i_valid
),
229 self
.update_output(),
231 with m
.Else(): # p.o_ready is false, and something is in buffer.
232 # Flush the [already processed] buffer to the output port.
233 m
.d
.sync
+= [self
.n
.o_valid
.eq(1),
235 # clear stall condition, declare register empty.
236 self
.p
.o_ready
.eq(1),
238 # ignore input, since p.o_ready is also false.
240 # (n.i_ready) is false here: next stage is ready
241 with m
.Elif(o_n_validn
): # next stage being told "ready"
242 m
.d
.sync
+= [self
.n
.o_valid
.eq(self
.p
.i_valid
),
243 self
.p
.o_ready
.eq(1), # Keep the buffer empty
244 # set the output data (from comb result)
245 self
.update_output(),
247 # (n.i_ready) false and (n.o_valid) true:
248 with m
.Elif(i_p_valid_o_p_ready
):
249 # If next stage *is* ready, and not stalled yet, accept input
250 m
.d
.sync
+= self
.p
.o_ready
.eq(~
(self
.p
.i_valid
& self
.n
.o_valid
))
255 return [self
.p
.i_valid
, self
.n
.i_ready
,
256 self
.n
.o_valid
, self
.p
.o_ready
,
260 class ExampleAddStage
:
261 """ an example of how to use the buffered pipeline, as a class instance
265 """ returns a tuple of input signals which will be the incoming data
267 return (Signal(16), Signal(16))
270 """ returns an output signal which will happen to contain the sum
275 def process(self
, i
):
276 """ process the input data (sums the values in the tuple) and returns it
281 class ExampleBufPipeAdd(BufferedPipeline
):
282 """ an example of how to use the buffered pipeline, using a class instance
286 addstage
= ExampleAddStage()
287 BufferedPipeline
.__init
__(self
, addstage
)
291 """ an example of how to use the buffered pipeline, in a static class
302 """ process the input data and returns it (adds 1)
307 class ExampleBufPipe(BufferedPipeline
):
308 """ an example of how to use the buffered pipeline.
312 BufferedPipeline
.__init
__(self
, ExampleStage
)
316 """A simple pipeline stage containing combinational logic that can execute
317 completely in one clock cycle.
321 input_shape : int or tuple or None
322 the shape of ``input.data`` and ``comb_input``
323 output_shape : int or tuple or None
324 the shape of ``output.data`` and ``comb_output``
334 comb_input : Signal, input_shape
335 The input to the combinatorial logic
336 comb_output: Signal, output_shape
337 The output of the combinatorial logic
340 def __init__(self
, stage
):
342 self
._data
_valid
= Signal()
343 # set up input and output IO ACK (prev/next ready/valid)
344 self
.p
= PrevControl()
345 self
.n
= NextControl()
347 # set up the input and output data
348 self
.p
.data
= stage
.ispec() # input type
349 self
.r_data
= stage
.ispec() # input type
350 self
.result
= stage
.ospec() # output data
351 self
.n
.data
= stage
.ospec() # output type
352 self
.n
.data
.name
= "outdata"
354 def set_input(self
, i
):
355 """ helper function to set the input data
357 return eq(self
.p
.data
, i
)
359 def elaborate(self
, platform
):
361 if hasattr(self
.stage
, "setup"):
362 self
.stage
.setup(m
, self
.r_data
)
363 m
.d
.comb
+= eq(self
.result
, self
.stage
.process(self
.r_data
))
364 m
.d
.comb
+= self
.n
.o_valid
.eq(self
._data
_valid
)
365 m
.d
.comb
+= self
.p
.o_ready
.eq(~self
._data
_valid | self
.n
.i_ready
)
366 m
.d
.sync
+= self
._data
_valid
.eq(self
.p
.i_valid | \
367 (~self
.n
.i_ready
& self
._data
_valid
))
368 with m
.If(self
.p
.i_valid
& self
.p
.o_ready
):
369 m
.d
.sync
+= eq(self
.r_data
, self
.p
.data
)
370 m
.d
.comb
+= eq(self
.n
.data
, self
.result
)
374 return [self
.p
.data
, self
.n
.data
]
377 class ExampleCombPipe(CombPipe
):
378 """ an example of how to use the combinatorial pipeline.
382 CombPipe
.__init
__(self
, ExampleStage
)
385 if __name__
== '__main__':
386 dut
= ExampleBufPipe()
387 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
388 with
open("test_bufpipe.il", "w") as f
:
391 dut
= ExampleCombPipe()
392 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
393 with
open("test_combpipe.il", "w") as f
: