1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
6 from nmigen
.cli
import main
, verilog
8 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
10 from singlepipe
import eq
15 def __init__(self
, width
, single_cycle
=False):
18 self
.single_cycle
= single_cycle
20 self
.in_a
= FPOp(width
)
21 self
.in_b
= FPOp(width
)
22 self
.out_z
= FPOp(width
)
24 def get_fragment(self
, platform
=None):
25 """ creates the HDL code-fragment for FPAdd
30 a
= FPNumIn(self
.in_a
, self
.width
)
31 b
= FPNumIn(self
.in_b
, self
.width
)
32 z
= FPNumOut(self
.width
, False)
34 m
.submodules
.fpnum_a
= a
35 m
.submodules
.fpnum_b
= b
36 m
.submodules
.fpnum_z
= z
38 m
.d
.comb
+= a
.v
.eq(self
.in_a
.v
)
39 m
.d
.comb
+= b
.v
.eq(self
.in_b
.v
)
42 tot
= Signal(w
, reset_less
=True) # sticky/round/guard, {mantissa} result, 1 overflow
46 m
.submodules
.overflow
= of
53 with m
.State("get_a"):
54 res
= self
.get_op(m
, self
.in_a
, a
, "get_b")
55 m
.d
.sync
+= eq([a
, self
.in_a
.ack
], res
)
60 with m
.State("get_b"):
61 res
= self
.get_op(m
, self
.in_b
, b
, "special_cases")
62 m
.d
.sync
+= eq([b
, self
.in_b
.ack
], res
)
65 # special cases: NaNs, infs, zeros, denormalised
66 # NOTE: some of these are unique to add. see "Special Operations"
67 # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
69 with m
.State("special_cases"):
72 m
.d
.comb
+= s_nomatch
.eq(a
.s
!= b
.s
)
75 m
.d
.comb
+= m_match
.eq(a
.m
== b
.m
)
77 # if a is NaN or b is NaN return NaN
78 with m
.If(a
.is_nan | b
.is_nan
):
82 # XXX WEIRDNESS for FP16 non-canonical NaN handling
85 ## if a is zero and b is NaN return -b
86 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
88 # m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
90 ## if b is zero and a is NaN return -a
91 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
93 # m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
95 ## if a is -zero and b is NaN return -b
96 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
98 # m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
100 ## if b is -zero and a is NaN return -a
101 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
103 # m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
105 # if a is inf return inf (or NaN)
106 with m
.Elif(a
.is_inf
):
108 m
.d
.sync
+= z
.inf(a
.s
)
109 # if a is inf and signs don't match return NaN
110 with m
.If(b
.exp_128
& s_nomatch
):
113 # if b is inf return inf
114 with m
.Elif(b
.is_inf
):
116 m
.d
.sync
+= z
.inf(b
.s
)
118 # if a is zero and b zero return signed-a/b
119 with m
.Elif(a
.is_zero
& b
.is_zero
):
121 m
.d
.sync
+= z
.create(a
.s
& b
.s
, b
.e
, b
.m
[3:-1])
123 # if a is zero return b
124 with m
.Elif(a
.is_zero
):
126 m
.d
.sync
+= z
.create(b
.s
, b
.e
, b
.m
[3:-1])
128 # if b is zero return a
129 with m
.Elif(b
.is_zero
):
131 m
.d
.sync
+= z
.create(a
.s
, a
.e
, a
.m
[3:-1])
133 # if a equal to -b return zero (+ve zero)
134 with m
.Elif(s_nomatch
& m_match
& (a
.e
== b
.e
)):
136 m
.d
.sync
+= z
.zero(0)
138 # Denormalised Number checks
141 self
.denormalise(m
, a
)
142 self
.denormalise(m
, b
)
147 with m
.State("align"):
148 if not self
.single_cycle
:
149 # NOTE: this does *not* do single-cycle multi-shifting,
150 # it *STAYS* in the align state until exponents match
152 # exponent of a greater than b: shift b down
153 with m
.If(a
.e
> b
.e
):
154 m
.d
.sync
+= b
.shift_down()
155 # exponent of b greater than a: shift a down
156 with m
.Elif(a
.e
< b
.e
):
157 m
.d
.sync
+= a
.shift_down()
158 # exponents equal: move to next stage.
162 # This one however (single-cycle) will do the shift
165 # XXX TODO: the shifter used here is quite expensive
166 # having only one would be better
168 ediff
= Signal((len(a
.e
), True), reset_less
=True)
169 ediffr
= Signal((len(a
.e
), True), reset_less
=True)
170 m
.d
.comb
+= ediff
.eq(a
.e
- b
.e
)
171 m
.d
.comb
+= ediffr
.eq(b
.e
- a
.e
)
172 with m
.If(ediff
> 0):
173 m
.d
.sync
+= b
.shift_down_multi(ediff
)
174 # exponent of b greater than a: shift a down
175 with m
.Elif(ediff
< 0):
176 m
.d
.sync
+= a
.shift_down_multi(ediffr
)
181 # First stage of add. covers same-sign (add) and subtract
182 # special-casing when mantissas are greater or equal, to
183 # give greatest accuracy.
185 with m
.State("add_0"):
187 m
.d
.sync
+= z
.e
.eq(a
.e
)
188 # same-sign (both negative or both positive) add mantissas
189 with m
.If(a
.s
== b
.s
):
191 tot
.eq(Cat(a
.m
, 0) + Cat(b
.m
, 0)),
194 # a mantissa greater than b, use a
195 with m
.Elif(a
.m
>= b
.m
):
197 tot
.eq(Cat(a
.m
, 0) - Cat(b
.m
, 0)),
200 # b mantissa greater than a, use b
203 tot
.eq(Cat(b
.m
, 0) - Cat(a
.m
, 0)),
208 # Second stage of add: preparation for normalisation.
209 # detects when tot sum is too big (tot[27] is kinda a carry bit)
211 with m
.State("add_1"):
212 m
.next
= "normalise_1"
213 # tot[27] gets set when the sum overflows. shift result down
219 of
.round_bit
.eq(tot
[2]),
220 of
.sticky
.eq(tot
[1] | tot
[0]),
229 of
.round_bit
.eq(tot
[1]),
234 # First stage of normalisation.
236 with m
.State("normalise_1"):
237 self
.normalise_1(m
, z
, of
, "normalise_2")
240 # Second stage of normalisation.
242 with m
.State("normalise_2"):
243 self
.normalise_2(m
, z
, of
, "round")
248 with m
.State("round"):
249 self
.roundz(m
, z
, of
.roundz
)
250 m
.next
= "corrections"
255 with m
.State("corrections"):
256 self
.corrections(m
, z
, "pack")
261 with m
.State("pack"):
262 self
.pack(m
, z
, "put_z")
267 with m
.State("put_z"):
268 self
.put_z(m
, z
, self
.out_z
, "get_a")
273 if __name__
== "__main__":
274 alu
= FPADD(width
=32)
275 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
278 # works... but don't use, just do "python fname.py convert -t v"
279 #print (verilog.convert(alu, ports=[
280 # ports=alu.in_a.ports() + \
281 # alu.in_b.ports() + \