8c08652ff9115d90989cf14e8154c106f4a23677
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
6 from nmigen
.cli
import main
, verilog
8 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
11 class FPState(FPBase
):
12 def __init__(self
, state_from
):
13 self
.state_from
= state_from
15 def set_inputs(self
, inputs
):
17 for k
,v
in inputs
.items():
20 def set_outputs(self
, outputs
):
21 self
.outputs
= outputs
22 for k
,v
in outputs
.items():
26 class FPGetOpA(FPState
):
29 self
.get_op(m
, self
.in_a
, self
.a
, "get_b")
32 class FPGetOpB(FPState
):
35 self
.get_op(m
, self
.in_b
, self
.b
, "special_cases")
38 class FPAddSpecialCases(FPState
):
42 m
.d
.comb
+= s_nomatch
.eq(self
.a
.s
!= self
.b
.s
)
45 m
.d
.comb
+= m_match
.eq(self
.a
.m
== self
.b
.m
)
47 # if a is NaN or b is NaN return NaN
48 with m
.If(self
.a
.is_nan | self
.b
.is_nan
):
50 m
.d
.sync
+= self
.z
.nan(1)
52 # XXX WEIRDNESS for FP16 non-canonical NaN handling
55 ## if a is zero and b is NaN return -b
56 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
58 # m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
60 ## if b is zero and a is NaN return -a
61 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
63 # m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
65 ## if a is -zero and b is NaN return -b
66 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
68 # m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
70 ## if b is -zero and a is NaN return -a
71 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
73 # m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
75 # if a is inf return inf (or NaN)
76 with m
.Elif(self
.a
.is_inf
):
78 m
.d
.sync
+= self
.z
.inf(self
.a
.s
)
79 # if a is inf and signs don't match return NaN
80 with m
.If(self
.b
.exp_128
& s_nomatch
):
81 m
.d
.sync
+= self
.z
.nan(1)
83 # if b is inf return inf
84 with m
.Elif(self
.b
.is_inf
):
86 m
.d
.sync
+= self
.z
.inf(self
.b
.s
)
88 # if a is zero and b zero return signed-a/b
89 with m
.Elif(self
.a
.is_zero
& self
.b
.is_zero
):
91 m
.d
.sync
+= self
.z
.create(self
.a
.s
& self
.b
.s
, self
.b
.e
,
94 # if a is zero return b
95 with m
.Elif(self
.a
.is_zero
):
97 m
.d
.sync
+= self
.z
.create(self
.b
.s
, self
.b
.e
, self
.b
.m
[3:-1])
99 # if b is zero return a
100 with m
.Elif(self
.b
.is_zero
):
102 m
.d
.sync
+= self
.z
.create(self
.a
.s
, self
.a
.e
, self
.a
.m
[3:-1])
104 # if a equal to -b return zero (+ve zero)
105 with m
.Elif(s_nomatch
& m_match
& (self
.a
.e
== self
.b
.e
)):
107 m
.d
.sync
+= self
.z
.zero(0)
109 # Denormalised Number checks
111 m
.next
= "denormalise"
114 class FPAddDeNorm(FPState
):
117 # Denormalised Number checks
119 self
.denormalise(m
, self
.a
)
120 self
.denormalise(m
, self
.b
)
125 def __init__(self
, width
, single_cycle
=False):
126 FPBase
.__init
__(self
)
128 self
.single_cycle
= single_cycle
130 self
.in_a
= FPOp(width
)
131 self
.in_b
= FPOp(width
)
132 self
.out_z
= FPOp(width
)
134 def get_fragment(self
, platform
=None):
135 """ creates the HDL code-fragment for FPAdd
140 a
= FPNumIn(self
.in_a
, self
.width
)
141 b
= FPNumIn(self
.in_b
, self
.width
)
142 z
= FPNumOut(self
.width
, False)
144 m
.submodules
.fpnum_a
= a
145 m
.submodules
.fpnum_b
= b
146 m
.submodules
.fpnum_z
= z
149 tot
= Signal(w
, reset_less
=True) # sticky/round/guard, {mantissa} result, 1 overflow
152 m
.submodules
.overflow
= of
154 geta
= FPGetOpA("get_a")
155 geta
.set_inputs({"in_a": self
.in_a
})
156 geta
.set_outputs({"a": a
})
157 m
.d
.comb
+= a
.v
.eq(self
.in_a
.v
) # links in_a to a
159 getb
= FPGetOpB("get_b")
160 getb
.set_inputs({"in_b": self
.in_b
})
161 getb
.set_outputs({"b": b
})
162 m
.d
.comb
+= b
.v
.eq(self
.in_b
.v
) # links in_b to b
164 sc
= FPAddSpecialCases("special_cases")
165 sc
.set_inputs({"a": a
, "b": b
})
166 sc
.set_outputs({"z": z
})
168 dn
= FPAddDeNorm("denormalise")
169 dn
.set_inputs({"a": a
, "b": b
})
170 dn
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
177 with m
.State("get_a"):
183 with m
.State("get_b"):
184 #self.get_op(m, self.in_b, b, "special_cases")
188 # special cases: NaNs, infs, zeros, denormalised
189 # NOTE: some of these are unique to add. see "Special Operations"
190 # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
192 with m
.State("special_cases"):
198 with m
.State("denormalise"):
204 with m
.State("align"):
205 if not self
.single_cycle
:
206 # NOTE: this does *not* do single-cycle multi-shifting,
207 # it *STAYS* in the align state until exponents match
209 # exponent of a greater than b: shift b down
210 with m
.If(a
.e
> b
.e
):
211 m
.d
.sync
+= b
.shift_down()
212 # exponent of b greater than a: shift a down
213 with m
.Elif(a
.e
< b
.e
):
214 m
.d
.sync
+= a
.shift_down()
215 # exponents equal: move to next stage.
219 # This one however (single-cycle) will do the shift
222 # XXX TODO: the shifter used here is quite expensive
223 # having only one would be better
225 ediff
= Signal((len(a
.e
), True), reset_less
=True)
226 ediffr
= Signal((len(a
.e
), True), reset_less
=True)
227 m
.d
.comb
+= ediff
.eq(a
.e
- b
.e
)
228 m
.d
.comb
+= ediffr
.eq(b
.e
- a
.e
)
229 with m
.If(ediff
> 0):
230 m
.d
.sync
+= b
.shift_down_multi(ediff
)
231 # exponent of b greater than a: shift a down
232 with m
.Elif(ediff
< 0):
233 m
.d
.sync
+= a
.shift_down_multi(ediffr
)
238 # First stage of add. covers same-sign (add) and subtract
239 # special-casing when mantissas are greater or equal, to
240 # give greatest accuracy.
242 with m
.State("add_0"):
244 m
.d
.sync
+= z
.e
.eq(a
.e
)
245 # same-sign (both negative or both positive) add mantissas
246 with m
.If(a
.s
== b
.s
):
248 tot
.eq(Cat(a
.m
, 0) + Cat(b
.m
, 0)),
251 # a mantissa greater than b, use a
252 with m
.Elif(a
.m
>= b
.m
):
254 tot
.eq(Cat(a
.m
, 0) - Cat(b
.m
, 0)),
257 # b mantissa greater than a, use b
260 tot
.eq(Cat(b
.m
, 0) - Cat(a
.m
, 0)),
265 # Second stage of add: preparation for normalisation.
266 # detects when tot sum is too big (tot[27] is kinda a carry bit)
268 with m
.State("add_1"):
269 m
.next
= "normalise_1"
270 # tot[27] gets set when the sum overflows. shift result down
276 of
.round_bit
.eq(tot
[2]),
277 of
.sticky
.eq(tot
[1] | tot
[0]),
286 of
.round_bit
.eq(tot
[1]),
291 # First stage of normalisation.
293 with m
.State("normalise_1"):
294 self
.normalise_1(m
, z
, of
, "normalise_2")
297 # Second stage of normalisation.
299 with m
.State("normalise_2"):
300 self
.normalise_2(m
, z
, of
, "round")
305 with m
.State("round"):
306 self
.roundz(m
, z
, of
, "corrections")
311 with m
.State("corrections"):
312 self
.corrections(m
, z
, "pack")
317 with m
.State("pack"):
318 self
.pack(m
, z
, "put_z")
323 with m
.State("put_z"):
324 self
.put_z(m
, z
, self
.out_z
, "get_a")
329 if __name__
== "__main__":
330 alu
= FPADD(width
=32)
331 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
334 # works... but don't use, just do "python fname.py convert -t v"
335 #print (verilog.convert(alu, ports=[
336 # ports=alu.in_a.ports() + \
337 # alu.in_b.ports() + \