1 """ Pipeline API. For multi-input and multi-output variants, see multipipe.
3 Associated development bugs:
4 * http://bugs.libre-riscv.org/show_bug.cgi?id=64
5 * http://bugs.libre-riscv.org/show_bug.cgi?id=57
7 Important: see Stage API (stageapi.py) in combination with below
12 A convenience class that takes an input shape, output shape, a
13 "processing" function and an optional "setup" function. Honestly
14 though, there's not much more effort to just... create a class
15 that returns a couple of Records (see ExampleAddRecordStage in
21 A convenience class that takes a single function as a parameter,
22 that is chain-called to create the exact same input and output spec.
23 It has a process() function that simply returns its input.
25 Instances of this class are completely redundant if handed to
26 StageChain, however when passed to UnbufferedPipeline they
27 can be used to introduce a single clock delay.
32 The base class for pipelines. Contains previous and next ready/valid/data.
33 Also has an extremely useful "connect" function that can be used to
34 connect a chain of pipelines and present the exact same prev/next
37 Note: pipelines basically do not become pipelines as such until
38 handed to a derivative of ControlBase. ControlBase itself is *not*
39 strictly considered a pipeline class. Wishbone and AXI4 (master or
40 slave) could be derived from ControlBase, for example.
44 A simple stalling clock-synchronised pipeline that has no buffering
45 (unlike BufferedHandshake). Data flows on *every* clock cycle when
46 the conditions are right (this is nominally when the input is valid
47 and the output is ready).
49 A stall anywhere along the line will result in a stall back-propagating
50 down the entire chain. The BufferedHandshake by contrast will buffer
51 incoming data, allowing previous stages one clock cycle's grace before
54 An advantage of the UnbufferedPipeline over the Buffered one is
55 that the amount of logic needed (number of gates) is greatly
56 reduced (no second set of buffers basically)
58 The disadvantage of the UnbufferedPipeline is that the valid/ready
59 logic, if chained together, is *combinatorial*, resulting in
60 progressively larger gate delay.
65 A Control class that introduces a single clock delay, passing its
66 data through unaltered. Unlike RegisterPipeline (which relies
67 on UnbufferedPipeline and PassThroughStage) it handles ready/valid
73 A convenience class that, because UnbufferedPipeline introduces a single
74 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
75 stage that, duh, delays its (unmodified) input by one clock cycle.
80 nmigen implementation of buffered pipeline stage, based on zipcpu:
81 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
83 this module requires quite a bit of thought to understand how it works
84 (and why it is needed in the first place). reading the above is
85 *strongly* recommended.
87 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
88 the STB / ACK signals to raise and lower (on separate clocks) before
89 data may proceeed (thus only allowing one piece of data to proceed
90 on *ALTERNATE* cycles), the signalling here is a true pipeline
91 where data will flow on *every* clock when the conditions are right.
93 input acceptance conditions are when:
94 * incoming previous-stage strobe (p.valid_i) is HIGH
95 * outgoing previous-stage ready (p.ready_o) is LOW
97 output transmission conditions are when:
98 * outgoing next-stage strobe (n.valid_o) is HIGH
99 * outgoing next-stage ready (n.ready_i) is LOW
101 the tricky bit is when the input has valid data and the output is not
102 ready to accept it. if it wasn't for the clock synchronisation, it
103 would be possible to tell the input "hey don't send that data, we're
104 not ready". unfortunately, it's not possible to "change the past":
105 the previous stage *has no choice* but to pass on its data.
107 therefore, the incoming data *must* be accepted - and stored: that
108 is the responsibility / contract that this stage *must* accept.
109 on the same clock, it's possible to tell the input that it must
110 not send any more data. this is the "stall" condition.
112 we now effectively have *two* possible pieces of data to "choose" from:
113 the buffered data, and the incoming data. the decision as to which
114 to process and output is based on whether we are in "stall" or not.
115 i.e. when the next stage is no longer ready, the output comes from
116 the buffer if a stall had previously occurred, otherwise it comes
117 direct from processing the input.
119 this allows us to respect a synchronous "travelling STB" with what
120 dan calls a "buffered handshake".
122 it's quite a complex state machine!
127 Synchronised pipeline, Based on:
128 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
131 from nmigen
import Signal
, Mux
, Module
, Elaboratable
132 from nmigen
.cli
import verilog
, rtlil
133 from nmigen
.hdl
.rec
import Record
135 from queue
import Queue
138 from iocontrol
import (PrevControl
, NextControl
, Object
, RecordObject
)
139 from stageapi
import (_spec
, StageCls
, Stage
, StageChain
, StageHelper
)
143 class RecordBasedStage(Stage
):
144 """ convenience class which provides a Records-based layout.
145 honestly it's a lot easier just to create a direct Records-based
146 class (see ExampleAddRecordStage)
148 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
149 self
.in_shape
= in_shape
150 self
.out_shape
= out_shape
151 self
.__process
= processfn
152 self
.__setup
= setupfn
153 def ispec(self
): return Record(self
.in_shape
)
154 def ospec(self
): return Record(self
.out_shape
)
155 def process(seif
, i
): return self
.__process
(i
)
156 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
159 class PassThroughStage(StageCls
):
160 """ a pass-through stage with its input data spec identical to its output,
161 and "passes through" its data from input to output (does nothing).
163 use this basically to explicitly make any data spec Stage-compliant.
164 (many APIs would potentially use a static "wrap" method in e.g.
165 StageCls to achieve a similar effect)
167 def __init__(self
, iospecfn
): self
.iospecfn
= iospecfn
168 def ispec(self
): return self
.iospecfn()
169 def ospec(self
): return self
.iospecfn()
172 class ControlBase(StageHelper
, Elaboratable
):
173 """ Common functions for Pipeline API. Note: a "pipeline stage" only
174 exists (conceptually) when a ControlBase derivative is handed
175 a Stage (combinatorial block)
177 NOTE: ControlBase derives from StageHelper, making it accidentally
178 compliant with the Stage API. Using those functions directly
179 *BYPASSES* a ControlBase instance ready/valid signalling, which
180 clearly should not be done without a really, really good reason.
182 def __init__(self
, stage
=None, in_multi
=None, stage_ctl
=False):
183 """ Base class containing ready/valid/data to previous and next stages
185 * p: contains ready/valid to the previous stage
186 * n: contains ready/valid to the next stage
188 Except when calling Controlbase.connect(), user must also:
189 * add data_i member to PrevControl (p) and
190 * add data_o member to NextControl (n)
191 Calling ControlBase._new_data is a good way to do that.
193 StageHelper
.__init
__(self
, stage
)
195 # set up input and output IO ACK (prev/next ready/valid)
196 self
.p
= PrevControl(in_multi
, stage_ctl
)
197 self
.n
= NextControl(stage_ctl
)
199 # set up the input and output data
200 if stage
is not None:
201 self
._new
_data
(self
, self
, "data")
203 def _new_data(self
, p
, n
, name
):
204 """ allocates new data_i and data_o
206 self
.p
.data_i
= _spec(p
.stage
.ispec
, "%s_i" % name
)
207 self
.n
.data_o
= _spec(n
.stage
.ospec
, "%s_o" % name
)
211 return self
.process(self
.p
.data_i
)
213 def connect_to_next(self
, nxt
):
214 """ helper function to connect to the next stage data/valid/ready.
216 return self
.n
.connect_to_next(nxt
.p
)
218 def _connect_in(self
, prev
):
219 """ internal helper function to connect stage to an input source.
220 do not use to connect stage-to-stage!
222 return self
.p
._connect
_in
(prev
.p
)
224 def _connect_out(self
, nxt
):
225 """ internal helper function to connect stage to an output source.
226 do not use to connect stage-to-stage!
228 return self
.n
._connect
_out
(nxt
.n
)
230 def connect(self
, pipechain
):
231 """ connects a chain (list) of Pipeline instances together and
232 links them to this ControlBase instance:
234 in <----> self <---> out
237 [pipe1, pipe2, pipe3, pipe4]
240 out---in out--in out---in
242 Also takes care of allocating data_i/data_o, by looking up
243 the data spec for each end of the pipechain. i.e It is NOT
244 necessary to allocate self.p.data_i or self.n.data_o manually:
245 this is handled AUTOMATICALLY, here.
247 Basically this function is the direct equivalent of StageChain,
248 except that unlike StageChain, the Pipeline logic is followed.
250 Just as StageChain presents an object that conforms to the
251 Stage API from a list of objects that also conform to the
252 Stage API, an object that calls this Pipeline connect function
253 has the exact same pipeline API as the list of pipline objects
256 Thus it becomes possible to build up larger chains recursively.
257 More complex chains (multi-input, multi-output) will have to be
262 * :pipechain: - a sequence of ControlBase-derived classes
263 (must be one or more in length)
267 * a list of eq assignments that will need to be added in
268 an elaborate() to m.d.comb
270 assert len(pipechain
) > 0, "pipechain must be non-zero length"
271 assert self
.stage
is None, "do not use connect with a stage"
272 eqs
= [] # collated list of assignment statements
274 # connect inter-chain
275 for i
in range(len(pipechain
)-1):
276 pipe1
= pipechain
[i
] # earlier
277 pipe2
= pipechain
[i
+1] # later (by 1)
278 eqs
+= pipe1
.connect_to_next(pipe2
) # earlier n to later p
280 # connect front and back of chain to ourselves
281 front
= pipechain
[0] # first in chain
282 end
= pipechain
[-1] # last in chain
283 self
._new
_data
(front
, end
, "chain") # NOTE: REPLACES existing data
284 eqs
+= front
._connect
_in
(self
) # front p to our p
285 eqs
+= end
._connect
_out
(self
) # end n to out n
289 def set_input(self
, i
):
290 """ helper function to set the input data (used in unit tests)
292 return nmoperator
.eq(self
.p
.data_i
, i
)
295 yield from self
.p
# yields ready/valid/data (data also gets yielded)
296 yield from self
.n
# ditto
301 def elaborate(self
, platform
):
302 """ handles case where stage has dynamic ready/valid functions
305 m
.submodules
.p
= self
.p
306 m
.submodules
.n
= self
.n
308 self
.setup(m
, self
.p
.data_i
)
310 if not self
.p
.stage_ctl
:
313 # intercept the previous (outgoing) "ready", combine with stage ready
314 m
.d
.comb
+= self
.p
.s_ready_o
.eq(self
.p
._ready
_o
& self
.stage
.d_ready
)
316 # intercept the next (incoming) "ready" and combine it with data valid
317 sdv
= self
.stage
.d_valid(self
.n
.ready_i
)
318 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.ready_i
& sdv
)
323 class BufferedHandshake(ControlBase
):
324 """ buffered pipeline stage. data and strobe signals travel in sync.
325 if ever the input is ready and the output is not, processed data
326 is shunted in a temporary register.
328 Argument: stage. see Stage API above
330 stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
331 stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
332 stage-1 p.data_i >>in stage n.data_o out>> stage+1
338 input data p.data_i is read (only), is processed and goes into an
339 intermediate result store [process()]. this is updated combinatorially.
341 in a non-stall condition, the intermediate result will go into the
342 output (update_output). however if ever there is a stall, it goes
343 into r_data instead [update_buffer()].
345 when the non-stall condition is released, r_data is the first
346 to be transferred to the output [flush_buffer()], and the stall
349 on the next cycle (as long as stall is not raised again) the
350 input may begin to be processed and transferred directly to output.
353 def elaborate(self
, platform
):
354 self
.m
= ControlBase
.elaborate(self
, platform
)
356 result
= _spec(self
.stage
.ospec
, "r_tmp")
357 r_data
= _spec(self
.stage
.ospec
, "r_data")
359 # establish some combinatorial temporaries
360 o_n_validn
= Signal(reset_less
=True)
361 n_ready_i
= Signal(reset_less
=True, name
="n_i_rdy_data")
362 nir_por
= Signal(reset_less
=True)
363 nir_por_n
= Signal(reset_less
=True)
364 p_valid_i
= Signal(reset_less
=True)
365 nir_novn
= Signal(reset_less
=True)
366 nirn_novn
= Signal(reset_less
=True)
367 por_pivn
= Signal(reset_less
=True)
368 npnn
= Signal(reset_less
=True)
369 self
.m
.d
.comb
+= [p_valid_i
.eq(self
.p
.valid_i_test
),
370 o_n_validn
.eq(~self
.n
.valid_o
),
371 n_ready_i
.eq(self
.n
.ready_i_test
),
372 nir_por
.eq(n_ready_i
& self
.p
._ready
_o
),
373 nir_por_n
.eq(n_ready_i
& ~self
.p
._ready
_o
),
374 nir_novn
.eq(n_ready_i | o_n_validn
),
375 nirn_novn
.eq(~n_ready_i
& o_n_validn
),
376 npnn
.eq(nir_por | nirn_novn
),
377 por_pivn
.eq(self
.p
._ready
_o
& ~p_valid_i
)
380 # store result of processing in combinatorial temporary
381 self
.m
.d
.comb
+= nmoperator
.eq(result
, self
.data_r
)
383 # if not in stall condition, update the temporary register
384 with self
.m
.If(self
.p
.ready_o
): # not stalled
385 self
.m
.d
.sync
+= nmoperator
.eq(r_data
, result
) # update buffer
387 # data pass-through conditions
388 with self
.m
.If(npnn
):
389 data_o
= self
._postprocess
(result
) # XXX TBD, does nothing right now
390 self
.m
.d
.sync
+= [self
.n
.valid_o
.eq(p_valid_i
), # valid if p_valid
391 nmoperator
.eq(self
.n
.data_o
, data_o
), # update out
393 # buffer flush conditions (NOTE: can override data passthru conditions)
394 with self
.m
.If(nir_por_n
): # not stalled
395 # Flush the [already processed] buffer to the output port.
396 data_o
= self
._postprocess
(r_data
) # XXX TBD, does nothing right now
397 self
.m
.d
.sync
+= [self
.n
.valid_o
.eq(1), # reg empty
398 nmoperator
.eq(self
.n
.data_o
, data_o
), # flush
400 # output ready conditions
401 self
.m
.d
.sync
+= self
.p
._ready
_o
.eq(nir_novn | por_pivn
)
406 class SimpleHandshake(ControlBase
):
407 """ simple handshake control. data and strobe signals travel in sync.
408 implements the protocol used by Wishbone and AXI4.
410 Argument: stage. see Stage API above
412 stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
413 stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
414 stage-1 p.data_i >>in stage n.data_o out>> stage+1
419 Inputs Temporary Output Data
420 ------- ---------- ----- ----
421 P P N N PiV& ~NiR& N P
428 0 0 1 0 0 0 0 1 process(data_i)
429 0 0 1 1 0 0 0 1 process(data_i)
433 0 1 1 0 0 0 0 1 process(data_i)
434 0 1 1 1 0 0 0 1 process(data_i)
438 1 0 1 0 0 0 0 1 process(data_i)
439 1 0 1 1 0 0 0 1 process(data_i)
441 1 1 0 0 1 0 1 0 process(data_i)
442 1 1 0 1 1 1 1 0 process(data_i)
443 1 1 1 0 1 0 1 1 process(data_i)
444 1 1 1 1 1 0 1 1 process(data_i)
448 def elaborate(self
, platform
):
449 self
.m
= m
= ControlBase
.elaborate(self
, platform
)
452 result
= _spec(self
.stage
.ospec
, "r_tmp")
454 # establish some combinatorial temporaries
455 n_ready_i
= Signal(reset_less
=True, name
="n_i_rdy_data")
456 p_valid_i_p_ready_o
= Signal(reset_less
=True)
457 p_valid_i
= Signal(reset_less
=True)
458 m
.d
.comb
+= [p_valid_i
.eq(self
.p
.valid_i_test
),
459 n_ready_i
.eq(self
.n
.ready_i_test
),
460 p_valid_i_p_ready_o
.eq(p_valid_i
& self
.p
.ready_o
),
463 # store result of processing in combinatorial temporary
464 m
.d
.comb
+= nmoperator
.eq(result
, self
.data_r
)
466 # previous valid and ready
467 with m
.If(p_valid_i_p_ready_o
):
468 data_o
= self
._postprocess
(result
) # XXX TBD, does nothing right now
469 m
.d
.sync
+= [r_busy
.eq(1), # output valid
470 nmoperator
.eq(self
.n
.data_o
, data_o
), # update output
472 # previous invalid or not ready, however next is accepting
473 with m
.Elif(n_ready_i
):
474 data_o
= self
._postprocess
(result
) # XXX TBD, does nothing right now
475 m
.d
.sync
+= [nmoperator
.eq(self
.n
.data_o
, data_o
)]
476 # TODO: could still send data here (if there was any)
477 #m.d.sync += self.n.valid_o.eq(0) # ...so set output invalid
478 m
.d
.sync
+= r_busy
.eq(0) # ...so set output invalid
480 m
.d
.comb
+= self
.n
.valid_o
.eq(r_busy
)
481 # if next is ready, so is previous
482 m
.d
.comb
+= self
.p
._ready
_o
.eq(n_ready_i
)
487 class UnbufferedPipeline(ControlBase
):
488 """ A simple pipeline stage with single-clock synchronisation
489 and two-way valid/ready synchronised signalling.
491 Note that a stall in one stage will result in the entire pipeline
494 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
495 travel synchronously with the data: the valid/ready signalling
496 combines in a *combinatorial* fashion. Therefore, a long pipeline
497 chain will lengthen propagation delays.
499 Argument: stage. see Stage API, above
501 stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
502 stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
503 stage-1 p.data_i >>in stage n.data_o out>> stage+1
511 p.data_i : StageInput, shaped according to ispec
513 p.data_o : StageOutput, shaped according to ospec
515 r_data : input_shape according to ispec
516 A temporary (buffered) copy of a prior (valid) input.
517 This is HELD if the output is not ready. It is updated
519 result: output_shape according to ospec
520 The output of the combinatorial logic. it is updated
521 COMBINATORIALLY (no clock dependence).
525 Inputs Temp Output Data
547 1 1 0 0 0 1 1 process(data_i)
548 1 1 0 1 1 1 0 process(data_i)
549 1 1 1 0 0 1 1 process(data_i)
550 1 1 1 1 0 1 1 process(data_i)
553 Note: PoR is *NOT* involved in the above decision-making.
556 def elaborate(self
, platform
):
557 self
.m
= m
= ControlBase
.elaborate(self
, platform
)
559 data_valid
= Signal() # is data valid or not
560 r_data
= _spec(self
.stage
.ospec
, "r_tmp") # output type
563 p_valid_i
= Signal(reset_less
=True)
564 pv
= Signal(reset_less
=True)
565 buf_full
= Signal(reset_less
=True)
566 m
.d
.comb
+= p_valid_i
.eq(self
.p
.valid_i_test
)
567 m
.d
.comb
+= pv
.eq(self
.p
.valid_i
& self
.p
.ready_o
)
568 m
.d
.comb
+= buf_full
.eq(~self
.n
.ready_i_test
& data_valid
)
570 m
.d
.comb
+= self
.n
.valid_o
.eq(data_valid
)
571 m
.d
.comb
+= self
.p
._ready
_o
.eq(~data_valid | self
.n
.ready_i_test
)
572 m
.d
.sync
+= data_valid
.eq(p_valid_i | buf_full
)
575 m
.d
.sync
+= nmoperator
.eq(r_data
, self
.data_r
)
576 data_o
= self
._postprocess
(r_data
) # XXX TBD, does nothing right now
577 m
.d
.comb
+= nmoperator
.eq(self
.n
.data_o
, data_o
)
581 class UnbufferedPipeline2(ControlBase
):
582 """ A simple pipeline stage with single-clock synchronisation
583 and two-way valid/ready synchronised signalling.
585 Note that a stall in one stage will result in the entire pipeline
588 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
589 travel synchronously with the data: the valid/ready signalling
590 combines in a *combinatorial* fashion. Therefore, a long pipeline
591 chain will lengthen propagation delays.
593 Argument: stage. see Stage API, above
595 stage-1 p.valid_i >>in stage n.valid_o out>> stage+1
596 stage-1 p.ready_o <<out stage n.ready_i <<in stage+1
597 stage-1 p.data_i >>in stage n.data_o out>> stage+1
602 p.data_i : StageInput, shaped according to ispec
604 p.data_o : StageOutput, shaped according to ospec
606 buf : output_shape according to ospec
607 A temporary (buffered) copy of a valid output
608 This is HELD if the output is not ready. It is updated
611 Inputs Temp Output Data
613 P P N N ~NiR& N P (buf_full)
618 0 0 0 0 0 0 1 process(data_i)
619 0 0 0 1 1 1 0 reg (odata, unchanged)
620 0 0 1 0 0 0 1 process(data_i)
621 0 0 1 1 0 0 1 process(data_i)
623 0 1 0 0 0 0 1 process(data_i)
624 0 1 0 1 1 1 0 reg (odata, unchanged)
625 0 1 1 0 0 0 1 process(data_i)
626 0 1 1 1 0 0 1 process(data_i)
628 1 0 0 0 0 1 1 process(data_i)
629 1 0 0 1 1 1 0 reg (odata, unchanged)
630 1 0 1 0 0 1 1 process(data_i)
631 1 0 1 1 0 1 1 process(data_i)
633 1 1 0 0 0 1 1 process(data_i)
634 1 1 0 1 1 1 0 reg (odata, unchanged)
635 1 1 1 0 0 1 1 process(data_i)
636 1 1 1 1 0 1 1 process(data_i)
639 Note: PoR is *NOT* involved in the above decision-making.
642 def elaborate(self
, platform
):
643 self
.m
= m
= ControlBase
.elaborate(self
, platform
)
645 buf_full
= Signal() # is data valid or not
646 buf
= _spec(self
.stage
.ospec
, "r_tmp") # output type
649 p_valid_i
= Signal(reset_less
=True)
650 m
.d
.comb
+= p_valid_i
.eq(self
.p
.valid_i_test
)
652 m
.d
.comb
+= self
.n
.valid_o
.eq(buf_full | p_valid_i
)
653 m
.d
.comb
+= self
.p
._ready
_o
.eq(~buf_full
)
654 m
.d
.sync
+= buf_full
.eq(~self
.n
.ready_i_test
& self
.n
.valid_o
)
656 data_o
= Mux(buf_full
, buf
, self
.data_r
)
657 data_o
= self
._postprocess
(data_o
) # XXX TBD, does nothing right now
658 m
.d
.comb
+= nmoperator
.eq(self
.n
.data_o
, data_o
)
659 m
.d
.sync
+= nmoperator
.eq(buf
, self
.n
.data_o
)
664 class PassThroughHandshake(ControlBase
):
665 """ A control block that delays by one clock cycle.
667 Inputs Temporary Output Data
668 ------- ------------------ ----- ----
669 P P N N PiV& PiV| NiR| pvr N P (pvr)
670 i o i o PoR ~PoR ~NoV o o
674 0 0 0 0 0 1 1 0 1 1 odata (unchanged)
675 0 0 0 1 0 1 0 0 1 0 odata (unchanged)
676 0 0 1 0 0 1 1 0 1 1 odata (unchanged)
677 0 0 1 1 0 1 1 0 1 1 odata (unchanged)
679 0 1 0 0 0 0 1 0 0 1 odata (unchanged)
680 0 1 0 1 0 0 0 0 0 0 odata (unchanged)
681 0 1 1 0 0 0 1 0 0 1 odata (unchanged)
682 0 1 1 1 0 0 1 0 0 1 odata (unchanged)
684 1 0 0 0 0 1 1 1 1 1 process(in)
685 1 0 0 1 0 1 0 0 1 0 odata (unchanged)
686 1 0 1 0 0 1 1 1 1 1 process(in)
687 1 0 1 1 0 1 1 1 1 1 process(in)
689 1 1 0 0 1 1 1 1 1 1 process(in)
690 1 1 0 1 1 1 0 0 1 0 odata (unchanged)
691 1 1 1 0 1 1 1 1 1 1 process(in)
692 1 1 1 1 1 1 1 1 1 1 process(in)
697 def elaborate(self
, platform
):
698 self
.m
= m
= ControlBase
.elaborate(self
, platform
)
700 r_data
= _spec(self
.stage
.ospec
, "r_tmp") # output type
703 p_valid_i
= Signal(reset_less
=True)
704 pvr
= Signal(reset_less
=True)
705 m
.d
.comb
+= p_valid_i
.eq(self
.p
.valid_i_test
)
706 m
.d
.comb
+= pvr
.eq(p_valid_i
& self
.p
.ready_o
)
708 m
.d
.comb
+= self
.p
.ready_o
.eq(~self
.n
.valid_o | self
.n
.ready_i_test
)
709 m
.d
.sync
+= self
.n
.valid_o
.eq(p_valid_i | ~self
.p
.ready_o
)
711 odata
= Mux(pvr
, self
.data_r
, r_data
)
712 m
.d
.sync
+= nmoperator
.eq(r_data
, odata
)
713 r_data
= self
._postprocess
(r_data
) # XXX TBD, does nothing right now
714 m
.d
.comb
+= nmoperator
.eq(self
.n
.data_o
, r_data
)
719 class RegisterPipeline(UnbufferedPipeline
):
720 """ A pipeline stage that delays by one clock cycle, creating a
721 sync'd latch out of data_o and valid_o as an indirect byproduct
722 of using PassThroughStage
724 def __init__(self
, iospecfn
):
725 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))
728 class FIFOControl(ControlBase
):
729 """ FIFO Control. Uses Queue to store data, coincidentally
730 happens to have same valid/ready signalling as Stage API.
732 data_i -> fifo.din -> FIFO -> fifo.dout -> data_o
734 def __init__(self
, depth
, stage
, in_multi
=None, stage_ctl
=False,
735 fwft
=True, pipe
=False):
738 * :depth: number of entries in the FIFO
739 * :stage: data processing block
740 * :fwft: first word fall-thru mode (non-fwft introduces delay)
741 * :buffered: use buffered FIFO (introduces extra cycle delay)
743 NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO
744 (fwft=True, buffered=False). XXX TODO: fix this by
745 using Queue in all cases instead.
747 data is processed (and located) as follows:
749 self.p self.stage temp fn temp fn temp fp self.n
750 data_i->process()->result->cat->din.FIFO.dout->cat(data_o)
752 yes, really: cat produces a Cat() which can be assigned to.
753 this is how the FIFO gets de-catted without needing a de-cat
759 ControlBase
.__init
__(self
, stage
, in_multi
, stage_ctl
)
761 def elaborate(self
, platform
):
762 self
.m
= m
= ControlBase
.elaborate(self
, platform
)
764 # make a FIFO with a signal of equal width to the data_o.
765 (fwidth
, _
) = nmoperator
.shape(self
.n
.data_o
)
766 fifo
= Queue(fwidth
, self
.fdepth
, fwft
=self
.fwft
, pipe
=self
.pipe
)
767 m
.submodules
.fifo
= fifo
769 # store result of processing in combinatorial temporary
770 result
= _spec(self
.stage
.ospec
, "r_temp")
771 m
.d
.comb
+= nmoperator
.eq(result
, self
.data_r
)
773 # connect previous rdy/valid/data - do cat on data_i
774 # NOTE: cannot do the PrevControl-looking trick because
775 # of need to process the data. shaaaame....
776 m
.d
.comb
+= [fifo
.we
.eq(self
.p
.valid_i_test
),
777 self
.p
.ready_o
.eq(fifo
.writable
),
778 nmoperator
.eq(fifo
.din
, nmoperator
.cat(result
)),
781 # connect next rdy/valid/data - do cat on data_o (further below)
782 connections
= [self
.n
.valid_o
.eq(fifo
.readable
),
783 fifo
.re
.eq(self
.n
.ready_i_test
),
786 m
.d
.comb
+= connections
# combinatorial on next ready/valid
788 m
.d
.sync
+= connections
# unbuffered fwft mode needs sync
789 data_o
= nmoperator
.cat(self
.n
.data_o
).eq(fifo
.dout
)
790 data_o
= self
._postprocess
(data_o
) # XXX TBD, does nothing right now
797 class UnbufferedPipeline(FIFOControl
):
798 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
799 FIFOControl
.__init
__(self
, 1, stage
, in_multi
, stage_ctl
,
800 fwft
=True, pipe
=False)
802 # aka "BreakReadyStage" XXX had to set fwft=True to get it to work
803 class PassThroughHandshake(FIFOControl
):
804 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
805 FIFOControl
.__init
__(self
, 1, stage
, in_multi
, stage_ctl
,
806 fwft
=True, pipe
=True)
808 # this is *probably* BufferedHandshake, although test #997 now succeeds.
809 class BufferedHandshake(FIFOControl
):
810 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
811 FIFOControl
.__init
__(self
, 2, stage
, in_multi
, stage_ctl
,
812 fwft
=True, pipe
=False)
816 # this is *probably* SimpleHandshake (note: memory cell size=0)
817 class SimpleHandshake(FIFOControl):
818 def __init__(self, stage, in_multi=None, stage_ctl=False):
819 FIFOControl.__init__(self, 0, stage, in_multi, stage_ctl,
820 fwft=True, pipe=False)