1 """ Unit tests for Buffered and Unbuffered pipelines
3 contains useful worked examples of how to use the Pipeline API,
6 * Combinatorial Stage "Chaining"
7 * class-based data stages
8 * nmigen module-based data stages
9 * special nmigen module-based data stage, where the stage *is* the module
10 * Record-based data stages
11 * static-class data stages
12 * multi-stage pipelines (and how to connect them)
13 * how to *use* the pipelines (see Test5) - how to get data in and out
17 from nmigen
import Module
, Signal
, Mux
, Const
18 from nmigen
.hdl
.rec
import Record
19 from nmigen
.compat
.sim
import run_simulation
20 from nmigen
.cli
import verilog
, rtlil
22 from example_buf_pipe
import ExampleBufPipe
, ExampleBufPipeAdd
23 from example_buf_pipe
import ExamplePipeline
, UnbufferedPipeline
24 from example_buf_pipe
import ExampleStageCls
25 from example_buf_pipe
import PrevControl
, NextControl
, BufferedHandshake
26 from example_buf_pipe
import StageChain
, ControlBase
, StageCls
27 from singlepipe
import UnbufferedPipeline2
28 from singlepipe
import SimpleHandshake
29 from singlepipe
import PassThroughHandshake
30 from singlepipe
import PassThroughStage
31 from singlepipe
import FIFOControl
32 from singlepipe
import RecordObject
34 from random
import randint
, seed
39 def check_o_n_valid(dut
, val
):
40 o_n_valid
= yield dut
.n
.o_valid
41 assert o_n_valid
== val
43 def check_o_n_valid2(dut
, val
):
44 o_n_valid
= yield dut
.n
.o_valid
45 assert o_n_valid
== val
49 #yield dut.i_p_rst.eq(1)
50 yield dut
.n
.i_ready
.eq(0)
51 yield dut
.p
.o_ready
.eq(0)
54 #yield dut.i_p_rst.eq(0)
55 yield dut
.n
.i_ready
.eq(1)
56 yield dut
.p
.i_data
.eq(5)
57 yield dut
.p
.i_valid
.eq(1)
60 yield dut
.p
.i_data
.eq(7)
61 yield from check_o_n_valid(dut
, 0) # effects of i_p_valid delayed
63 yield from check_o_n_valid(dut
, 1) # ok *now* i_p_valid effect is felt
65 yield dut
.p
.i_data
.eq(2)
67 yield dut
.n
.i_ready
.eq(0) # begin going into "stall" (next stage says ready)
68 yield dut
.p
.i_data
.eq(9)
70 yield dut
.p
.i_valid
.eq(0)
71 yield dut
.p
.i_data
.eq(12)
73 yield dut
.p
.i_data
.eq(32)
74 yield dut
.n
.i_ready
.eq(1)
76 yield from check_o_n_valid(dut
, 1) # buffer still needs to output
78 yield from check_o_n_valid(dut
, 1) # buffer still needs to output
80 yield from check_o_n_valid(dut
, 0) # buffer outputted, *now* we're done.
85 #yield dut.p.i_rst.eq(1)
86 yield dut
.n
.i_ready
.eq(0)
87 #yield dut.p.o_ready.eq(0)
90 #yield dut.p.i_rst.eq(0)
91 yield dut
.n
.i_ready
.eq(1)
92 yield dut
.p
.i_data
.eq(5)
93 yield dut
.p
.i_valid
.eq(1)
96 yield dut
.p
.i_data
.eq(7)
97 yield from check_o_n_valid2(dut
, 0) # effects of i_p_valid delayed 2 clocks
99 yield from check_o_n_valid2(dut
, 0) # effects of i_p_valid delayed 2 clocks
101 yield dut
.p
.i_data
.eq(2)
103 yield from check_o_n_valid2(dut
, 1) # ok *now* i_p_valid effect is felt
104 yield dut
.n
.i_ready
.eq(0) # begin going into "stall" (next stage says ready)
105 yield dut
.p
.i_data
.eq(9)
107 yield dut
.p
.i_valid
.eq(0)
108 yield dut
.p
.i_data
.eq(12)
110 yield dut
.p
.i_data
.eq(32)
111 yield dut
.n
.i_ready
.eq(1)
113 yield from check_o_n_valid2(dut
, 1) # buffer still needs to output
115 yield from check_o_n_valid2(dut
, 1) # buffer still needs to output
117 yield from check_o_n_valid2(dut
, 1) # buffer still needs to output
119 yield from check_o_n_valid2(dut
, 0) # buffer outputted, *now* we're done.
126 def __init__(self
, dut
, resultfn
):
128 self
.resultfn
= resultfn
130 for i
in range(num_tests
):
131 #data.append(randint(0, 1<<16-1))
132 self
.data
.append(i
+1)
137 while self
.o
!= len(self
.data
):
138 send_range
= randint(0, 3)
139 for j
in range(randint(1,10)):
143 send
= randint(0, send_range
) != 0
144 o_p_ready
= yield self
.dut
.p
.o_ready
148 if send
and self
.i
!= len(self
.data
):
149 yield self
.dut
.p
.i_valid
.eq(1)
150 yield self
.dut
.p
.i_data
.eq(self
.data
[self
.i
])
153 yield self
.dut
.p
.i_valid
.eq(0)
157 while self
.o
!= len(self
.data
):
158 stall_range
= randint(0, 3)
159 for j
in range(randint(1,10)):
160 stall
= randint(0, stall_range
) != 0
161 yield self
.dut
.n
.i_ready
.eq(stall
)
163 o_n_valid
= yield self
.dut
.n
.o_valid
164 i_n_ready
= yield self
.dut
.n
.i_ready_test
165 if not o_n_valid
or not i_n_ready
:
167 o_data
= yield self
.dut
.n
.o_data
168 self
.resultfn(o_data
, self
.data
[self
.o
], self
.i
, self
.o
)
170 if self
.o
== len(self
.data
):
173 def test3_resultfn(o_data
, expected
, i
, o
):
174 assert o_data
== expected
+ 1, \
175 "%d-%d data %x not match %x\n" \
176 % (i
, o
, o_data
, expected
)
178 def data_placeholder():
180 for i
in range(num_tests
):
182 d
.src1
= randint(0, 1<<16-1)
183 d
.src2
= randint(0, 1<<16-1)
189 for i
in range(num_tests
):
190 data
.append({'src1': randint(0, 1<<16-1),
191 'src2': randint(0, 1<<16-1)})
196 def __init__(self
, dut
, resultfn
, data
=None, stage_ctl
=False):
198 self
.resultfn
= resultfn
199 self
.stage_ctl
= stage_ctl
204 for i
in range(num_tests
):
205 self
.data
.append((randint(0, 1<<16-1), randint(0, 1<<16-1)))
210 while self
.o
!= len(self
.data
):
211 send_range
= randint(0, 3)
212 for j
in range(randint(1,10)):
216 send
= randint(0, send_range
) != 0
218 o_p_ready
= yield self
.dut
.p
.o_ready
222 if send
and self
.i
!= len(self
.data
):
223 yield self
.dut
.p
.i_valid
.eq(1)
224 for v
in self
.dut
.set_input(self
.data
[self
.i
]):
228 yield self
.dut
.p
.i_valid
.eq(0)
232 while self
.o
!= len(self
.data
):
233 stall_range
= randint(0, 3)
234 for j
in range(randint(1,10)):
235 ready
= randint(0, stall_range
) != 0
237 yield self
.dut
.n
.i_ready
.eq(ready
)
239 o_n_valid
= yield self
.dut
.n
.o_valid
240 i_n_ready
= yield self
.dut
.n
.i_ready_test
241 if not o_n_valid
or not i_n_ready
:
243 if isinstance(self
.dut
.n
.o_data
, Record
):
245 dod
= self
.dut
.n
.o_data
246 for k
, v
in dod
.fields
.items():
249 o_data
= yield self
.dut
.n
.o_data
250 self
.resultfn(o_data
, self
.data
[self
.o
], self
.i
, self
.o
)
252 if self
.o
== len(self
.data
):
255 def test5_resultfn(o_data
, expected
, i
, o
):
256 res
= expected
[0] + expected
[1]
257 assert o_data
== res
, \
258 "%d-%d data %x not match %s\n" \
259 % (i
, o
, o_data
, repr(expected
))
263 for i
in range(num_tests
):
264 #data.append(randint(0, 1<<16-1))
269 stall
= randint(0, 3) != 0
270 send
= randint(0, 5) != 0
271 yield dut
.n
.i_ready
.eq(stall
)
272 o_p_ready
= yield dut
.p
.o_ready
274 if send
and i
!= len(data
):
275 yield dut
.p
.i_valid
.eq(1)
276 yield dut
.p
.i_data
.eq(data
[i
])
279 yield dut
.p
.i_valid
.eq(0)
281 o_n_valid
= yield dut
.n
.o_valid
282 i_n_ready
= yield dut
.n
.i_ready_test
283 if o_n_valid
and i_n_ready
:
284 o_data
= yield dut
.n
.o_data
285 assert o_data
== data
[o
] + 2, "%d-%d data %x not match %x\n" \
286 % (i
, o
, o_data
, data
[o
])
291 ######################################################################
293 ######################################################################
295 class ExampleBufPipe2(ControlBase
):
296 """ Example of how to do chained pipeline stages.
299 def elaborate(self
, platform
):
302 pipe1
= ExampleBufPipe()
303 pipe2
= ExampleBufPipe()
305 m
.submodules
.pipe1
= pipe1
306 m
.submodules
.pipe2
= pipe2
308 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
313 ######################################################################
315 ######################################################################
317 class ExampleBufPipeChain2(BufferedHandshake
):
318 """ connects two stages together as a *single* combinatorial stage.
321 stage1
= ExampleStageCls()
322 stage2
= ExampleStageCls()
323 combined
= StageChain([stage1
, stage2
])
324 BufferedHandshake
.__init
__(self
, combined
)
329 for i
in range(num_tests
):
330 data
.append(randint(0, 1<<16-2))
334 def test9_resultfn(o_data
, expected
, i
, o
):
336 assert o_data
== res
, \
337 "%d-%d received data %x not match expected %x\n" \
338 % (i
, o
, o_data
, res
)
341 ######################################################################
343 ######################################################################
346 def __init__(self
, width
, signed
):
348 self
.src1
= Signal((width
, signed
), name
="src1")
349 self
.src2
= Signal((width
, signed
), name
="src2")
350 self
.output
= Signal(width
, name
="out")
352 def elaborate(self
, platform
):
353 self
.m
.d
.comb
+= self
.output
.eq(Mux(self
.src1
< self
.src2
, 1, 0))
357 class LTStage(StageCls
):
358 """ module-based stage example
361 self
.slt
= SetLessThan(16, True)
364 return (Signal(16, name
="sig1"), Signal(16, "sig2"))
367 return Signal(16, "out")
369 def setup(self
, m
, i
):
371 m
.submodules
.slt
= self
.slt
372 m
.d
.comb
+= self
.slt
.src1
.eq(i
[0])
373 m
.d
.comb
+= self
.slt
.src2
.eq(i
[1])
374 m
.d
.comb
+= self
.o
.eq(self
.slt
.output
)
376 def process(self
, i
):
380 class LTStageDerived(SetLessThan
, StageCls
):
381 """ special version of a nmigen module where the module is also a stage
383 shows that you don't actually need to combinatorially connect
384 to the outputs, or add the module as a submodule: just return
385 the module output parameter(s) from the Stage.process() function
389 SetLessThan
.__init
__(self
, 16, True)
392 return (Signal(16), Signal(16))
397 def setup(self
, m
, i
):
398 m
.submodules
.slt
= self
399 m
.d
.comb
+= self
.src1
.eq(i
[0])
400 m
.d
.comb
+= self
.src2
.eq(i
[1])
402 def process(self
, i
):
406 class ExampleLTPipeline(UnbufferedPipeline
):
407 """ an example of how to use the unbuffered pipeline.
412 UnbufferedPipeline
.__init
__(self
, stage
)
415 class ExampleLTBufferedPipeDerived(BufferedHandshake
):
416 """ an example of how to use the buffered pipeline.
420 stage
= LTStageDerived()
421 BufferedHandshake
.__init
__(self
, stage
)
424 def test6_resultfn(o_data
, expected
, i
, o
):
425 res
= 1 if expected
[0] < expected
[1] else 0
426 assert o_data
== res
, \
427 "%d-%d data %x not match %s\n" \
428 % (i
, o
, o_data
, repr(expected
))
431 ######################################################################
433 ######################################################################
435 class ExampleAddRecordStage(StageCls
):
436 """ example use of a Record
439 record_spec
= [('src1', 16), ('src2', 16)]
441 """ returns a Record using the specification
443 return Record(self
.record_spec
)
446 return Record(self
.record_spec
)
448 def process(self
, i
):
449 """ process the input data, returning a dictionary with key names
450 that exactly match the Record's attributes.
452 return {'src1': i
.src1
+ 1,
455 ######################################################################
457 ######################################################################
459 class ExampleAddRecordPlaceHolderStage(StageCls
):
460 """ example use of a Record, with a placeholder as the processing result
463 record_spec
= [('src1', 16), ('src2', 16)]
465 """ returns a Record using the specification
467 return Record(self
.record_spec
)
470 return Record(self
.record_spec
)
472 def process(self
, i
):
473 """ process the input data, returning a PlaceHolder class instance
474 with attributes that exactly match those of the Record.
482 class PlaceHolder
: pass
485 class ExampleAddRecordPipe(UnbufferedPipeline
):
486 """ an example of how to use the combinatorial pipeline.
490 stage
= ExampleAddRecordStage()
491 UnbufferedPipeline
.__init
__(self
, stage
)
494 def test7_resultfn(o_data
, expected
, i
, o
):
495 res
= (expected
['src1'] + 1, expected
['src2'] + 1)
496 assert o_data
['src1'] == res
[0] and o_data
['src2'] == res
[1], \
497 "%d-%d data %s not match %s\n" \
498 % (i
, o
, repr(o_data
), repr(expected
))
501 class ExampleAddRecordPlaceHolderPipe(UnbufferedPipeline
):
502 """ an example of how to use the combinatorial pipeline.
506 stage
= ExampleAddRecordPlaceHolderStage()
507 UnbufferedPipeline
.__init
__(self
, stage
)
510 def test11_resultfn(o_data
, expected
, i
, o
):
511 res1
= expected
.src1
+ 1
512 res2
= expected
.src2
+ 1
513 assert o_data
['src1'] == res1
and o_data
['src2'] == res2
, \
514 "%d-%d data %s not match %s\n" \
515 % (i
, o
, repr(o_data
), repr(expected
))
518 ######################################################################
520 ######################################################################
523 class Example2OpClass
:
524 """ an example of a class used to store 2 operands.
525 requires an eq function, to conform with the pipeline stage API
529 self
.op1
= Signal(16)
530 self
.op2
= Signal(16)
533 return [self
.op1
.eq(i
.op1
), self
.op2
.eq(i
.op2
)]
536 class ExampleAddClassStage(StageCls
):
537 """ an example of how to use the buffered pipeline, as a class instance
541 """ returns an instance of an Example2OpClass.
543 return Example2OpClass()
546 """ returns an output signal which will happen to contain the sum
551 def process(self
, i
):
552 """ process the input data (sums the values in the tuple) and returns it
557 class ExampleBufPipeAddClass(BufferedHandshake
):
558 """ an example of how to use the buffered pipeline, using a class instance
562 addstage
= ExampleAddClassStage()
563 BufferedHandshake
.__init
__(self
, addstage
)
567 """ the eq function, called by set_input, needs an incoming object
568 that conforms to the Example2OpClass.eq function requirements
569 easiest way to do that is to create a class that has the exact
570 same member layout (self.op1, self.op2) as Example2OpClass
572 def __init__(self
, op1
, op2
):
577 def test8_resultfn(o_data
, expected
, i
, o
):
578 res
= expected
.op1
+ expected
.op2
# these are a TestInputAdd instance
579 assert o_data
== res
, \
580 "%d-%d data %x not match %s\n" \
581 % (i
, o
, o_data
, repr(expected
))
585 for i
in range(num_tests
):
586 data
.append(TestInputAdd(randint(0, 1<<16-1), randint(0, 1<<16-1)))
590 ######################################################################
592 ######################################################################
594 class ExampleStageDelayCls(StageCls
):
595 """ an example of how to use the buffered pipeline, in a static class
599 def __init__(self
, valid_trigger
=2):
600 self
.count
= Signal(2)
601 self
.valid_trigger
= valid_trigger
604 return Signal(16, name
="example_input_signal")
607 return Signal(16, name
="example_output_signal")
611 return (self
.count
== 1)# | (self.count == 3)
614 def d_valid(self
, i_ready
):
615 return self
.count
== self
.valid_trigger
618 def process(self
, i
):
619 """ process the input data and returns it (adds 1)
623 def elaborate(self
, platform
):
625 m
.d
.sync
+= self
.count
.eq(self
.count
+ 1)
629 class ExampleBufDelayedPipe(BufferedHandshake
):
632 stage
= ExampleStageDelayCls(valid_trigger
=2)
633 BufferedHandshake
.__init
__(self
, stage
, stage_ctl
=True)
635 def elaborate(self
, platform
):
636 m
= BufferedHandshake
.elaborate(self
, platform
)
637 m
.submodules
.stage
= self
.stage
643 for i
in range(num_tests
):
644 data
.append(1<<((i
*3)%15))
645 #data.append(randint(0, 1<<16-2))
646 #print (hex(data[-1]))
650 def test12_resultfn(o_data
, expected
, i
, o
):
652 assert o_data
== res
, \
653 "%d-%d data %x not match %x\n" \
654 % (i
, o
, o_data
, res
)
657 ######################################################################
659 ######################################################################
661 class ExampleUnBufDelayedPipe(BufferedHandshake
):
664 stage
= ExampleStageDelayCls(valid_trigger
=3)
665 BufferedHandshake
.__init
__(self
, stage
, stage_ctl
=True)
667 def elaborate(self
, platform
):
668 m
= BufferedHandshake
.elaborate(self
, platform
)
669 m
.submodules
.stage
= self
.stage
672 ######################################################################
674 ######################################################################
676 class ExampleBufModeAdd1Pipe(SimpleHandshake
):
679 stage
= ExampleStageCls()
680 SimpleHandshake
.__init
__(self
, stage
)
683 ######################################################################
685 ######################################################################
687 class ExampleBufModeUnBufPipe(ControlBase
):
689 def elaborate(self
, platform
):
690 m
= ControlBase
._elaborate
(self
, platform
)
692 pipe1
= ExampleBufModeAdd1Pipe()
693 pipe2
= ExampleBufAdd1Pipe()
695 m
.submodules
.pipe1
= pipe1
696 m
.submodules
.pipe2
= pipe2
698 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
702 ######################################################################
704 ######################################################################
706 class ExampleUnBufAdd1Pipe2(UnbufferedPipeline2
):
709 stage
= ExampleStageCls()
710 UnbufferedPipeline2
.__init__(self
, stage
)
713 ######################################################################
715 ######################################################################
717 class PassThroughTest(PassThroughHandshake
):
720 return Signal(16, "out")
723 stage
= PassThroughStage(self
.iospecfn
)
724 PassThroughHandshake
.__init
__(self
, stage
)
726 def test_identical_resultfn(o_data
, expected
, i
, o
):
728 assert o_data
== res
, \
729 "%d-%d data %x not match %x\n" \
730 % (i
, o
, o_data
, res
)
733 ######################################################################
735 ######################################################################
737 class ExamplePassAdd1Pipe(PassThroughHandshake
):
740 stage
= ExampleStageCls()
741 PassThroughHandshake
.__init
__(self
, stage
)
744 class ExampleBufPassThruPipe(ControlBase
):
746 def elaborate(self
, platform
):
747 m
= ControlBase
._elaborate
(self
, platform
)
749 # XXX currently fails: any other permutation works fine.
750 # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
751 # also fails using UnbufferedPipeline as well
752 pipe1
= ExampleBufModeAdd1Pipe()
753 pipe2
= ExamplePassAdd1Pipe()
755 m
.submodules
.pipe1
= pipe1
756 m
.submodules
.pipe2
= pipe2
758 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
763 ######################################################################
765 ######################################################################
768 return Signal(16, name
="d_in")
770 class FIFOTest16(FIFOControl
):
773 FIFOControl
.__init
__(self
, 2, iospecfn
)
776 ######################################################################
778 ######################################################################
780 class ExampleFIFOPassThruPipe1(ControlBase
):
782 def elaborate(self
, platform
):
783 m
= ControlBase
._elaborate
(self
, platform
)
786 pipe2
= ExamplePassAdd1Pipe()
788 m
.submodules
.pipe1
= pipe1
789 m
.submodules
.pipe2
= pipe2
791 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
796 ######################################################################
798 ######################################################################
800 class Example2OpRecord(RecordObject
):
802 RecordObject
.__init
__(self
)
803 self
.op1
= Signal(16)
804 self
.op2
= Signal(16)
807 class ExampleAddRecordObjectStage(StageCls
):
810 """ returns an instance of an Example2OpRecord.
812 return Example2OpRecord()
815 """ returns an output signal which will happen to contain the sum
820 def process(self
, i
):
821 """ process the input data (sums the values in the tuple) and returns it
826 class ExampleRecordHandshakeAddClass(SimpleHandshake
):
829 addstage
= ExampleAddRecordObjectStage()
830 SimpleHandshake
.__init
__(self
, stage
=addstage
)
833 ######################################################################
835 ######################################################################
837 def iospecfnrecord():
838 return Example2OpRecord()
840 class FIFOTestRecordControl(FIFOControl
):
843 FIFOControl
.__init
__(self
, 2, iospecfnrecord
)
846 class ExampleFIFORecordObjectPipe(ControlBase
):
848 def elaborate(self
, platform
):
849 m
= ControlBase
._elaborate
(self
, platform
)
851 pipe1
= FIFOTestRecordControl()
852 pipe2
= ExampleRecordHandshakeAddClass()
854 m
.submodules
.pipe1
= pipe1
855 m
.submodules
.pipe2
= pipe2
857 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
862 ######################################################################
864 ######################################################################
867 return (Signal(16, name
="src1"), Signal(16, name
="src2"))
869 class FIFOTest2x16(FIFOControl
):
872 FIFOControl
.__init
__(self
, iospecfn2
, 2)
875 ######################################################################
877 ######################################################################
879 class ExampleBufPassThruPipe2(ControlBase
):
881 def elaborate(self
, platform
):
882 m
= ControlBase
._elaborate
(self
, platform
)
884 # XXX currently fails: any other permutation works fine.
885 # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
886 # also fails using UnbufferedPipeline as well
887 #pipe1 = ExampleUnBufAdd1Pipe()
888 #pipe2 = ExampleBufAdd1Pipe()
889 pipe1
= ExampleBufAdd1Pipe()
890 pipe2
= ExamplePassAdd1Pipe()
892 m
.submodules
.pipe1
= pipe1
893 m
.submodules
.pipe2
= pipe2
895 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
900 ######################################################################
902 ######################################################################
904 class ExampleBufPipe3(ControlBase
):
905 """ Example of how to do delayed pipeline, where the stage signals
909 def elaborate(self
, platform
):
910 m
= ControlBase
._elaborate
(self
, platform
)
912 pipe1
= ExampleBufDelayedPipe()
913 pipe2
= ExampleBufPipe()
915 m
.submodules
.pipe1
= pipe1
916 m
.submodules
.pipe2
= pipe2
918 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
922 ######################################################################
923 # Test 999 - XXX FAILS
924 # http://bugs.libre-riscv.org/show_bug.cgi?id=57
925 ######################################################################
927 class ExampleBufAdd1Pipe(BufferedHandshake
):
930 stage
= ExampleStageCls()
931 BufferedHandshake
.__init
__(self
, stage
)
934 class ExampleUnBufAdd1Pipe(UnbufferedPipeline
):
937 stage
= ExampleStageCls()
938 UnbufferedPipeline
.__init
__(self
, stage
)
941 class ExampleBufUnBufPipe(ControlBase
):
943 def elaborate(self
, platform
):
944 m
= ControlBase
._elaborate
(self
, platform
)
946 # XXX currently fails: any other permutation works fine.
947 # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
948 # also fails using UnbufferedPipeline as well
949 #pipe1 = ExampleUnBufAdd1Pipe()
950 #pipe2 = ExampleBufAdd1Pipe()
951 pipe1
= ExampleBufAdd1Pipe()
952 pipe2
= ExampleUnBufAdd1Pipe()
954 m
.submodules
.pipe1
= pipe1
955 m
.submodules
.pipe2
= pipe2
957 m
.d
.comb
+= self
.connect([pipe1
, pipe2
])
962 ######################################################################
964 ######################################################################
968 if __name__
== '__main__':
970 dut
= ExampleBufPipe()
971 run_simulation(dut
, testbench(dut
), vcd_name
="test_bufpipe.vcd")
974 dut
= ExampleBufPipe2()
975 run_simulation(dut
, testbench2(dut
), vcd_name
="test_bufpipe2.vcd")
976 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
977 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
978 [dut
.p
.i_data
] + [dut
.n
.o_data
]
979 vl
= rtlil
.convert(dut
, ports
=ports
)
980 with
open("test_bufpipe2.il", "w") as f
:
985 dut
= ExampleBufPipe()
986 test
= Test3(dut
, test3_resultfn
)
987 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe3.vcd")
990 dut
= ExamplePipeline()
991 test
= Test3(dut
, test3_resultfn
)
992 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_combpipe3.vcd")
995 dut
= ExampleBufPipe2()
996 run_simulation(dut
, testbench4(dut
), vcd_name
="test_bufpipe4.vcd")
999 dut
= ExampleBufPipeAdd()
1000 test
= Test5(dut
, test5_resultfn
, stage_ctl
=True)
1001 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe5.vcd")
1004 dut
= ExampleLTPipeline()
1005 test
= Test5(dut
, test6_resultfn
)
1006 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_ltcomb6.vcd")
1008 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1009 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1010 list(dut
.p
.i_data
) + [dut
.n
.o_data
]
1011 vl
= rtlil
.convert(dut
, ports
=ports
)
1012 with
open("test_ltcomb_pipe.il", "w") as f
:
1016 dut
= ExampleAddRecordPipe()
1018 test
= Test5(dut
, test7_resultfn
, data
=data
)
1019 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_addrecord.vcd")
1021 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1022 dut
.n
.o_valid
, dut
.p
.o_ready
,
1023 dut
.p
.i_data
.src1
, dut
.p
.i_data
.src2
,
1024 dut
.n
.o_data
.src1
, dut
.n
.o_data
.src2
]
1025 vl
= rtlil
.convert(dut
, ports
=ports
)
1026 with
open("test_recordcomb_pipe.il", "w") as f
:
1030 dut
= ExampleBufPipeAddClass()
1032 test
= Test5(dut
, test8_resultfn
, data
=data
)
1033 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe8.vcd")
1036 dut
= ExampleBufPipeChain2()
1037 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1038 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1039 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1040 vl
= rtlil
.convert(dut
, ports
=ports
)
1041 with
open("test_bufpipechain2.il", "w") as f
:
1044 data
= data_chain2()
1045 test
= Test5(dut
, test9_resultfn
, data
=data
)
1046 run_simulation(dut
, [test
.send
, test
.rcv
],
1047 vcd_name
="test_bufpipechain2.vcd")
1050 dut
= ExampleLTBufferedPipeDerived()
1051 test
= Test5(dut
, test6_resultfn
)
1052 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_ltbufpipe10.vcd")
1053 vl
= rtlil
.convert(dut
, ports
=ports
)
1054 with
open("test_ltbufpipe10.il", "w") as f
:
1058 dut
= ExampleAddRecordPlaceHolderPipe()
1059 data
=data_placeholder()
1060 test
= Test5(dut
, test11_resultfn
, data
=data
)
1061 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_addrecord.vcd")
1065 dut
= ExampleBufDelayedPipe()
1066 data
= data_chain1()
1067 test
= Test5(dut
, test12_resultfn
, data
=data
)
1068 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe12.vcd")
1069 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1070 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1071 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1072 vl
= rtlil
.convert(dut
, ports
=ports
)
1073 with
open("test_bufpipe12.il", "w") as f
:
1077 dut
= ExampleUnBufDelayedPipe()
1078 data
= data_chain1()
1079 test
= Test5(dut
, test12_resultfn
, data
=data
)
1080 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_unbufpipe13.vcd")
1081 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1082 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1083 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1084 vl
= rtlil
.convert(dut
, ports
=ports
)
1085 with
open("test_unbufpipe13.il", "w") as f
:
1089 dut
= ExampleBufModeAdd1Pipe()
1090 data
= data_chain1()
1091 test
= Test5(dut
, test12_resultfn
, data
=data
)
1092 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufunbuf15.vcd")
1093 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1094 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1095 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1096 vl
= rtlil
.convert(dut
, ports
=ports
)
1097 with
open("test_bufunbuf15.il", "w") as f
:
1101 dut
= ExampleBufModeUnBufPipe()
1102 data
= data_chain1()
1103 test
= Test5(dut
, test9_resultfn
, data
=data
)
1104 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufunbuf16.vcd")
1105 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1106 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1107 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1108 vl
= rtlil
.convert(dut
, ports
=ports
)
1109 with
open("test_bufunbuf16.il", "w") as f
:
1113 dut
= ExampleUnBufAdd1Pipe2()
1114 data
= data_chain1()
1115 test
= Test5(dut
, test12_resultfn
, data
=data
)
1116 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_unbufpipe17.vcd")
1117 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1118 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1119 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1120 vl
= rtlil
.convert(dut
, ports
=ports
)
1121 with
open("test_unbufpipe17.il", "w") as f
:
1125 dut
= PassThroughTest()
1126 data
= data_chain1()
1127 test
= Test5(dut
, test_identical_resultfn
, data
=data
)
1128 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_passthru18.vcd")
1129 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1130 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1131 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1132 vl
= rtlil
.convert(dut
, ports
=ports
)
1133 with
open("test_passthru18.il", "w") as f
:
1137 dut
= ExampleBufPassThruPipe()
1138 data
= data_chain1()
1139 test
= Test5(dut
, test9_resultfn
, data
=data
)
1140 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpass19.vcd")
1141 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1142 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1143 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1144 vl
= rtlil
.convert(dut
, ports
=ports
)
1145 with
open("test_bufpass19.il", "w") as f
:
1150 data
= data_chain1()
1151 test
= Test5(dut
, test_identical_resultfn
, data
=data
)
1152 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_fifo20.vcd")
1153 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1154 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1155 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1156 vl
= rtlil
.convert(dut
, ports
=ports
)
1157 with
open("test_fifo20.il", "w") as f
:
1161 dut
= ExampleFIFOPassThruPipe1()
1162 data
= data_chain1()
1163 test
= Test5(dut
, test12_resultfn
, data
=data
)
1164 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_fifopass21.vcd")
1165 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1166 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1167 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1168 vl
= rtlil
.convert(dut
, ports
=ports
)
1169 with
open("test_fifopass21.il", "w") as f
:
1173 dut
= ExampleRecordHandshakeAddClass()
1175 test
= Test5(dut
, test8_resultfn
, data
=data
)
1176 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_addrecord22.vcd")
1177 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1178 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1179 [dut
.p
.i_data
.op1
, dut
.p
.i_data
.op2
] + \
1181 vl
= rtlil
.convert(dut
, ports
=ports
)
1182 with
open("test_addrecord22.il", "w") as f
:
1187 dut
= ExampleFIFORecordObjectPipe()
1189 test
= Test5(dut
, test8_resultfn
, data
=data
)
1190 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_addrecord23.vcd")
1191 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1192 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1193 [dut
.p
.i_data
.op1
, dut
.p
.i_data
.op2
] + \
1195 vl
= rtlil
.convert(dut
, ports
=ports
)
1196 with
open("test_addrecord23.il", "w") as f
:
1200 dut
= ExampleBufPassThruPipe2()
1201 data
= data_chain1()
1202 test
= Test5(dut
, test9_resultfn
, data
=data
)
1203 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpass997.vcd")
1204 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1205 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1206 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1207 vl
= rtlil
.convert(dut
, ports
=ports
)
1208 with
open("test_bufpass997.il", "w") as f
:
1211 print ("test 998 (fails, bug)")
1212 dut
= ExampleBufPipe3()
1213 data
= data_chain1()
1214 test
= Test5(dut
, test9_resultfn
, data
=data
)
1215 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufpipe14.vcd")
1216 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1217 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1218 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1219 vl
= rtlil
.convert(dut
, ports
=ports
)
1220 with
open("test_bufpipe14.il", "w") as f
:
1223 print ("test 999 (expected to fail, which is a bug)")
1224 dut
= ExampleBufUnBufPipe()
1225 data
= data_chain1()
1226 test
= Test5(dut
, test9_resultfn
, data
=data
)
1227 run_simulation(dut
, [test
.send
, test
.rcv
], vcd_name
="test_bufunbuf999.vcd")
1228 ports
= [dut
.p
.i_valid
, dut
.n
.i_ready
,
1229 dut
.n
.o_valid
, dut
.p
.o_ready
] + \
1230 [dut
.p
.i_data
] + [dut
.n
.o_data
]
1231 vl
= rtlil
.convert(dut
, ports
=ports
)
1232 with
open("test_bufunbuf999.il", "w") as f
: