1 from random
import randint
2 from nmigen
import Module
, Signal
3 from nmigen
.compat
.sim
import run_simulation
4 from nmigen
.cli
import verilog
, rtlil
6 from nmigen_add_experiment
import InputGroup
10 stb
= yield dut
.out_op
.stb
12 ack
= yield dut
.out_op
.ack
16 yield dut
.rs
[1].in_op
[0].eq(5)
17 yield dut
.rs
[1].stb
.eq(0b01) # strobe indicate 1st op ready
18 #yield dut.rs[1].ack.eq(1)
21 # check row 1 output (should be inactive)
22 decode
= yield dut
.rs
[1].out_decode
25 op0
= yield dut
.rs
[1].out_op
[0]
26 op1
= yield dut
.rs
[1].out_op
[1]
27 assert op0
== 0 and op1
== 0
29 # output should be inactive
30 out_stb
= yield dut
.out_op
.stb
34 yield dut
.rs
[1].in_op
[1].eq(6)
35 yield dut
.rs
[1].stb
.eq(0b11) # strobe indicate both ops ready
37 # set acknowledgement of output... takes 1 cycle to respond
38 yield dut
.out_op
.ack
.eq(1)
40 yield dut
.out_op
.ack
.eq(0) # clear ack on output
41 yield dut
.rs
[1].stb
.eq(0) # clear row 1 strobe
43 # output strobe should be active, MID should be 0 until "ack" is set...
44 out_stb
= yield dut
.out_op
.stb
46 out_mid
= yield dut
.mid
49 # ... and output should not yet be passed through either
50 op0
= yield dut
.out_op
.v
[0]
51 op1
= yield dut
.out_op
.v
[1]
52 assert op0
== 0 and op1
== 0
54 # wait for out_op.ack to activate...
55 yield dut
.rs
[1].stb
.eq(0b00) # set row 1 strobes to zero
58 # *now* output should be passed through
59 op0
= yield dut
.out_op
.v
[0]
60 op1
= yield dut
.out_op
.v
[1]
61 assert op0
== 5 and op1
== 6
64 yield dut
.rs
[2].in_op
[0].eq(3)
65 yield dut
.rs
[2].in_op
[1].eq(4)
66 yield dut
.rs
[2].stb
.eq(0b11) # strobe indicate 1st op ready
67 yield dut
.out_op
.ack
.eq(1) # set output ack
69 yield dut
.rs
[2].stb
.eq(0) # clear row 2 strobe
70 yield dut
.out_op
.ack
.eq(0) # set output ack
72 op0
= yield dut
.out_op
.v
[0]
73 op1
= yield dut
.out_op
.v
[1]
74 assert op0
== 3 and op1
== 4, "op0 %d op1 %d" % (op0
, op1
)
75 out_mid
= yield dut
.mid
78 # set row 0 and 3 input
79 yield dut
.rs
[0].in_op
[0].eq(9)
80 yield dut
.rs
[0].in_op
[1].eq(8)
81 yield dut
.rs
[0].stb
.eq(0b11) # strobe indicate 1st op ready
82 yield dut
.rs
[3].in_op
[0].eq(1)
83 yield dut
.rs
[3].in_op
[1].eq(2)
84 yield dut
.rs
[3].stb
.eq(0b11) # strobe indicate 1st op ready
86 # set acknowledgement of output... takes 1 cycle to respond
87 yield dut
.out_op
.ack
.eq(1)
89 yield dut
.rs
[0].stb
.eq(0) # clear row 1 strobe
91 out_mid
= yield dut
.mid
92 assert out_mid
== 0, "out mid %d" % out_mid
95 yield dut
.rs
[3].stb
.eq(0) # clear row 1 strobe
96 yield dut
.out_op
.ack
.eq(0) # clear ack on output
98 out_mid
= yield dut
.mid
99 assert out_mid
== 3, "out mid %d" % out_mid
102 if __name__
== '__main__':
103 dut
= InputGroup(width
=32)
104 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
105 with
open("test_inputgroup.il", "w") as f
:
107 run_simulation(dut
, testbench(dut
), vcd_name
="test_inputgroup.vcd")