2 from random
import randint
3 from random
import seed
4 from operator
import mul
6 from nmigen
import Module
, Signal
7 from nmigen
.compat
.sim
import run_simulation
11 from unit_test_single
import (get_mantissa
, get_exponent
, get_sign
, is_nan
,
12 is_inf
, is_pos_inf
, is_neg_inf
,
13 match
, get_case
, check_case
, run_test
,
14 run_edge_cases
, run_corner_cases
)
18 yield from check_case(dut
, 0x40000000, 0x40000000, 0x40800000)
19 yield from check_case(dut
, 0x41400000, 0x40A00000, 0x42700000)
24 stimulus_a
= [0xba57711a, 0xbf9b1e94, 0x34082401, 0x5e8ef81,
26 stimulus_b
= [0xee1818c5, 0xc038ed3a, 0xb328cd45, 0x114f3db,
27 0x2f642a39, 0xff3807ab]
28 yield from run_test(dut
, stimulus_a
, stimulus_b
, mul
, get_case
)
29 count
+= len(stimulus_a
)
30 print (count
, "vectors passed")
32 yield from run_corner_cases(dut
, count
, mul
, get_case
)
33 yield from run_edge_cases(dut
, count
, mul
, get_case
)
36 if __name__
== '__main__':
38 run_simulation(dut
, testbench(dut
), vcd_name
="test_mul.vcd")