1 from random
import randint
3 from nmigen
import Module
, Signal
, Cat
4 from nmigen
.compat
.sim
import run_simulation
5 from nmigen
.cli
import verilog
, rtlil
7 from multipipe
import CombMuxOutPipe
8 from singlepipe
import UnbufferedPipeline
13 self
.mid
= Signal(2, reset_less
=True)
14 self
.data
= Signal(16, reset_less
=True)
17 return [self
.mid
.eq(i
.mid
), self
.data
.eq(i
.data
)]
20 return [self
.mid
, self
.data
]
23 class PassThroughStage
:
29 return Signal(16, name
="data_out", reset_less
=True)
35 class PassThroughDataStage
:
39 return self
.ispec() # same as ospec
42 return i
# pass-through
46 class PassThroughPipe(UnbufferedPipeline
):
48 UnbufferedPipeline
.__init
__(self
, PassThroughDataStage())
54 stb
= yield dut
.out_op
.stb
56 ack
= yield dut
.out_op
.ack
60 yield dut
.rs
[1].in_op
[0].eq(5)
61 yield dut
.rs
[1].stb
.eq(0b01) # strobe indicate 1st op ready
62 #yield dut.rs[1].ack.eq(1)
65 # check row 1 output (should be inactive)
66 decode
= yield dut
.rs
[1].out_decode
69 op0
= yield dut
.rs
[1].out_op
[0]
70 op1
= yield dut
.rs
[1].out_op
[1]
71 assert op0
== 0 and op1
== 0
73 # output should be inactive
74 out_stb
= yield dut
.out_op
.stb
78 yield dut
.rs
[1].in_op
[1].eq(6)
79 yield dut
.rs
[1].stb
.eq(0b11) # strobe indicate both ops ready
81 # set acknowledgement of output... takes 1 cycle to respond
82 yield dut
.out_op
.ack
.eq(1)
84 yield dut
.out_op
.ack
.eq(0) # clear ack on output
85 yield dut
.rs
[1].stb
.eq(0) # clear row 1 strobe
87 # output strobe should be active, MID should be 0 until "ack" is set...
88 out_stb
= yield dut
.out_op
.stb
90 out_mid
= yield dut
.mid
93 # ... and output should not yet be passed through either
94 op0
= yield dut
.out_op
.v
[0]
95 op1
= yield dut
.out_op
.v
[1]
96 assert op0
== 0 and op1
== 0
98 # wait for out_op.ack to activate...
99 yield dut
.rs
[1].stb
.eq(0b00) # set row 1 strobes to zero
102 # *now* output should be passed through
103 op0
= yield dut
.out_op
.v
[0]
104 op1
= yield dut
.out_op
.v
[1]
105 assert op0
== 5 and op1
== 6
108 yield dut
.rs
[2].in_op
[0].eq(3)
109 yield dut
.rs
[2].in_op
[1].eq(4)
110 yield dut
.rs
[2].stb
.eq(0b11) # strobe indicate 1st op ready
111 yield dut
.out_op
.ack
.eq(1) # set output ack
113 yield dut
.rs
[2].stb
.eq(0) # clear row 2 strobe
114 yield dut
.out_op
.ack
.eq(0) # set output ack
116 op0
= yield dut
.out_op
.v
[0]
117 op1
= yield dut
.out_op
.v
[1]
118 assert op0
== 3 and op1
== 4, "op0 %d op1 %d" % (op0
, op1
)
119 out_mid
= yield dut
.mid
122 # set row 0 and 3 input
123 yield dut
.rs
[0].in_op
[0].eq(9)
124 yield dut
.rs
[0].in_op
[1].eq(8)
125 yield dut
.rs
[0].stb
.eq(0b11) # strobe indicate 1st op ready
126 yield dut
.rs
[3].in_op
[0].eq(1)
127 yield dut
.rs
[3].in_op
[1].eq(2)
128 yield dut
.rs
[3].stb
.eq(0b11) # strobe indicate 1st op ready
130 # set acknowledgement of output... takes 1 cycle to respond
131 yield dut
.out_op
.ack
.eq(1)
133 yield dut
.rs
[0].stb
.eq(0) # clear row 1 strobe
135 out_mid
= yield dut
.mid
136 assert out_mid
== 0, "out mid %d" % out_mid
139 yield dut
.rs
[3].stb
.eq(0) # clear row 1 strobe
140 yield dut
.out_op
.ack
.eq(0) # clear ack on output
142 out_mid
= yield dut
.mid
143 assert out_mid
== 3, "out mid %d" % out_mid
147 def __init__(self
, dut
):
152 for i
in range(self
.tlen
* dut
.num_rows
):
156 mid
= randint(0, dut
.num_rows
-1)
157 data
= randint(0, 255) + (mid
<<8)
158 if mid
not in self
.do
:
160 self
.di
.append((data
, mid
))
161 self
.do
[mid
].append(data
)
164 for i
in range(self
.tlen
* dut
.num_rows
):
168 yield rs
.i_valid
.eq(1)
169 yield rs
.i_data
.data
.eq(op2
)
170 yield rs
.i_data
.mid
.eq(mid
)
172 o_p_ready
= yield rs
.o_ready
175 o_p_ready
= yield rs
.o_ready
177 print ("send", mid
, i
, hex(op2
))
179 yield rs
.i_valid
.eq(0)
180 # wait random period of time before queueing another value
181 for i
in range(randint(0, 3)):
184 yield rs
.i_valid
.eq(0)
189 stall_range
= randint(0, 3)
190 while out_i
!= len(self
.do
[mid
]):
192 assert count
!= 2000, "timeout: too long"
194 yield n
.i_ready
.eq(1)
196 o_n_valid
= yield n
.o_valid
197 i_n_ready
= yield n
.i_ready
198 if not o_n_valid
or not i_n_ready
:
201 out_v
= yield n
.o_data
203 print ("recv", mid
, out_i
, hex(out_v
))
205 assert self
.do
[mid
][out_i
] == out_v
# pass-through data
209 if randint(0, 5) == 0:
210 stall_range
= randint(0, 3)
211 stall
= randint(0, stall_range
) != 0
213 yield n
.i_ready
.eq(0)
214 for i
in range(stall_range
):
218 class TestPriorityMuxPipe(CombMuxOutPipe
):
219 def __init__(self
, num_rows
):
220 self
.num_rows
= num_rows
221 stage
= PassThroughStage()
222 CombMuxOutPipe
.__init
__(self
, stage
, n_len
=self
.num_rows
)
225 class TestSyncToPriorityPipe
:
228 self
.pipe
= PassThroughPipe()
229 self
.muxpipe
= TestPriorityMuxPipe(self
.num_rows
)
232 self
.n
= self
.muxpipe
.n
234 def elaborate(self
, platform
):
236 m
.submodules
+= self
.pipe
237 m
.submodules
+= self
.muxpipe
238 m
.d
.comb
+= self
.pipe
.n
.connect_to_next(self
.muxpipe
.p
)
242 res
= [self
.p
.i_valid
, self
.p
.o_ready
] + \
243 self
.p
.i_data
.ports()
244 for i
in range(len(self
.n
)):
245 res
+= [self
.n
[i
].i_ready
, self
.n
[i
].o_valid
] + \
247 #self.n[i].o_data.ports()
251 if __name__
== '__main__':
252 dut
= TestSyncToPriorityPipe()
253 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
254 with
open("test_outmux_pipe.il", "w") as f
:
256 #run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")
258 test
= OutputTest(dut
)
259 run_simulation(dut
, [test
.rcv(1), test
.rcv(0),
260 test
.rcv(3), test
.rcv(2),
262 vcd_name
="test_outmux_pipe.vcd")