2 * Copyright © 2014 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
28 ****************************************************************************************************
30 * @brief Contains the Addr::Lib base class definition.
31 ****************************************************************************************************
34 #ifndef __ADDR_LIB_H__
35 #define __ADDR_LIB_H__
37 #include "addrinterface.h"
38 #include "addrobject.h"
39 #include "addrelemlib.h"
42 #include "amdgpu_id.h"
47 #ifndef CIASICIDGFXENGINE_R600
48 #define CIASICIDGFXENGINE_R600 0x00000006
51 #ifndef CIASICIDGFXENGINE_R800
52 #define CIASICIDGFXENGINE_R800 0x00000008
55 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
56 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
59 #ifndef CIASICIDGFXENGINE_ARCTICISLAND
60 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
67 ****************************************************************************************************
68 * @brief Neutral enums that define pipeinterleave
69 ****************************************************************************************************
73 ADDR_PIPEINTERLEAVE_256B
= 256,
74 ADDR_PIPEINTERLEAVE_512B
= 512,
75 ADDR_PIPEINTERLEAVE_1KB
= 1024,
76 ADDR_PIPEINTERLEAVE_2KB
= 2048,
80 ****************************************************************************************************
81 * @brief Neutral enums that define DRAM row size
82 ****************************************************************************************************
86 ADDR_ROWSIZE_1KB
= 1024,
87 ADDR_ROWSIZE_2KB
= 2048,
88 ADDR_ROWSIZE_4KB
= 4096,
89 ADDR_ROWSIZE_8KB
= 8192,
93 ****************************************************************************************************
94 * @brief Neutral enums that define bank interleave
95 ****************************************************************************************************
99 ADDR_BANKINTERLEAVE_1
= 1,
100 ADDR_BANKINTERLEAVE_2
= 2,
101 ADDR_BANKINTERLEAVE_4
= 4,
102 ADDR_BANKINTERLEAVE_8
= 8,
106 ****************************************************************************************************
107 * @brief Neutral enums that define shader engine tile size
108 ****************************************************************************************************
110 enum ShaderEngineTileSize
112 ADDR_SE_TILESIZE_16
= 16,
113 ADDR_SE_TILESIZE_32
= 32,
117 ****************************************************************************************************
118 * @brief Neutral enums that define bank swap size
119 ****************************************************************************************************
123 ADDR_BANKSWAP_128B
= 128,
124 ADDR_BANKSWAP_256B
= 256,
125 ADDR_BANKSWAP_512B
= 512,
126 ADDR_BANKSWAP_1KB
= 1024,
130 ****************************************************************************************************
131 * @brief This class contains asic independent address lib functionalities
132 ****************************************************************************************************
134 class Lib
: public Object
139 static ADDR_E_RETURNCODE
Create(
140 const ADDR_CREATE_INPUT
* pCreateInfo
, ADDR_CREATE_OUTPUT
* pCreateOut
);
148 static Lib
* GetLib(ADDR_HANDLE hLib
);
150 /// Returns AddrLib version (from compiled binary instead include file)
156 /// Returns asic chip family name defined by AddrLib
157 ChipFamily
GetChipFamily()
162 ADDR_E_RETURNCODE
Flt32ToDepthPixel(
163 const ELEM_FLT32TODEPTHPIXEL_INPUT
* pIn
,
164 ELEM_FLT32TODEPTHPIXEL_OUTPUT
* pOut
) const;
166 ADDR_E_RETURNCODE
Flt32ToColorPixel(
167 const ELEM_FLT32TOCOLORPIXEL_INPUT
* pIn
,
168 ELEM_FLT32TOCOLORPIXEL_OUTPUT
* pOut
) const;
170 BOOL_32
GetExportNorm(const ELEM_GETEXPORTNORM_INPUT
* pIn
) const;
172 ADDR_E_RETURNCODE
GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT
* pOut
) const;
175 Lib(); // Constructor is protected
176 Lib(const Client
* pClient
);
178 /// Pure virtual function to get max alignments
179 virtual ADDR_E_RETURNCODE
HwlGetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT
* pOut
) const = 0;
184 /// Pure Virtual function for Hwl computing internal global parameters from h/w registers
185 virtual BOOL_32
HwlInitGlobalParams(const ADDR_CREATE_INPUT
* pCreateIn
) = 0;
187 /// Pure Virtual function for Hwl converting chip family
188 virtual ChipFamily
HwlConvertChipFamily(UINT_32 uChipFamily
, UINT_32 uChipRevision
) = 0;
190 /// Get equation table pointer and number of equations
191 virtual UINT_32
HwlGetEquationTableInfo(const ADDR_EQUATION
** ppEquationTable
) const
193 *ppEquationTable
= NULL
;
201 static UINT_32
Bits2Number(UINT_32 bitNum
, ...);
203 static UINT_32
GetNumFragments(UINT_32 numSamples
, UINT_32 numFrags
)
205 return (numFrags
!= 0) ? numFrags
: Max(1u, numSamples
);
208 /// Returns pointer of ElemLib
209 ElemLib
* GetElemLib() const
214 /// Returns fillSizeFields flag
215 UINT_32
GetFillSizeFieldsFlags() const
217 return m_configFlags
.fillSizeFields
;
221 // Disallow the copy constructor
224 // Disallow the assignment operator
225 Lib
& operator=(const Lib
& a
);
227 VOID
SetChipFamily(UINT_32 uChipFamily
, UINT_32 uChipRevision
);
229 VOID
SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels
);
232 LibClass m_class
; ///< Store class type (HWL type)
234 ChipFamily m_chipFamily
; ///< Chip family translated from the one in atiid.h
236 UINT_32 m_chipRevision
; ///< Revision id from xxx_id.h
238 UINT_32 m_version
; ///< Current version
243 ConfigFlags m_configFlags
; ///< Global configuration flags. Note this is setup by
244 /// AddrLib instead of Client except forceLinearAligned
246 UINT_32 m_pipes
; ///< Number of pipes
247 UINT_32 m_banks
; ///< Number of banks
248 /// For r800 this is MC_ARB_RAMCFG.NOOFBANK
249 /// Keep it here to do default parameter calculation
251 UINT_32 m_pipeInterleaveBytes
;
252 ///< Specifies the size of contiguous address space
253 /// within each tiling pipe when making linear
254 /// accesses. (Formerly Group Size)
256 UINT_32 m_rowSize
; ///< DRAM row size, in bytes
258 UINT_32 m_minPitchAlignPixels
; ///< Minimum pitch alignment in pixels
259 UINT_32 m_maxSamples
; ///< Max numSamples
261 ElemLib
* m_pElemLib
; ///< Element Lib pointer
264 Lib
* SiHwlInit (const Client
* pClient
);
265 Lib
* CiHwlInit (const Client
* pClient
);
266 Lib
* Gfx9HwlInit (const Client
* pClient
);