src/amd/addrlib/core/addrlib.h

   1 /*
   2  * Copyright © 2014 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  14  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  15  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  16  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  17  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  */
  26
  27 /**
  28 ***************************************************************************************************
  29 * @file  addrlib.h
  30 * @brief Contains the AddrLib base class definition.
  31 ***************************************************************************************************
  32 */
  33
  34 #ifndef __ADDR_LIB_H__
  35 #define __ADDR_LIB_H__
  36
  37
  38 #include "addrinterface.h"
  39 #include "addrobject.h"
  40 #include "addrelemlib.h"
  41
  42 #if BRAHMA_BUILD
  43 #include "amdgpu_id.h"
  44 #else
  45 #include "atiid.h"
  46 #endif
  47
  48 #ifndef CIASICIDGFXENGINE_R600
  49 #define CIASICIDGFXENGINE_R600 0x00000006
  50 #endif
  51
  52 #ifndef CIASICIDGFXENGINE_R800
  53 #define CIASICIDGFXENGINE_R800 0x00000008
  54 #endif
  55
  56 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  57 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  58 #endif
  59
  60 #ifndef CIASICIDGFXENGINE_SEAISLAND
  61 #define CIASICIDGFXENGINE_SEAISLAND 0x0000000B
  62 #endif
  63 /**
  64 ***************************************************************************************************
  65 * @brief Neutral enums that define pipeinterleave
  66 ***************************************************************************************************
  67 */
  68 enum AddrPipeInterleave
  69 {
  70     ADDR_PIPEINTERLEAVE_256B = 256,
  71     ADDR_PIPEINTERLEAVE_512B = 512,
  72 };
  73
  74 /**
  75 ***************************************************************************************************
  76 * @brief Neutral enums that define DRAM row size
  77 ***************************************************************************************************
  78 */
  79 enum AddrRowSize
  80 {
  81     ADDR_ROWSIZE_1KB = 1024,
  82     ADDR_ROWSIZE_2KB = 2048,
  83     ADDR_ROWSIZE_4KB = 4096,
  84     ADDR_ROWSIZE_8KB = 8192,
  85 };
  86
  87 /**
  88 ***************************************************************************************************
  89 * @brief Neutral enums that define bank interleave
  90 ***************************************************************************************************
  91 */
  92 enum AddrBankInterleave
  93 {
  94     ADDR_BANKINTERLEAVE_1 = 1,
  95     ADDR_BANKINTERLEAVE_2 = 2,
  96     ADDR_BANKINTERLEAVE_4 = 4,
  97     ADDR_BANKINTERLEAVE_8 = 8,
  98 };
  99
 100 /**
 101 ***************************************************************************************************
 102 * @brief Neutral enums that define MGPU chip tile size
 103 ***************************************************************************************************
 104 */
 105 enum AddrChipTileSize
 106 {
 107     ADDR_CHIPTILESIZE_16 = 16,
 108     ADDR_CHIPTILESIZE_32 = 32,
 109     ADDR_CHIPTILESIZE_64 = 64,
 110     ADDR_CHIPTILESIZE_128 = 128,
 111 };
 112
 113 /**
 114 ***************************************************************************************************
 115 * @brief Neutral enums that define shader engine tile size
 116 ***************************************************************************************************
 117 */
 118 enum AddrEngTileSize
 119 {
 120     ADDR_SE_TILESIZE_16 = 16,
 121     ADDR_SE_TILESIZE_32 = 32,
 122 };
 123
 124 /**
 125 ***************************************************************************************************
 126 * @brief Neutral enums that define bank swap size
 127 ***************************************************************************************************
 128 */
 129 enum AddrBankSwapSize
 130 {
 131     ADDR_BANKSWAP_128B = 128,
 132     ADDR_BANKSWAP_256B = 256,
 133     ADDR_BANKSWAP_512B = 512,
 134     ADDR_BANKSWAP_1KB = 1024,
 135 };
 136
 137
 138 /**
 139 ***************************************************************************************************
 140 * @brief This class contains asic independent address lib functionalities
 141 ***************************************************************************************************
 142 */
 143 class AddrLib : public AddrObject
 144 {
 145 public:
 146     virtual ~AddrLib();
 147
 148     static ADDR_E_RETURNCODE Create(
 149         const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut);
 150
 151     /// Pair of Create
 152     VOID Destroy()
 153     {
 154         delete this;
 155     }
 156
 157     static AddrLib* GetAddrLib(
 158         ADDR_HANDLE hLib);
 159
 160     /// Returns AddrLib version (from compiled binary instead include file)
 161     UINT_32 GetVersion()
 162     {
 163         return m_version;
 164     }
 165
 166     /// Returns asic chip family name defined by AddrLib
 167     AddrChipFamily GetAddrChipFamily()
 168     {
 169         return m_chipFamily;
 170     }
 171
 172     ADDR_E_RETURNCODE Flt32ToDepthPixel(
 173         const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
 174         ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const;
 175
 176     ADDR_E_RETURNCODE Flt32ToColorPixel(
 177         const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
 178         ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const;
 179
 180     BOOL_32 GetExportNorm(
 181         const ELEM_GETEXPORTNORM_INPUT* pIn) const;
 182
 183     ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const;
 184
 185 protected:
 186     AddrLib();  // Constructor is protected
 187     AddrLib(const AddrClient* pClient);
 188
 189     /// Pure virtual function to get max alignments
 190     virtual ADDR_E_RETURNCODE HwlGetMaxAlignments(ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut) const = 0;
 191
 192     //
 193     // Initialization
 194     //
 195     /// Pure Virtual function for Hwl computing internal global parameters from h/w registers
 196     virtual BOOL_32 HwlInitGlobalParams(
 197         const ADDR_CREATE_INPUT* pCreateIn) = 0;
 198
 199     /// Pure Virtual function for Hwl converting chip family
 200     virtual AddrChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0;
 201
 202     //
 203     // Misc helper
 204     //
 205     static UINT_32 Bits2Number(UINT_32 bitNum,...);
 206
 207     static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags)
 208     {
 209         return numFrags != 0 ? numFrags : Max(1u, numSamples);
 210     }
 211
 212     /// Returns pointer of AddrElemLib
 213     AddrElemLib* GetElemLib() const
 214     {
 215         return m_pElemLib;
 216     }
 217
 218     /// Returns fillSizeFields flag
 219     UINT_32 GetFillSizeFieldsFlags() const
 220     {
 221         return m_configFlags.fillSizeFields;
 222     }
 223
 224 private:
 225     // Disallow the copy constructor
 226     AddrLib(const AddrLib& a);
 227
 228     // Disallow the assignment operator
 229     AddrLib& operator=(const AddrLib& a);
 230
 231     VOID SetAddrChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision);
 232
 233     VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels);
 234
 235 protected:
 236     AddrLibClass        m_class;        ///< Store class type (HWL type)
 237
 238     AddrChipFamily      m_chipFamily;   ///< Chip family translated from the one in atiid.h
 239
 240     UINT_32             m_chipRevision; ///< Revision id from xxx_id.h
 241
 242     UINT_32             m_version;      ///< Current version
 243
 244     //
 245     // Global parameters
 246     //
 247     ADDR_CONFIG_FLAGS   m_configFlags;  ///< Global configuration flags. Note this is setup by
 248                                         ///  AddrLib instead of Client except forceLinearAligned
 249
 250     UINT_32             m_pipes;        ///< Number of pipes
 251     UINT_32             m_banks;        ///< Number of banks
 252                                         ///  For r800 this is MC_ARB_RAMCFG.NOOFBANK
 253                                         ///  Keep it here to do default parameter calculation
 254
 255     UINT_32             m_pipeInterleaveBytes;
 256                                         ///< Specifies the size of contiguous address space
 257                                         ///  within each tiling pipe when making linear
 258                                         ///  accesses. (Formerly Group Size)
 259
 260     UINT_32             m_rowSize;      ///< DRAM row size, in bytes
 261
 262     UINT_32             m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels
 263     UINT_32             m_maxSamples;   ///< Max numSamples
 264 private:
 265     AddrElemLib*        m_pElemLib;     ///< Element Lib pointer
 266 };
 267
 268 AddrLib* AddrSIHwlInit  (const AddrClient* pClient);
 269 AddrLib* AddrCIHwlInit  (const AddrClient* pClient);
 270
 271 #endif
 272