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[mesa.git] / src / amd / addrlib / core / addrlib2.h
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 /**
28 ************************************************************************************************************************
29 * @file addrlib2.h
30 * @brief Contains the Addr::V2::Lib class definition.
31 ************************************************************************************************************************
32 */
33
34 #ifndef __ADDR2_LIB2_H__
35 #define __ADDR2_LIB2_H__
36
37 #include "addrlib.h"
38
39 namespace Addr
40 {
41 namespace V2
42 {
43
44 /**
45 ************************************************************************************************************************
46 * @brief Flags for SwizzleModeTable
47 ************************************************************************************************************************
48 */
49 struct SwizzleModeFlags
50 {
51 // Swizzle mode
52 UINT_32 isLinear : 1; // Linear
53
54 // Block size
55 UINT_32 is256b : 1; // Block size is 256B
56 UINT_32 is4kb : 1; // Block size is 4KB
57 UINT_32 is64kb : 1; // Block size is 64KB
58 UINT_32 isVar : 1; // Block size is variable
59
60 UINT_32 isZ : 1; // Z order swizzle mode
61 UINT_32 isStd : 1; // Standard swizzle mode
62 UINT_32 isDisp : 1; // Display swizzle mode
63 UINT_32 isRot : 1; // Rotate swizzle mode
64
65 // XOR mode
66 UINT_32 isXor : 1; // XOR after swizzle if set
67
68 UINT_32 isT : 1; // T mode
69
70 UINT_32 isRtOpt : 1; // mode opt for render target
71 };
72
73 struct Dim2d
74 {
75 UINT_32 w;
76 UINT_32 h;
77 };
78
79 struct Dim3d
80 {
81 UINT_32 w;
82 UINT_32 h;
83 UINT_32 d;
84 };
85
86 /**
87 ************************************************************************************************************************
88 * @brief This class contains asic independent address lib functionalities
89 ************************************************************************************************************************
90 */
91 class Lib : public Addr::Lib
92 {
93 public:
94 virtual ~Lib();
95
96 static Lib* GetLib(
97 ADDR_HANDLE hLib);
98
99 //
100 // Interface stubs
101 //
102
103 // For data surface
104 ADDR_E_RETURNCODE ComputeSurfaceInfo(
105 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
106 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
107
108 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord(
109 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
110 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
111
112 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr(
113 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
114 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
115
116 // For HTile
117 ADDR_E_RETURNCODE ComputeHtileInfo(
118 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
119 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const;
120
121 ADDR_E_RETURNCODE ComputeHtileAddrFromCoord(
122 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
123 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const;
124
125 ADDR_E_RETURNCODE ComputeHtileCoordFromAddr(
126 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
127 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const;
128
129 // For CMask
130 ADDR_E_RETURNCODE ComputeCmaskInfo(
131 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
132 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const;
133
134 ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord(
135 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
136 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
137
138 ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr(
139 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
140 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const;
141
142 // For FMask
143 ADDR_E_RETURNCODE ComputeFmaskInfo(
144 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
145 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
146
147 ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord(
148 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
149 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
150
151 ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr(
152 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
153 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
154
155 // For DCC key
156 ADDR_E_RETURNCODE ComputeDccInfo(
157 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
158 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const;
159
160 ADDR_E_RETURNCODE ComputeDccAddrFromCoord(
161 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
162 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const;
163
164 // Misc
165 ADDR_E_RETURNCODE ComputePipeBankXor(
166 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
167 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
168
169 ADDR_E_RETURNCODE ComputeSlicePipeBankXor(
170 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
171 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);
172
173 ADDR_E_RETURNCODE ComputeSubResourceOffsetForSwizzlePattern(
174 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
175 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
176
177 ADDR_E_RETURNCODE Addr2GetPreferredSurfaceSetting(
178 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
179 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const;
180
181 virtual BOOL_32 IsValidDisplaySwizzleMode(
182 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
183 {
184 ADDR_NOT_IMPLEMENTED();
185 return ADDR_NOTIMPLEMENTED;
186 }
187
188 protected:
189 Lib(); // Constructor is protected
190 Lib(const Client* pClient);
191
192 static const UINT_32 MaxNumOfBpp = 5;
193
194 static const Dim2d Block256_2d[MaxNumOfBpp];
195 static const Dim3d Block1K_3d[MaxNumOfBpp];
196
197 static const UINT_32 PrtAlignment = 64 * 1024;
198 static const UINT_32 MaxMacroBits = 20;
199
200 // Checking block size
201 BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const
202 {
203 return m_swizzleModeTable[swizzleMode].is256b;
204 }
205
206 BOOL_32 IsBlock4kb(AddrSwizzleMode swizzleMode) const
207 {
208 return m_swizzleModeTable[swizzleMode].is4kb;
209 }
210
211 BOOL_32 IsBlock64kb(AddrSwizzleMode swizzleMode) const
212 {
213 return m_swizzleModeTable[swizzleMode].is64kb;
214 }
215
216 BOOL_32 IsBlockVariable(AddrSwizzleMode swizzleMode) const
217 {
218 return m_swizzleModeTable[swizzleMode].isVar;
219 }
220
221 // Checking swizzle mode
222 BOOL_32 IsLinear(AddrSwizzleMode swizzleMode) const
223 {
224 return m_swizzleModeTable[swizzleMode].isLinear;
225 }
226
227 BOOL_32 IsRtOptSwizzle(AddrSwizzleMode swizzleMode) const
228 {
229 return m_swizzleModeTable[swizzleMode].isRtOpt;
230 }
231
232 BOOL_32 IsZOrderSwizzle(AddrSwizzleMode swizzleMode) const
233 {
234 return m_swizzleModeTable[swizzleMode].isZ;
235 }
236
237 BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
238 {
239 return HwlIsStandardSwizzle(resourceType, swizzleMode);
240 }
241
242 BOOL_32 IsDisplaySwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
243 {
244 return HwlIsDisplaySwizzle(resourceType, swizzleMode);
245 }
246
247 BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const
248 {
249 return m_swizzleModeTable[swizzleMode].isRot;
250 }
251
252 BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const
253 {
254 return m_swizzleModeTable[swizzleMode].isXor;
255 }
256
257 BOOL_32 IsPrt(AddrSwizzleMode swizzleMode) const
258 {
259 return m_swizzleModeTable[swizzleMode].isT;
260 }
261
262 BOOL_32 IsNonPrtXor(AddrSwizzleMode swizzleMode) const
263 {
264 return (IsXor(swizzleMode) && (IsPrt(swizzleMode) == FALSE));
265 }
266
267 // Checking resource type
268 static BOOL_32 IsTex1d(AddrResourceType resourceType)
269 {
270 return (resourceType == ADDR_RSRC_TEX_1D);
271 }
272
273 static BOOL_32 IsTex2d(AddrResourceType resourceType)
274 {
275 return (resourceType == ADDR_RSRC_TEX_2D);
276 }
277
278 static BOOL_32 IsTex3d(AddrResourceType resourceType)
279 {
280 return (resourceType == ADDR_RSRC_TEX_3D);
281 }
282
283 BOOL_32 IsThick(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
284 {
285 return HwlIsThick(resourceType, swizzleMode);
286 }
287
288 BOOL_32 IsThin(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const
289 {
290 return HwlIsThin(resourceType, swizzleMode);
291 }
292
293 UINT_32 GetBlockSizeLog2(AddrSwizzleMode swizzleMode) const
294 {
295 UINT_32 blockSizeLog2 = 0;
296
297 if (IsBlock256b(swizzleMode) || IsLinear(swizzleMode))
298 {
299 blockSizeLog2 = 8;
300 }
301 else if (IsBlock4kb(swizzleMode))
302 {
303 blockSizeLog2 = 12;
304 }
305 else if (IsBlock64kb(swizzleMode))
306 {
307 blockSizeLog2 = 16;
308 }
309 else if (IsBlockVariable(swizzleMode))
310 {
311 blockSizeLog2 = m_blockVarSizeLog2;
312 }
313 else
314 {
315 ADDR_ASSERT_ALWAYS();
316 }
317
318 return blockSizeLog2;
319 }
320
321 UINT_32 GetBlockSize(AddrSwizzleMode swizzleMode) const
322 {
323 return (1 << GetBlockSizeLog2(swizzleMode));
324 }
325
326 static UINT_32 GetFmaskBpp(UINT_32 sample, UINT_32 frag)
327 {
328 sample = (sample == 0) ? 1 : sample;
329 frag = (frag == 0) ? sample : frag;
330
331 UINT_32 fmaskBpp = QLog2(frag);
332
333 if (sample > frag)
334 {
335 fmaskBpp++;
336 }
337
338 if (fmaskBpp == 3)
339 {
340 fmaskBpp = 4;
341 }
342
343 fmaskBpp = Max(8u, fmaskBpp * sample);
344
345 return fmaskBpp;
346 }
347
348 virtual BOOL_32 HwlIsStandardSwizzle(
349 AddrResourceType resourceType,
350 AddrSwizzleMode swizzleMode) const
351 {
352 ADDR_NOT_IMPLEMENTED();
353 return FALSE;
354 }
355
356 virtual BOOL_32 HwlIsDisplaySwizzle(
357 AddrResourceType resourceType,
358 AddrSwizzleMode swizzleMode) const
359 {
360 ADDR_NOT_IMPLEMENTED();
361 return FALSE;
362 }
363
364 virtual BOOL_32 HwlIsThin(
365 AddrResourceType resourceType,
366 AddrSwizzleMode swizzleMode) const
367 {
368 ADDR_NOT_IMPLEMENTED();
369 return FALSE;
370 }
371
372 virtual BOOL_32 HwlIsThick(
373 AddrResourceType resourceType,
374 AddrSwizzleMode swizzleMode) const
375 {
376 ADDR_NOT_IMPLEMENTED();
377 return FALSE;
378 }
379
380 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo(
381 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
382 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const
383 {
384 ADDR_NOT_IMPLEMENTED();
385 return ADDR_NOTSUPPORTED;
386 }
387
388 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo(
389 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
390 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const
391 {
392 ADDR_NOT_IMPLEMENTED();
393 return ADDR_NOTSUPPORTED;
394 }
395
396 virtual ADDR_E_RETURNCODE HwlComputeDccInfo(
397 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
398 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const
399 {
400 ADDR_NOT_IMPLEMENTED();
401 return ADDR_NOTSUPPORTED;
402 }
403
404 virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord(
405 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
406 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) const
407 {
408 ADDR_NOT_IMPLEMENTED();
409 return ADDR_NOTSUPPORTED;
410 }
411
412 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord(
413 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
414 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) const
415 {
416 ADDR_NOT_IMPLEMENTED();
417 return ADDR_NOTSUPPORTED;
418 }
419
420 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord(
421 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
422 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) const
423 {
424 ADDR_NOT_IMPLEMENTED();
425 return ADDR_NOTSUPPORTED;
426 }
427
428 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr(
429 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
430 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) const
431 {
432 ADDR_NOT_IMPLEMENTED();
433 return ADDR_NOTSUPPORTED;
434 }
435
436 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation(
437 AddrResourceType rsrcType,
438 AddrSwizzleMode swMode,
439 UINT_32 elementBytesLog2,
440 ADDR_EQUATION* pEquation) const
441 {
442 ADDR_NOT_IMPLEMENTED();
443 return ADDR_NOTSUPPORTED;
444 }
445
446 virtual ADDR_E_RETURNCODE HwlComputeThinEquation(
447 AddrResourceType rsrcType,
448 AddrSwizzleMode swMode,
449 UINT_32 elementBytesLog2,
450 ADDR_EQUATION* pEquation) const
451 {
452 ADDR_NOT_IMPLEMENTED();
453 return ADDR_NOTSUPPORTED;
454 }
455
456 virtual ADDR_E_RETURNCODE HwlComputeThickEquation(
457 AddrResourceType rsrcType,
458 AddrSwizzleMode swMode,
459 UINT_32 elementBytesLog2,
460 ADDR_EQUATION* pEquation) const
461 {
462 ADDR_NOT_IMPLEMENTED();
463 return ADDR_NOTSUPPORTED;
464 }
465
466 virtual UINT_32 HwlGetEquationIndex(
467 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
468 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
469 {
470 ADDR_NOT_IMPLEMENTED();
471 return ADDR_INVALID_EQUATION_INDEX;
472 }
473
474 UINT_32 GetEquationIndex(
475 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
476 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
477 {
478 return HwlGetEquationIndex(pIn, pOut);
479 }
480
481 virtual UINT_32 HwlComputeSurfaceBaseAlign(AddrSwizzleMode swizzleMode) const
482 {
483 ADDR_NOT_IMPLEMENTED();
484 return 0;
485 }
486
487 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor(
488 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
489 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const
490 {
491 ADDR_NOT_IMPLEMENTED();
492 return ADDR_NOTSUPPORTED;
493 }
494
495 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor(
496 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
497 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const
498 {
499 ADDR_NOT_IMPLEMENTED();
500 return ADDR_NOTSUPPORTED;
501 }
502
503
504 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern(
505 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
506 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const
507 {
508 ADDR_NOT_IMPLEMENTED();
509 return ADDR_NOTSUPPORTED;
510 }
511
512 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting(
513 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
514 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const
515 {
516 ADDR_NOT_IMPLEMENTED();
517 return ADDR_NOTSUPPORTED;
518 }
519
520 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck(
521 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
522 {
523 ADDR_NOT_IMPLEMENTED();
524 return ADDR_NOTSUPPORTED;
525 }
526
527 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled(
528 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
529 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const
530 {
531 ADDR_NOT_IMPLEMENTED();
532 return ADDR_NOTIMPLEMENTED;
533 }
534
535 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled(
536 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
537 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const
538 {
539 ADDR_NOT_IMPLEMENTED();
540 return ADDR_NOTIMPLEMENTED;
541 }
542
543 ADDR_E_RETURNCODE ComputeBlock256Equation(
544 AddrResourceType rsrcType,
545 AddrSwizzleMode swMode,
546 UINT_32 elementBytesLog2,
547 ADDR_EQUATION* pEquation) const;
548
549 ADDR_E_RETURNCODE ComputeThinEquation(
550 AddrResourceType rsrcType,
551 AddrSwizzleMode swMode,
552 UINT_32 elementBytesLog2,
553 ADDR_EQUATION* pEquation) const;
554
555 ADDR_E_RETURNCODE ComputeThickEquation(
556 AddrResourceType rsrcType,
557 AddrSwizzleMode swMode,
558 UINT_32 elementBytesLog2,
559 ADDR_EQUATION* pEquation) const;
560
561 ADDR_E_RETURNCODE ComputeSurfaceInfoSanityCheck(
562 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const;
563
564 ADDR_E_RETURNCODE ComputeSurfaceInfoLinear(
565 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
566 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
567
568 ADDR_E_RETURNCODE ComputeSurfaceLinearPadding(
569 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
570 UINT_32* pMipmap0PaddedWidth,
571 UINT_32* pSlice0PaddedHeight,
572 ADDR2_MIP_INFO* pMipInfo = NULL) const;
573
574 ADDR_E_RETURNCODE ComputeSurfaceInfoTiled(
575 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
576 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
577
578 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordLinear(
579 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
580 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
581
582 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordTiled(
583 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
584 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
585
586 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrLinear(
587 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
588 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
589
590 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrTiled(
591 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
592 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
593
594 UINT_32 ComputeSurface2DMicroBlockOffset(
595 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const;
596
597 UINT_32 ComputeSurface3DMicroBlockOffset(
598 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const;
599
600 // Misc
601 ADDR_E_RETURNCODE ComputeBlockDimensionForSurf(
602 UINT_32* pWidth,
603 UINT_32* pHeight,
604 UINT_32* pDepth,
605 UINT_32 bpp,
606 UINT_32 numSamples,
607 AddrResourceType resourceType,
608 AddrSwizzleMode swizzleMode) const;
609
610 ADDR_E_RETURNCODE ComputeBlockDimension(
611 UINT_32* pWidth,
612 UINT_32* pHeight,
613 UINT_32* pDepth,
614 UINT_32 bpp,
615 AddrResourceType resourceType,
616 AddrSwizzleMode swizzleMode) const;
617
618 static UINT_64 ComputePadSize(
619 const Dim3d* pBlkDim,
620 UINT_32 width,
621 UINT_32 height,
622 UINT_32 numSlices,
623 Dim3d* pPadDim)
624 {
625 pPadDim->w = PowTwoAlign(width ,pBlkDim->w);
626 pPadDim->h = PowTwoAlign(height ,pBlkDim->h);
627 pPadDim->d = PowTwoAlign(numSlices, pBlkDim->d);
628 return static_cast<UINT_64>(pPadDim->w) * pPadDim->h * pPadDim->d;
629 }
630
631 static ADDR_E_RETURNCODE ExtractPipeBankXor(
632 UINT_32 pipeBankXor,
633 UINT_32 bankBits,
634 UINT_32 pipeBits,
635 UINT_32* pBankX,
636 UINT_32* pPipeX);
637
638 static BOOL_32 Valid3DMipSliceIdConstraint(
639 UINT_32 numSlices,
640 UINT_32 mipId,
641 UINT_32 slice)
642 {
643 return (Max((numSlices >> mipId), 1u) > slice);
644 }
645
646 Dim3d GetMipTailDim(
647 AddrResourceType resourceType,
648 AddrSwizzleMode swizzleMode,
649 UINT_32 blockWidth,
650 UINT_32 blockHeight,
651 UINT_32 blockDepth) const;
652
653 BOOL_32 IsInMipTail(
654 AddrResourceType resourceType,
655 AddrSwizzleMode swizzleMode,
656 Dim3d mipTailDim,
657 UINT_32 width,
658 UINT_32 height,
659 UINT_32 depth) const
660 {
661 BOOL_32 inTail = ((width <= mipTailDim.w) &&
662 (height <= mipTailDim.h) &&
663 (IsThin(resourceType, swizzleMode) || (depth <= mipTailDim.d)));
664
665 return inTail;
666 }
667
668 static BOOL_32 IsLocalHeap(AddrResrouceLocation resourceType)
669 {
670 return ((resourceType == ADDR_RSRC_LOC_LOCAL) ||
671 (resourceType == ADDR_RSRC_LOC_INVIS));
672 }
673
674 static BOOL_32 IsInvisibleHeap(AddrResrouceLocation resourceType)
675 {
676 return (resourceType == ADDR_RSRC_LOC_INVIS);
677 }
678
679 static BOOL_32 IsNonlocalHeap(AddrResrouceLocation resourceType)
680 {
681 return ((resourceType == ADDR_RSRC_LOC_USWC) ||
682 (resourceType == ADDR_RSRC_LOC_CACHED));
683 }
684
685 UINT_32 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const
686 {
687 UINT_32 numPipeLog2 = pipeAligned ? Min(m_pipesLog2 + m_seLog2, 5u) : 0;
688
689 if (IsXor(swizzleMode))
690 {
691 UINT_32 maxPipeLog2 = GetBlockSizeLog2(swizzleMode) - m_pipeInterleaveLog2;
692
693 numPipeLog2 = Min(numPipeLog2, maxPipeLog2);
694 }
695
696 return numPipeLog2;
697 }
698
699 UINT_32 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const
700 {
701 return (1 << GetPipeLog2ForMetaAddressing(pipeAligned, swizzleMode));
702 }
703
704 VOID VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const
705 {
706 #if DEBUG
707 if (pIn->numMipLevels > 1)
708 {
709 UINT_32 actualMipLevels = 1;
710 switch (pIn->resourceType)
711 {
712 case ADDR_RSRC_TEX_3D:
713 // Fall through to share 2D case
714 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->numSlices) + 1);
715 case ADDR_RSRC_TEX_2D:
716 // Fall through to share 1D case
717 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->height) + 1);
718 case ADDR_RSRC_TEX_1D:
719 // Base 1D case
720 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->width) + 1);
721 break;
722 default:
723 ADDR_ASSERT_ALWAYS();
724 break;
725 }
726 // Client pass wrong number of MipLevels to addrlib and result will be bad.
727 // Not sure if we should fail this calling instead of putting an assertion here.
728 ADDR_ASSERT(actualMipLevels >= pIn->numMipLevels);
729 }
730 #endif
731 }
732
733 ADDR_E_RETURNCODE ApplyCustomerPipeBankXor(
734 AddrSwizzleMode swizzleMode,
735 UINT_32 pipeBankXor,
736 UINT_32 bankBits,
737 UINT_32 pipeBits,
738 UINT_32* pBlockOffset) const
739 {
740 ADDR_E_RETURNCODE returnCode = ADDR_OK;
741
742 if (IsXor(swizzleMode))
743 {
744 // Apply driver set bankPipeXor
745 UINT_32 bankX = 0;
746 UINT_32 pipeX = 0;
747 returnCode = ExtractPipeBankXor(pipeBankXor, bankBits, pipeBits, &bankX, &pipeX);
748 *pBlockOffset ^= (pipeX << m_pipeInterleaveLog2);
749 *pBlockOffset ^= (bankX << (m_pipeInterleaveLog2 + pipeBits));
750 }
751
752 return returnCode;
753 }
754
755 UINT_32 GetPipeXorBits(UINT_32 macroBlockBits) const;
756 UINT_32 GetBankXorBits(UINT_32 macroBlockBits) const;
757
758 ADDR_E_RETURNCODE ApplyCustomizedPitchHeight(
759 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
760 UINT_32 elementBytes,
761 UINT_32 pitchAlignInElement,
762 UINT_32* pPitch,
763 UINT_32* pHeight) const;
764
765 VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
766
767 UINT_32 m_se; ///< Number of shader engine
768 UINT_32 m_rbPerSe; ///< Number of render backend per shader engine
769 UINT_32 m_maxCompFrag; ///< Number of max compressed fragment
770
771 UINT_32 m_banksLog2; ///< Number of bank Log2
772 UINT_32 m_pipesLog2; ///< Number of pipe per shader engine Log2
773 UINT_32 m_seLog2; ///< Number of shader engine Log2
774 UINT_32 m_rbPerSeLog2; ///< Number of render backend per shader engine Log2
775 UINT_32 m_maxCompFragLog2; ///< Number of max compressed fragment Log2
776
777 UINT_32 m_pipeInterleaveLog2; ///< Log2 of pipe interleave bytes
778
779 UINT_32 m_blockVarSizeLog2; ///< Log2 of block var size
780
781 SwizzleModeFlags m_swizzleModeTable[ADDR_SW_MAX_TYPE]; ///< Swizzle mode table
782
783 private:
784 // Disallow the copy constructor
785 Lib(const Lib& a);
786
787 // Disallow the assignment operator
788 Lib& operator=(const Lib& a);
789 };
790
791 } // V2
792 } // Addr
793
794 #endif
795