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amd: update addrlib
[mesa.git] / src / amd / addrlib / inc / addrinterface.h
1 /*
2 * Copyright © 2007-2019 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 /**
28 ****************************************************************************************************
29 * @file addrinterface.h
30 * @brief Contains the addrlib interfaces declaration and parameter defines
31 ****************************************************************************************************
32 */
33 #ifndef __ADDR_INTERFACE_H__
34 #define __ADDR_INTERFACE_H__
35
36 #include "addrtypes.h"
37
38 #if defined(__cplusplus)
39 extern "C"
40 {
41 #endif
42
43 #define ADDRLIB_VERSION_MAJOR 6
44 #define ADDRLIB_VERSION_MINOR 2
45 #define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR)
46
47 /// Virtually all interface functions need ADDR_HANDLE as first parameter
48 typedef VOID* ADDR_HANDLE;
49
50 /// Client handle used in callbacks
51 typedef VOID* ADDR_CLIENT_HANDLE;
52
53 /**
54 * /////////////////////////////////////////////////////////////////////////////////////////////////
55 * // Callback functions
56 * /////////////////////////////////////////////////////////////////////////////////////////////////
57 * typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
58 * const ADDR_ALLOCSYSMEM_INPUT* pInput);
59 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
60 * VOID* pVirtAddr);
61 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
62 * const ADDR_DEBUGPRINT_INPUT* pInput);
63 *
64 * /////////////////////////////////////////////////////////////////////////////////////////////////
65 * // Create/Destroy/Config functions
66 * /////////////////////////////////////////////////////////////////////////////////////////////////
67 * AddrCreate()
68 * AddrDestroy()
69 *
70 * /////////////////////////////////////////////////////////////////////////////////////////////////
71 * // Surface functions
72 * /////////////////////////////////////////////////////////////////////////////////////////////////
73 * AddrComputeSurfaceInfo()
74 * AddrComputeSurfaceAddrFromCoord()
75 * AddrComputeSurfaceCoordFromAddr()
76 *
77 * /////////////////////////////////////////////////////////////////////////////////////////////////
78 * // HTile functions
79 * /////////////////////////////////////////////////////////////////////////////////////////////////
80 * AddrComputeHtileInfo()
81 * AddrComputeHtileAddrFromCoord()
82 * AddrComputeHtileCoordFromAddr()
83 *
84 * /////////////////////////////////////////////////////////////////////////////////////////////////
85 * // C-mask functions
86 * /////////////////////////////////////////////////////////////////////////////////////////////////
87 * AddrComputeCmaskInfo()
88 * AddrComputeCmaskAddrFromCoord()
89 * AddrComputeCmaskCoordFromAddr()
90 *
91 * /////////////////////////////////////////////////////////////////////////////////////////////////
92 * // F-mask functions
93 * /////////////////////////////////////////////////////////////////////////////////////////////////
94 * AddrComputeFmaskInfo()
95 * AddrComputeFmaskAddrFromCoord()
96 * AddrComputeFmaskCoordFromAddr()
97 *
98 * /////////////////////////////////////////////////////////////////////////////////////////////////
99 * // Element/Utility functions
100 * /////////////////////////////////////////////////////////////////////////////////////////////////
101 * ElemFlt32ToDepthPixel()
102 * ElemFlt32ToColorPixel()
103 * AddrExtractBankPipeSwizzle()
104 * AddrCombineBankPipeSwizzle()
105 * AddrComputeSliceSwizzle()
106 * AddrConvertTileInfoToHW()
107 * AddrConvertTileIndex()
108 * AddrConvertTileIndex1()
109 * AddrGetTileIndex()
110 * AddrComputeBaseSwizzle()
111 * AddrUseTileIndex()
112 * AddrUseCombinedSwizzle()
113 *
114 **/
115
116 ////////////////////////////////////////////////////////////////////////////////////////////////////
117 // Callback functions
118 ////////////////////////////////////////////////////////////////////////////////////////////////////
119
120 /**
121 ****************************************************************************************************
122 * @brief channel setting structure
123 ****************************************************************************************************
124 */
125 typedef union _ADDR_CHANNEL_SETTING
126 {
127 struct
128 {
129 UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid
130 UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel
131 UINT_8 index : 5; ///< Channel index
132 };
133 UINT_8 value; ///< Value
134 } ADDR_CHANNEL_SETTING;
135
136 /**
137 ****************************************************************************************************
138 * @brief address equation key structure
139 ****************************************************************************************************
140 */
141 typedef union _ADDR_EQUATION_KEY
142 {
143 struct
144 {
145 UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel
146 UINT_32 tileMode : 5; ///< Tile mode
147 UINT_32 microTileType : 3; ///< Micro tile type
148 UINT_32 pipeConfig : 5; ///< pipe config
149 UINT_32 numBanksLog2 : 3; ///< Number of banks log2
150 UINT_32 bankWidth : 4; ///< Bank width
151 UINT_32 bankHeight : 4; ///< Bank height
152 UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio
153 UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt
154 UINT_32 reserved : 1; ///< Reserved bit
155 } fields;
156 UINT_32 value;
157 } ADDR_EQUATION_KEY;
158
159 /**
160 ****************************************************************************************************
161 * @brief address equation structure
162 ****************************************************************************************************
163 */
164 #define ADDR_MAX_EQUATION_BIT 20u
165
166 // Invalid equation index
167 #define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF
168
169 typedef struct _ADDR_EQUATION
170 {
171 ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting
172 ///< each bit is result of addr ^ xor ^ xor2
173 ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting
174 ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting
175 UINT_32 numBits; ///< The number of bits in equation
176 BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being
177 ///< stacked vertically prior to swizzling
178 } ADDR_EQUATION;
179
180 /**
181 ****************************************************************************************************
182 * @brief Alloc system memory flags.
183 * @note These flags are reserved for future use and if flags are added will minimize the impact
184 * of the client.
185 ****************************************************************************************************
186 */
187 typedef union _ADDR_ALLOCSYSMEM_FLAGS
188 {
189 struct
190 {
191 UINT_32 reserved : 32; ///< Reserved for future use.
192 } fields;
193 UINT_32 value;
194
195 } ADDR_ALLOCSYSMEM_FLAGS;
196
197 /**
198 ****************************************************************************************************
199 * @brief Alloc system memory input structure
200 ****************************************************************************************************
201 */
202 typedef struct _ADDR_ALLOCSYSMEM_INPUT
203 {
204 UINT_32 size; ///< Size of this structure in bytes
205
206 ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags.
207 UINT_32 sizeInBytes; ///< System memory allocation size in bytes.
208 ADDR_CLIENT_HANDLE hClient; ///< Client handle
209 } ADDR_ALLOCSYSMEM_INPUT;
210
211 /**
212 ****************************************************************************************************
213 * ADDR_ALLOCSYSMEM
214 * @brief
215 * Allocate system memory callback function. Returns valid pointer on success.
216 ****************************************************************************************************
217 */
218 typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)(
219 const ADDR_ALLOCSYSMEM_INPUT* pInput);
220
221 /**
222 ****************************************************************************************************
223 * @brief Free system memory input structure
224 ****************************************************************************************************
225 */
226 typedef struct _ADDR_FREESYSMEM_INPUT
227 {
228 UINT_32 size; ///< Size of this structure in bytes
229
230 VOID* pVirtAddr; ///< Virtual address
231 ADDR_CLIENT_HANDLE hClient; ///< Client handle
232 } ADDR_FREESYSMEM_INPUT;
233
234 /**
235 ****************************************************************************************************
236 * ADDR_FREESYSMEM
237 * @brief
238 * Free system memory callback function.
239 * Returns ADDR_OK on success.
240 ****************************************************************************************************
241 */
242 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)(
243 const ADDR_FREESYSMEM_INPUT* pInput);
244
245 /**
246 ****************************************************************************************************
247 * @brief Print debug message input structure
248 ****************************************************************************************************
249 */
250 typedef struct _ADDR_DEBUGPRINT_INPUT
251 {
252 UINT_32 size; ///< Size of this structure in bytes
253
254 CHAR* pDebugString; ///< Debug print string
255 va_list ap; ///< Variable argument list
256 ADDR_CLIENT_HANDLE hClient; ///< Client handle
257 } ADDR_DEBUGPRINT_INPUT;
258
259 /**
260 ****************************************************************************************************
261 * ADDR_DEBUGPRINT
262 * @brief
263 * Print debug message callback function.
264 * Returns ADDR_OK on success.
265 ****************************************************************************************************
266 */
267 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)(
268 const ADDR_DEBUGPRINT_INPUT* pInput);
269
270 /**
271 ****************************************************************************************************
272 * ADDR_CALLBACKS
273 *
274 * @brief
275 * Address Library needs client to provide system memory alloc/free routines.
276 ****************************************************************************************************
277 */
278 typedef struct _ADDR_CALLBACKS
279 {
280 ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory
281 ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory
282 ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message
283 } ADDR_CALLBACKS;
284
285 ////////////////////////////////////////////////////////////////////////////////////////////////////
286 // Create/Destroy functions
287 ////////////////////////////////////////////////////////////////////////////////////////////////////
288
289 /**
290 ****************************************************************************************************
291 * ADDR_CREATE_FLAGS
292 *
293 * @brief
294 * This structure is used to pass some setup in creation of AddrLib
295 * @note
296 ****************************************************************************************************
297 */
298 typedef union _ADDR_CREATE_FLAGS
299 {
300 struct
301 {
302 UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off
303 UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and
304 /// output structure
305 UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid
306 UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle
307 UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level
308 UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment
309 UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize
310 UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility
311 UINT_32 reserved : 24; ///< Reserved bits for future use
312 };
313
314 UINT_32 value;
315 } ADDR_CREATE_FLAGS;
316
317 /**
318 ****************************************************************************************************
319 * ADDR_REGISTER_VALUE
320 *
321 * @brief
322 * Data from registers to setup AddrLib global data, used in AddrCreate
323 ****************************************************************************************************
324 */
325 typedef struct _ADDR_REGISTER_VALUE
326 {
327 UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value.
328 /// For R6xx/R7xx, use GB_TILING_CONFIG.
329 /// But they can be treated as the same.
330 /// if this value is 0, use chip to set default value
331 UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled.
332 /// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE
333
334 /// R800 registers-----------------------------------------------
335 UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK
336 /// No enums for this value in h/w header files
337 /// 0: 4
338 /// 1: 8
339 /// 2: 16
340 UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK
341 /// 0: 1
342 /// 1: 2
343 /// SI (R1000) registers-----------------------------------------
344 const UINT_32* pTileConfig; ///< Global tile setting tables
345 UINT_32 noOfEntries; ///< Number of entries in pTileConfig
346
347 ///< CI registers-------------------------------------------------
348 const UINT_32* pMacroTileConfig; ///< Global macro tile mode table
349 UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig
350
351 ///< GFX9 HW parameters
352 UINT_32 blockVarSizeLog2; ///< SW_VAR_* block size
353 } ADDR_REGISTER_VALUE;
354
355 /**
356 ****************************************************************************************************
357 * ADDR_CREATE_INPUT
358 *
359 * @brief
360 * Parameters use to create an AddrLib Object. Caller must provide all fields.
361 *
362 ****************************************************************************************************
363 */
364 typedef struct _ADDR_CREATE_INPUT
365 {
366 UINT_32 size; ///< Size of this structure in bytes
367
368 UINT_32 chipEngine; ///< Chip Engine
369 UINT_32 chipFamily; ///< Chip Family
370 UINT_32 chipRevision; ///< Chip Revision
371 ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print
372 ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib
373 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data
374 ADDR_CLIENT_HANDLE hClient; ///< Client handle
375 UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels
376 } ADDR_CREATE_INPUT;
377
378 /**
379 ****************************************************************************************************
380 * ADDR_CREATEINFO_OUTPUT
381 *
382 * @brief
383 * Return AddrLib handle to client driver
384 *
385 ****************************************************************************************************
386 */
387 typedef struct _ADDR_CREATE_OUTPUT
388 {
389 UINT_32 size; ///< Size of this structure in bytes
390
391 ADDR_HANDLE hLib; ///< Address lib handle
392
393 UINT_32 numEquations; ///< Number of equations in the table
394 const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table
395 } ADDR_CREATE_OUTPUT;
396
397 /**
398 ****************************************************************************************************
399 * AddrCreate
400 *
401 * @brief
402 * Create AddrLib object, must be called before any interface calls
403 *
404 * @return
405 * ADDR_OK if successful
406 ****************************************************************************************************
407 */
408 ADDR_E_RETURNCODE ADDR_API AddrCreate(
409 const ADDR_CREATE_INPUT* pAddrCreateIn,
410 ADDR_CREATE_OUTPUT* pAddrCreateOut);
411
412 /**
413 ****************************************************************************************************
414 * AddrDestroy
415 *
416 * @brief
417 * Destroy AddrLib object, must be called to free internally allocated resources.
418 *
419 * @return
420 * ADDR_OK if successful
421 ****************************************************************************************************
422 */
423 ADDR_E_RETURNCODE ADDR_API AddrDestroy(
424 ADDR_HANDLE hLib);
425
426 ////////////////////////////////////////////////////////////////////////////////////////////////////
427 // Surface functions
428 ////////////////////////////////////////////////////////////////////////////////////////////////////
429
430 /**
431 ****************************************************************************************************
432 * @brief
433 * Bank/tiling parameters. On function input, these can be set as desired or
434 * left 0 for AddrLib to calculate/default. On function output, these are the actual
435 * parameters used.
436 * @note
437 * Valid bankWidth/bankHeight value:
438 * 1,2,4,8. They are factors instead of pixels or bytes.
439 *
440 * The bank number remains constant across each row of the
441 * macro tile as each pipe is selected, so the number of
442 * tiles in the x direction with the same bank number will
443 * be bank_width * num_pipes.
444 ****************************************************************************************************
445 */
446 typedef struct _ADDR_TILEINFO
447 {
448 /// Any of these parameters can be set to 0 to use the HW default.
449 UINT_32 banks; ///< Number of banks, numerical value
450 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank
451 UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank
452 UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1
453 UINT_32 tileSplitBytes; ///< Tile split size, in bytes
454 AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1
455 } ADDR_TILEINFO;
456
457 // Create a define to avoid client change. The removal of R800 is because we plan to implement SI
458 // within 800 HWL - An AddrPipeCfg is added in above data structure
459 typedef ADDR_TILEINFO ADDR_R800_TILEINFO;
460
461 /**
462 ****************************************************************************************************
463 * @brief
464 * Information needed by quad buffer stereo support
465 ****************************************************************************************************
466 */
467 typedef struct _ADDR_QBSTEREOINFO
468 {
469 UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye
470 UINT_32 rightOffset; ///< Offset (in bytes) to right eye
471 UINT_32 rightSwizzle; ///< TileSwizzle for right eyes
472 } ADDR_QBSTEREOINFO;
473
474 /**
475 ****************************************************************************************************
476 * ADDR_SURFACE_FLAGS
477 *
478 * @brief
479 * Surface flags
480 ****************************************************************************************************
481 */
482 typedef union _ADDR_SURFACE_FLAGS
483 {
484 struct
485 {
486 UINT_32 color : 1; ///< Flag indicates this is a color buffer
487 UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer
488 UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer
489 UINT_32 texture : 1; ///< Flag indicates this is a texture
490 UINT_32 cube : 1; ///< Flag indicates this is a cubemap
491 UINT_32 volume : 1; ///< Flag indicates this is a volume texture
492 UINT_32 fmask : 1; ///< Flag indicates this is an fmask
493 UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays
494 UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed
495 UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface
496 UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil
497 UINT_32 display : 1; ///< Flag indicates this should match display controller req.
498 UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space
499 /// i.e. save some memory but may lose performance
500 UINT_32 prt : 1; ///< Flag for partially resident texture
501 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface
502 UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0)
503 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
504 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
505 UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce
506 UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear
507 UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that
508 /// dcc can't be enabled if pipe config of tile mode
509 /// is different from that of ASIC, this flag
510 /// is address lib internal flag, client should ignore it
511 UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment.
512 /// This flag indicates we need to follow the
513 /// alignment with CZ families or other ASICs under
514 /// PX configuration + CZ.
515 UINT_32 nonSplit : 1; ///< CI: depth texture should not be split
516 UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear
517 UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible.
518 /// This flag indicates we need to override tile
519 /// mode to PRT_* tile mode to disable slice rotation,
520 /// which is needed by swizzle pattern equation.
521 UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output.
522 UINT_32 rotateDisplay : 1; ///< Rotate micro tile type
523 UINT_32 minimizeAlignment : 1; ///< Minimize alignment
524 UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode
525 UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface
526 /// to make sure they share same tile config parameters
527 UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade
528 UINT_32 reserved : 1; ///< Reserved bits
529 };
530
531 UINT_32 value;
532 } ADDR_SURFACE_FLAGS;
533
534 /**
535 ****************************************************************************************************
536 * ADDR_COMPUTE_SURFACE_INFO_INPUT
537 *
538 * @brief
539 * Input structure for AddrComputeSurfaceInfo
540 ****************************************************************************************************
541 */
542 typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT
543 {
544 UINT_32 size; ///< Size of this structure in bytes
545
546 AddrTileMode tileMode; ///< Tile mode
547 AddrFormat format; ///< If format is set to valid one, bpp/width/height
548 /// might be overwritten
549 UINT_32 bpp; ///< Bits per pixel
550 UINT_32 numSamples; ///< Number of samples
551 UINT_32 width; ///< Width, in pixels
552 UINT_32 height; ///< Height, in pixels
553 UINT_32 numSlices; ///< Number of surface slices or depth
554 UINT_32 slice; ///< Slice index
555 UINT_32 mipLevel; ///< Current mipmap level
556 UINT_32 numMipLevels; ///< Number of mips in mip chain
557 ADDR_SURFACE_FLAGS flags; ///< Surface type flags
558 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
559 /// number of samples for normal AA; Set it to the
560 /// number of fragments for EQAA
561 /// r800 and later HWL parameters
562 // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's
563 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate
564 AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1
565 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
566 /// while the global useTileIndex is set to 1
567 UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a
568 /// must for mip levels from SI+.
569 /// Don't use pitch in blocks for compressed formats!
570 UINT_32 maxBaseAlign; ///< Max base alignment request from client
571 UINT_32 pitchAlign; ///< Pitch alignment request from client
572 UINT_32 heightAlign; ///< Height alignment request from client
573 } ADDR_COMPUTE_SURFACE_INFO_INPUT;
574
575 /**
576 ****************************************************************************************************
577 * ADDR_COMPUTE_SURFACE_INFO_OUTPUT
578 *
579 * @brief
580 * Output structure for AddrComputeSurfInfo
581 * @note
582 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
583 Pixel: Original pixel
584 ****************************************************************************************************
585 */
586 typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT
587 {
588 UINT_32 size; ///< Size of this structure in bytes
589
590 UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats)
591 UINT_32 height; ///< Height in elements (in blocks for compressed formats)
592 UINT_32 depth; ///< Number of slice/depth
593 UINT_64 surfSize; ///< Surface size in bytes
594 AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input
595 UINT_32 baseAlign; ///< Base address alignment
596 UINT_32 pitchAlign; ///< Pitch alignment, in elements
597 UINT_32 heightAlign; ///< Height alignment, in elements
598 UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture
599 UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit)
600 UINT_32 pixelPitch; ///< Pitch in original pixels
601 UINT_32 pixelHeight; ///< Height in original pixels
602 UINT_32 pixelBits; ///< Original bits per pixel, passed from input
603 UINT_64 sliceSize; ///< Size of slice specified by input's slice
604 /// The result is controlled by surface flags & createFlags
605 /// By default this value equals to surfSize for volume
606 UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register
607 UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register
608 UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register
609
610 UINT_32 numSamples; ///< Pass the effective numSamples processed in this call
611
612 /// r800 and later HWL parameters
613 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input
614 AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1
615 INT_32 tileIndex; ///< Tile index, MAY be "downgraded"
616
617 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
618 /// Output flags
619 struct
620 {
621 /// Special information to work around SI mipmap swizzle bug UBTS #317508
622 UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled
623 ///< Only meaningful when create flag checkLast2DLevel is set
624 UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible
625 UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering
626 UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT
627 ///< If address lib return true for mip 0, client should set prt flag
628 ///< for child mips in subsequent compute surface info calls
629 UINT_32 reserved :28; ///< Reserved bits
630 };
631
632 UINT_32 equationIndex; ///< Equation index in the equation table;
633
634 UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro)
635 UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro)
636 UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro)
637
638 /// Stereo info
639 ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE
640
641 INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set
642 } ADDR_COMPUTE_SURFACE_INFO_OUTPUT;
643
644 /**
645 ****************************************************************************************************
646 * AddrComputeSurfaceInfo
647 *
648 * @brief
649 * Compute surface width/height/depth/alignments and suitable tiling mode
650 ****************************************************************************************************
651 */
652 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo(
653 ADDR_HANDLE hLib,
654 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
655 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
656
657 /**
658 ****************************************************************************************************
659 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
660 *
661 * @brief
662 * Input structure for AddrComputeSurfaceAddrFromCoord
663 ****************************************************************************************************
664 */
665 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
666 {
667 UINT_32 size; ///< Size of this structure in bytes
668
669 UINT_32 x; ///< X coordinate
670 UINT_32 y; ///< Y coordinate
671 UINT_32 slice; ///< Slice index
672 UINT_32 sample; ///< Sample index, use fragment index for EQAA
673
674 UINT_32 bpp; ///< Bits per pixel
675 UINT_32 pitch; ///< Surface pitch, in pixels
676 UINT_32 height; ///< Surface height, in pixels
677 UINT_32 numSlices; ///< Surface depth
678 UINT_32 numSamples; ///< Number of samples
679
680 AddrTileMode tileMode; ///< Tile mode
681 BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within
682 /// micro tile. Textures can also choose depth sample order
683 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles
684 /// the case that components are stored separately
685 UINT_32 compBits; ///< The component bits actually needed(for planar surface)
686
687 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
688 /// number of samples for normal AA; Set it to the
689 /// number of fragments for EQAA
690 /// r800 and later HWL parameters
691 // Used for 1D tiling above
692 AddrTileType tileType; ///< See defintion of AddrTileType
693 struct
694 {
695 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture
696 /// only flag. Only non-RT texture can set this to TRUE
697 UINT_32 reserved :31; ///< Reserved for future use.
698 };
699 // 2D tiling needs following structure
700 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
701 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
702 /// while the global useTileIndex is set to 1
703 union
704 {
705 struct
706 {
707 UINT_32 bankSwizzle; ///< Bank swizzle
708 UINT_32 pipeSwizzle; ///< Pipe swizzle
709 };
710 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
711 };
712 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
713
714 /**
715 ****************************************************************************************************
716 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
717 *
718 * @brief
719 * Output structure for AddrComputeSurfaceAddrFromCoord
720 ****************************************************************************************************
721 */
722 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
723 {
724 UINT_32 size; ///< Size of this structure in bytes
725
726 UINT_64 addr; ///< Byte address
727 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7.
728 /// For surface bpp < 8, e.g. FMT_1.
729 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block)
730 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
731
732 /**
733 ****************************************************************************************************
734 * AddrComputeSurfaceAddrFromCoord
735 *
736 * @brief
737 * Compute surface address from a given coordinate.
738 ****************************************************************************************************
739 */
740 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord(
741 ADDR_HANDLE hLib,
742 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
743 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
744
745 /**
746 ****************************************************************************************************
747 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
748 *
749 * @brief
750 * Input structure for AddrComputeSurfaceCoordFromAddr
751 ****************************************************************************************************
752 */
753 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT
754 {
755 UINT_32 size; ///< Size of this structure in bytes
756
757 UINT_64 addr; ///< Address in bytes
758 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8,
759 /// e.g. FMT_1;
760 UINT_32 bpp; ///< Bits per pixel
761 UINT_32 pitch; ///< Pitch, in pixels
762 UINT_32 height; ///< Height in pixels
763 UINT_32 numSlices; ///< Surface depth
764 UINT_32 numSamples; ///< Number of samples
765
766 AddrTileMode tileMode; ///< Tile mode
767 BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile.
768 /// Note: Textures can choose depth sample order as well.
769 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles
770 /// the case that components are stored separately
771 UINT_32 compBits; ///< The component bits actually needed(for planar surface)
772
773 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
774 /// number of samples for normal AA; Set it to the
775 /// number of fragments for EQAA
776 /// r800 and later HWL parameters
777 // Used for 1D tiling above
778 AddrTileType tileType; ///< See defintion of AddrTileType
779 struct
780 {
781 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture
782 /// only flag. Only non-RT texture can set this to TRUE
783 UINT_32 reserved :31; ///< Reserved for future use.
784 };
785 // 2D tiling needs following structure
786 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
787 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
788 /// while the global useTileIndex is set to 1
789 union
790 {
791 struct
792 {
793 UINT_32 bankSwizzle; ///< Bank swizzle
794 UINT_32 pipeSwizzle; ///< Pipe swizzle
795 };
796 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
797 };
798 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
799
800 /**
801 ****************************************************************************************************
802 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
803 *
804 * @brief
805 * Output structure for AddrComputeSurfaceCoordFromAddr
806 ****************************************************************************************************
807 */
808 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
809 {
810 UINT_32 size; ///< Size of this structure in bytes
811
812 UINT_32 x; ///< X coordinate
813 UINT_32 y; ///< Y coordinate
814 UINT_32 slice; ///< Index of slices
815 UINT_32 sample; ///< Index of samples, means fragment index for EQAA
816 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
817
818 /**
819 ****************************************************************************************************
820 * AddrComputeSurfaceCoordFromAddr
821 *
822 * @brief
823 * Compute coordinate from a given surface address
824 ****************************************************************************************************
825 */
826 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr(
827 ADDR_HANDLE hLib,
828 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
829 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);
830
831 ////////////////////////////////////////////////////////////////////////////////////////////////////
832 // HTile functions
833 ////////////////////////////////////////////////////////////////////////////////////////////////////
834
835 /**
836 ****************************************************************************************************
837 * ADDR_HTILE_FLAGS
838 *
839 * @brief
840 * HTILE flags
841 ****************************************************************************************************
842 */
843 typedef union _ADDR_HTILE_FLAGS
844 {
845 struct
846 {
847 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
848 UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile
849 /// size to 256xBankxPipe when computing tc-compatible
850 /// htile info.
851 UINT_32 reserved : 30; ///< Reserved bits
852 };
853
854 UINT_32 value;
855 } ADDR_HTILE_FLAGS;
856
857 /**
858 ****************************************************************************************************
859 * ADDR_COMPUTE_HTILE_INFO_INPUT
860 *
861 * @brief
862 * Input structure of AddrComputeHtileInfo
863 ****************************************************************************************************
864 */
865 typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT
866 {
867 UINT_32 size; ///< Size of this structure in bytes
868
869 ADDR_HTILE_FLAGS flags; ///< HTILE flags
870 UINT_32 pitch; ///< Surface pitch, in pixels
871 UINT_32 height; ///< Surface height, in pixels
872 UINT_32 numSlices; ///< Number of slices
873 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
874 AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8
875 AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8
876 ADDR_TILEINFO* pTileInfo; ///< Tile info
877
878 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
879 /// while the global useTileIndex is set to 1
880 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
881 ///< README: When tileIndex is not -1, this must be valid
882 } ADDR_COMPUTE_HTILE_INFO_INPUT;
883
884 /**
885 ****************************************************************************************************
886 * ADDR_COMPUTE_HTILE_INFO_OUTPUT
887 *
888 * @brief
889 * Output structure of AddrComputeHtileInfo
890 ****************************************************************************************************
891 */
892 typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT
893 {
894 UINT_32 size; ///< Size of this structure in bytes
895
896 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this
897 /// HTile buffer. This might be larger than original depth
898 /// buffer pitch when called with an unaligned pitch.
899 UINT_32 height; ///< Height in pixels, as above
900 UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes
901 UINT_32 baseAlign; ///< Base alignment
902 UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block!
903 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape
904 UINT_32 macroHeight; ///< Macro height in pixels
905 UINT_64 sliceSize; ///< Slice size, in bytes.
906 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved
907 /// Compute engine clear can't be used if htile is interleaved
908 BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in
909 /// next mip level, it also indicates if memory set based
910 /// fast clear can be used for current mip level.
911 } ADDR_COMPUTE_HTILE_INFO_OUTPUT;
912
913 /**
914 ****************************************************************************************************
915 * AddrComputeHtileInfo
916 *
917 * @brief
918 * Compute Htile pitch, height, base alignment and size in bytes
919 ****************************************************************************************************
920 */
921 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo(
922 ADDR_HANDLE hLib,
923 const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn,
924 ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut);
925
926 /**
927 ****************************************************************************************************
928 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
929 *
930 * @brief
931 * Input structure for AddrComputeHtileAddrFromCoord
932 ****************************************************************************************************
933 */
934 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
935 {
936 UINT_32 size; ///< Size of this structure in bytes
937
938 UINT_32 pitch; ///< Pitch, in pixels
939 UINT_32 height; ///< Height in pixels
940 UINT_32 x; ///< X coordinate
941 UINT_32 y; ///< Y coordinate
942 UINT_32 slice; ///< Index of slice
943 UINT_32 numSlices; ///< Number of slices
944 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
945 ADDR_HTILE_FLAGS flags; ///< htile flags
946 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
947 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8
948 ADDR_TILEINFO* pTileInfo; ///< Tile info
949
950 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
951 /// while the global useTileIndex is set to 1
952 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
953 ///< README: When tileIndex is not -1, this must be valid
954 UINT_32 bpp; ///< depth/stencil buffer bit per pixel size
955 UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address
956 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
957
958 /**
959 ****************************************************************************************************
960 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
961 *
962 * @brief
963 * Output structure for AddrComputeHtileAddrFromCoord
964 ****************************************************************************************************
965 */
966 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
967 {
968 UINT_32 size; ///< Size of this structure in bytes
969
970 UINT_64 addr; ///< Address in bytes
971 UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method.
972 /// So we keep bitPosition for HTILE as well
973 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
974
975 /**
976 ****************************************************************************************************
977 * AddrComputeHtileAddrFromCoord
978 *
979 * @brief
980 * Compute Htile address according to coordinates (of depth buffer)
981 ****************************************************************************************************
982 */
983 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord(
984 ADDR_HANDLE hLib,
985 const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
986 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
987
988 /**
989 ****************************************************************************************************
990 * ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
991 *
992 * @brief
993 * Input structure for AddrComputeHtileCoordFromAddr
994 ****************************************************************************************************
995 */
996 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT
997 {
998 UINT_32 size; ///< Size of this structure in bytes
999
1000 UINT_64 addr; ///< Address
1001 UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods
1002 /// so we keep bitPosition for HTILE as well
1003 UINT_32 pitch; ///< Pitch, in pixels
1004 UINT_32 height; ///< Height, in pixels
1005 UINT_32 numSlices; ///< Number of slices
1006 BOOL_32 isLinear; ///< Linear or tiled HTILE layout
1007 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
1008 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8
1009 ADDR_TILEINFO* pTileInfo; ///< Tile info
1010
1011 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1012 /// while the global useTileIndex is set to 1
1013 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1014 ///< README: When tileIndex is not -1, this must be valid
1015 } ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT;
1016
1017 /**
1018 ****************************************************************************************************
1019 * ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
1020 *
1021 * @brief
1022 * Output structure for AddrComputeHtileCoordFromAddr
1023 ****************************************************************************************************
1024 */
1025 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
1026 {
1027 UINT_32 size; ///< Size of this structure in bytes
1028
1029 UINT_32 x; ///< X coordinate
1030 UINT_32 y; ///< Y coordinate
1031 UINT_32 slice; ///< Slice index
1032 } ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
1033
1034 /**
1035 ****************************************************************************************************
1036 * AddrComputeHtileCoordFromAddr
1037 *
1038 * @brief
1039 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to
1040 * Htile address
1041 ****************************************************************************************************
1042 */
1043 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr(
1044 ADDR_HANDLE hLib,
1045 const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
1046 ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
1047
1048 ////////////////////////////////////////////////////////////////////////////////////////////////////
1049 // C-mask functions
1050 ////////////////////////////////////////////////////////////////////////////////////////////////////
1051
1052 /**
1053 ****************************************************************************************************
1054 * ADDR_CMASK_FLAGS
1055 *
1056 * @brief
1057 * CMASK flags
1058 ****************************************************************************************************
1059 */
1060 typedef union _ADDR_CMASK_FLAGS
1061 {
1062 struct
1063 {
1064 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable
1065 UINT_32 reserved :31; ///< Reserved bits
1066 };
1067
1068 UINT_32 value;
1069 } ADDR_CMASK_FLAGS;
1070
1071 /**
1072 ****************************************************************************************************
1073 * ADDR_COMPUTE_CMASK_INFO_INPUT
1074 *
1075 * @brief
1076 * Input structure of AddrComputeCmaskInfo
1077 ****************************************************************************************************
1078 */
1079 typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT
1080 {
1081 UINT_32 size; ///< Size of this structure in bytes
1082
1083 ADDR_CMASK_FLAGS flags; ///< CMASK flags
1084 UINT_32 pitch; ///< Pitch, in pixels, of color buffer
1085 UINT_32 height; ///< Height, in pixels, of color buffer
1086 UINT_32 numSlices; ///< Number of slices, of color buffer
1087 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1088 ADDR_TILEINFO* pTileInfo; ///< Tile info
1089
1090 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1091 /// while the global useTileIndex is set to 1
1092 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1093 ///< README: When tileIndex is not -1, this must be valid
1094 } ADDR_COMPUTE_CMASK_INFO_INPUT;
1095
1096 /**
1097 ****************************************************************************************************
1098 * ADDR_COMPUTE_CMASK_INFO_OUTPUT
1099 *
1100 * @brief
1101 * Output structure of AddrComputeCmaskInfo
1102 ****************************************************************************************************
1103 */
1104 typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT
1105 {
1106 UINT_32 size; ///< Size of this structure in bytes
1107
1108 UINT_32 pitch; ///< Pitch in pixels of color buffer which
1109 /// this Cmask matches. The size might be larger than
1110 /// original color buffer pitch when called with
1111 /// an unaligned pitch.
1112 UINT_32 height; ///< Height in pixels, as above
1113 UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer
1114 UINT_32 baseAlign; ///< Base alignment
1115 UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register
1116 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape
1117 UINT_32 macroHeight; ///< Macro height in pixels
1118 UINT_64 sliceSize; ///< Slice size, in bytes.
1119 } ADDR_COMPUTE_CMASK_INFO_OUTPUT;
1120
1121 /**
1122 ****************************************************************************************************
1123 * AddrComputeCmaskInfo
1124 *
1125 * @brief
1126 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer
1127 * info
1128 ****************************************************************************************************
1129 */
1130 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo(
1131 ADDR_HANDLE hLib,
1132 const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn,
1133 ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut);
1134
1135 /**
1136 ****************************************************************************************************
1137 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
1138 *
1139 * @brief
1140 * Input structure for AddrComputeCmaskAddrFromCoord
1141 *
1142 ****************************************************************************************************
1143 */
1144 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
1145 {
1146 UINT_32 size; ///< Size of this structure in bytes
1147 UINT_32 x; ///< X coordinate
1148 UINT_32 y; ///< Y coordinate
1149 UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask
1150 UINT_32 slice; ///< Slice index
1151 UINT_32 pitch; ///< Pitch in pixels, of color buffer
1152 UINT_32 height; ///< Height in pixels, of color buffer
1153 UINT_32 numSlices; ///< Number of slices
1154 UINT_32 bpp;
1155 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1156 ADDR_CMASK_FLAGS flags; ///< CMASK flags
1157 ADDR_TILEINFO* pTileInfo; ///< Tile info
1158
1159 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1160 ///< while the global useTileIndex is set to 1
1161 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1162 ///< README: When tileIndex is not -1, this must be valid
1163 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
1164
1165 /**
1166 ****************************************************************************************************
1167 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
1168 *
1169 * @brief
1170 * Output structure for AddrComputeCmaskAddrFromCoord
1171 ****************************************************************************************************
1172 */
1173 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
1174 {
1175 UINT_32 size; ///< Size of this structure in bytes
1176
1177 UINT_64 addr; ///< CMASK address in bytes
1178 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp,
1179 /// so the address may be located in bit 0 (0) or 4 (4)
1180 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
1181
1182 /**
1183 ****************************************************************************************************
1184 * AddrComputeCmaskAddrFromCoord
1185 *
1186 * @brief
1187 * Compute Cmask address according to coordinates (of MSAA color buffer)
1188 ****************************************************************************************************
1189 */
1190 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord(
1191 ADDR_HANDLE hLib,
1192 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
1193 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
1194
1195 /**
1196 ****************************************************************************************************
1197 * ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
1198 *
1199 * @brief
1200 * Input structure for AddrComputeCmaskCoordFromAddr
1201 ****************************************************************************************************
1202 */
1203 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT
1204 {
1205 UINT_32 size; ///< Size of this structure in bytes
1206
1207 UINT_64 addr; ///< CMASK address in bytes
1208 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp,
1209 /// so the address may be located in bit 0 (0) or 4 (4)
1210 UINT_32 pitch; ///< Pitch, in pixels
1211 UINT_32 height; ///< Height in pixels
1212 UINT_32 numSlices; ///< Number of slices
1213 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear
1214 ADDR_TILEINFO* pTileInfo; ///< Tile info
1215
1216 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1217 /// while the global useTileIndex is set to 1
1218 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1219 ///< README: When tileIndex is not -1, this must be valid
1220 } ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT;
1221
1222 /**
1223 ****************************************************************************************************
1224 * ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
1225 *
1226 * @brief
1227 * Output structure for AddrComputeCmaskCoordFromAddr
1228 ****************************************************************************************************
1229 */
1230 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
1231 {
1232 UINT_32 size; ///< Size of this structure in bytes
1233
1234 UINT_32 x; ///< X coordinate
1235 UINT_32 y; ///< Y coordinate
1236 UINT_32 slice; ///< Slice index
1237 } ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
1238
1239 /**
1240 ****************************************************************************************************
1241 * AddrComputeCmaskCoordFromAddr
1242 *
1243 * @brief
1244 * Compute coordinates within color buffer (1st pixel of a micro tile) according to
1245 * Cmask address
1246 ****************************************************************************************************
1247 */
1248 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr(
1249 ADDR_HANDLE hLib,
1250 const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
1251 ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
1252
1253 ////////////////////////////////////////////////////////////////////////////////////////////////////
1254 // F-mask functions
1255 ////////////////////////////////////////////////////////////////////////////////////////////////////
1256
1257 /**
1258 ****************************************************************************************************
1259 * ADDR_COMPUTE_FMASK_INFO_INPUT
1260 *
1261 * @brief
1262 * Input structure for AddrComputeFmaskInfo
1263 ****************************************************************************************************
1264 */
1265 typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT
1266 {
1267 UINT_32 size; ///< Size of this structure in bytes
1268
1269 AddrTileMode tileMode; ///< Tile mode
1270 UINT_32 pitch; ///< Surface pitch, in pixels
1271 UINT_32 height; ///< Surface height, in pixels
1272 UINT_32 numSlices; ///< Number of slice/depth
1273 UINT_32 numSamples; ///< Number of samples
1274 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
1275 /// number of samples for normal AA; Set it to the
1276 /// number of fragments for EQAA
1277 /// r800 and later HWL parameters
1278 struct
1279 {
1280 UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used
1281 /// by H/W clients. S/W should always set it to FALSE.
1282 UINT_32 reserved: 31; ///< Reserved for future use.
1283 };
1284 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data
1285 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1286 /// while the global useTileIndex is set to 1
1287 } ADDR_COMPUTE_FMASK_INFO_INPUT;
1288
1289 /**
1290 ****************************************************************************************************
1291 * ADDR_COMPUTE_FMASK_INFO_OUTPUT
1292 *
1293 * @brief
1294 * Output structure for AddrComputeFmaskInfo
1295 ****************************************************************************************************
1296 */
1297 typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT
1298 {
1299 UINT_32 size; ///< Size of this structure in bytes
1300
1301 UINT_32 pitch; ///< Pitch of fmask in pixels
1302 UINT_32 height; ///< Height of fmask in pixels
1303 UINT_32 numSlices; ///< Slices of fmask
1304 UINT_64 fmaskBytes; ///< Size of fmask in bytes
1305 UINT_32 baseAlign; ///< Base address alignment
1306 UINT_32 pitchAlign; ///< Pitch alignment
1307 UINT_32 heightAlign; ///< Height alignment
1308 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes
1309 UINT_32 numSamples; ///< Number of samples, used for dump, export this since input
1310 /// may be changed in 9xx and above
1311 /// r800 and later HWL parameters
1312 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different
1313 /// bank_height from color buffer
1314 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1315 /// while the global useTileIndex is set to 1
1316 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1317 UINT_64 sliceSize; ///< Size of slice in bytes
1318 } ADDR_COMPUTE_FMASK_INFO_OUTPUT;
1319
1320 /**
1321 ****************************************************************************************************
1322 * AddrComputeFmaskInfo
1323 *
1324 * @brief
1325 * Compute Fmask pitch/height/depth/alignments and size in bytes
1326 ****************************************************************************************************
1327 */
1328 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo(
1329 ADDR_HANDLE hLib,
1330 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
1331 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut);
1332
1333 /**
1334 ****************************************************************************************************
1335 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
1336 *
1337 * @brief
1338 * Input structure for AddrComputeFmaskAddrFromCoord
1339 ****************************************************************************************************
1340 */
1341 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
1342 {
1343 UINT_32 size; ///< Size of this structure in bytes
1344
1345 UINT_32 x; ///< X coordinate
1346 UINT_32 y; ///< Y coordinate
1347 UINT_32 slice; ///< Slice index
1348 UINT_32 plane; ///< Plane number
1349 UINT_32 sample; ///< Sample index (fragment index for EQAA)
1350
1351 UINT_32 pitch; ///< Surface pitch, in pixels
1352 UINT_32 height; ///< Surface height, in pixels
1353 UINT_32 numSamples; ///< Number of samples
1354 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
1355 /// number of samples for normal AA; Set it to the
1356 /// number of fragments for EQAA
1357
1358 AddrTileMode tileMode; ///< Tile mode
1359 union
1360 {
1361 struct
1362 {
1363 UINT_32 bankSwizzle; ///< Bank swizzle
1364 UINT_32 pipeSwizzle; ///< Pipe swizzle
1365 };
1366 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
1367 };
1368
1369 /// r800 and later HWL parameters
1370 struct
1371 {
1372 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients
1373 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored.
1374 UINT_32 reserved: 30; ///< Reserved for future use.
1375 };
1376 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data
1377
1378 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
1379
1380 /**
1381 ****************************************************************************************************
1382 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
1383 *
1384 * @brief
1385 * Output structure for AddrComputeFmaskAddrFromCoord
1386 ****************************************************************************************************
1387 */
1388 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
1389 {
1390 UINT_32 size; ///< Size of this structure in bytes
1391
1392 UINT_64 addr; ///< Fmask address
1393 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7.
1394 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
1395
1396 /**
1397 ****************************************************************************************************
1398 * AddrComputeFmaskAddrFromCoord
1399 *
1400 * @brief
1401 * Compute Fmask address according to coordinates (x,y,slice,sample,plane)
1402 ****************************************************************************************************
1403 */
1404 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord(
1405 ADDR_HANDLE hLib,
1406 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
1407 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
1408
1409 /**
1410 ****************************************************************************************************
1411 * ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
1412 *
1413 * @brief
1414 * Input structure for AddrComputeFmaskCoordFromAddr
1415 ****************************************************************************************************
1416 */
1417 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT
1418 {
1419 UINT_32 size; ///< Size of this structure in bytes
1420
1421 UINT_64 addr; ///< Address
1422 UINT_32 bitPosition; ///< Bit position within addr, 0-7.
1423
1424 UINT_32 pitch; ///< Pitch, in pixels
1425 UINT_32 height; ///< Height in pixels
1426 UINT_32 numSamples; ///< Number of samples
1427 UINT_32 numFrags; ///< Number of fragments
1428 AddrTileMode tileMode; ///< Tile mode
1429 union
1430 {
1431 struct
1432 {
1433 UINT_32 bankSwizzle; ///< Bank swizzle
1434 UINT_32 pipeSwizzle; ///< Pipe swizzle
1435 };
1436 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE
1437 };
1438
1439 /// r800 and later HWL parameters
1440 struct
1441 {
1442 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components
1443 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored.
1444 UINT_32 reserved: 30; ///< Reserved for future use.
1445 };
1446 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1447
1448 } ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT;
1449
1450 /**
1451 ****************************************************************************************************
1452 * ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
1453 *
1454 * @brief
1455 * Output structure for AddrComputeFmaskCoordFromAddr
1456 ****************************************************************************************************
1457 */
1458 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
1459 {
1460 UINT_32 size; ///< Size of this structure in bytes
1461
1462 UINT_32 x; ///< X coordinate
1463 UINT_32 y; ///< Y coordinate
1464 UINT_32 slice; ///< Slice index
1465 UINT_32 plane; ///< Plane number
1466 UINT_32 sample; ///< Sample index (fragment index for EQAA)
1467 } ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
1468
1469 /**
1470 ****************************************************************************************************
1471 * AddrComputeFmaskCoordFromAddr
1472 *
1473 * @brief
1474 * Compute FMASK coordinate from an given address
1475 ****************************************************************************************************
1476 */
1477 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr(
1478 ADDR_HANDLE hLib,
1479 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
1480 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
1481
1482 ////////////////////////////////////////////////////////////////////////////////////////////////////
1483 // Element/utility functions
1484 ////////////////////////////////////////////////////////////////////////////////////////////////////
1485
1486 /**
1487 ****************************************************************************************************
1488 * AddrGetVersion
1489 *
1490 * @brief
1491 * Get AddrLib version number
1492 ****************************************************************************************************
1493 */
1494 UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib);
1495
1496 /**
1497 ****************************************************************************************************
1498 * AddrUseTileIndex
1499 *
1500 * @brief
1501 * Return TRUE if tileIndex is enabled in this address library
1502 ****************************************************************************************************
1503 */
1504 BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib);
1505
1506 /**
1507 ****************************************************************************************************
1508 * AddrUseCombinedSwizzle
1509 *
1510 * @brief
1511 * Return TRUE if combined swizzle is enabled in this address library
1512 ****************************************************************************************************
1513 */
1514 BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib);
1515
1516 /**
1517 ****************************************************************************************************
1518 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
1519 *
1520 * @brief
1521 * Input structure of AddrExtractBankPipeSwizzle
1522 ****************************************************************************************************
1523 */
1524 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT
1525 {
1526 UINT_32 size; ///< Size of this structure in bytes
1527
1528 UINT_32 base256b; ///< Base256b value
1529
1530 /// r800 and later HWL parameters
1531 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1532
1533 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1534 /// while the global useTileIndex is set to 1
1535 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1536 ///< README: When tileIndex is not -1, this must be valid
1537 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT;
1538
1539 /**
1540 ****************************************************************************************************
1541 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
1542 *
1543 * @brief
1544 * Output structure of AddrExtractBankPipeSwizzle
1545 ****************************************************************************************************
1546 */
1547 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT
1548 {
1549 UINT_32 size; ///< Size of this structure in bytes
1550
1551 UINT_32 bankSwizzle; ///< Bank swizzle
1552 UINT_32 pipeSwizzle; ///< Pipe swizzle
1553 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT;
1554
1555 /**
1556 ****************************************************************************************************
1557 * AddrExtractBankPipeSwizzle
1558 *
1559 * @brief
1560 * Extract Bank and Pipe swizzle from base256b
1561 * @return
1562 * ADDR_OK if no error
1563 ****************************************************************************************************
1564 */
1565 ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle(
1566 ADDR_HANDLE hLib,
1567 const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn,
1568 ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut);
1569
1570 /**
1571 ****************************************************************************************************
1572 * ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
1573 *
1574 * @brief
1575 * Input structure of AddrCombineBankPipeSwizzle
1576 ****************************************************************************************************
1577 */
1578 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT
1579 {
1580 UINT_32 size; ///< Size of this structure in bytes
1581
1582 UINT_32 bankSwizzle; ///< Bank swizzle
1583 UINT_32 pipeSwizzle; ///< Pipe swizzle
1584 UINT_64 baseAddr; ///< Base address (leave it zero for driver clients)
1585
1586 /// r800 and later HWL parameters
1587 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data
1588
1589 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1590 /// while the global useTileIndex is set to 1
1591 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1592 ///< README: When tileIndex is not -1, this must be valid
1593 } ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT;
1594
1595 /**
1596 ****************************************************************************************************
1597 * ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
1598 *
1599 * @brief
1600 * Output structure of AddrCombineBankPipeSwizzle
1601 ****************************************************************************************************
1602 */
1603 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT
1604 {
1605 UINT_32 size; ///< Size of this structure in bytes
1606
1607 UINT_32 tileSwizzle; ///< Combined swizzle
1608 } ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT;
1609
1610 /**
1611 ****************************************************************************************************
1612 * AddrCombineBankPipeSwizzle
1613 *
1614 * @brief
1615 * Combine Bank and Pipe swizzle
1616 * @return
1617 * ADDR_OK if no error
1618 * @note
1619 * baseAddr here is full MCAddress instead of base256b
1620 ****************************************************************************************************
1621 */
1622 ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle(
1623 ADDR_HANDLE hLib,
1624 const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn,
1625 ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut);
1626
1627 /**
1628 ****************************************************************************************************
1629 * ADDR_COMPUTE_SLICESWIZZLE_INPUT
1630 *
1631 * @brief
1632 * Input structure of AddrComputeSliceSwizzle
1633 ****************************************************************************************************
1634 */
1635 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT
1636 {
1637 UINT_32 size; ///< Size of this structure in bytes
1638
1639 AddrTileMode tileMode; ///< Tile Mode
1640 UINT_32 baseSwizzle; ///< Base tile swizzle
1641 UINT_32 slice; ///< Slice index
1642 UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases
1643
1644 /// r800 and later HWL parameters
1645 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!
1646
1647 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1648 /// while the global useTileIndex is set to 1
1649 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1650 ///< README: When tileIndex is not -1, this must be valid
1651 } ADDR_COMPUTE_SLICESWIZZLE_INPUT;
1652
1653 /**
1654 ****************************************************************************************************
1655 * ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
1656 *
1657 * @brief
1658 * Output structure of AddrComputeSliceSwizzle
1659 ****************************************************************************************************
1660 */
1661 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT
1662 {
1663 UINT_32 size; ///< Size of this structure in bytes
1664
1665 UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value
1666 } ADDR_COMPUTE_SLICESWIZZLE_OUTPUT;
1667
1668 /**
1669 ****************************************************************************************************
1670 * AddrComputeSliceSwizzle
1671 *
1672 * @brief
1673 * Extract Bank and Pipe swizzle from base256b
1674 * @return
1675 * ADDR_OK if no error
1676 ****************************************************************************************************
1677 */
1678 ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle(
1679 ADDR_HANDLE hLib,
1680 const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn,
1681 ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut);
1682
1683 /**
1684 ****************************************************************************************************
1685 * AddrSwizzleGenOption
1686 *
1687 * @brief
1688 * Which swizzle generating options: legacy or linear
1689 ****************************************************************************************************
1690 */
1691 typedef enum _AddrSwizzleGenOption
1692 {
1693 ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle
1694 ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle
1695 } AddrSwizzleGenOption;
1696
1697 /**
1698 ****************************************************************************************************
1699 * AddrSwizzleOption
1700 *
1701 * @brief
1702 * Controls how swizzle is generated
1703 ****************************************************************************************************
1704 */
1705 typedef union _ADDR_SWIZZLE_OPTION
1706 {
1707 struct
1708 {
1709 UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption
1710 UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits
1711 UINT_32 reserved :30; ///< Reserved bits
1712 };
1713
1714 UINT_32 value;
1715
1716 } ADDR_SWIZZLE_OPTION;
1717
1718 /**
1719 ****************************************************************************************************
1720 * ADDR_COMPUTE_BASE_SWIZZLE_INPUT
1721 *
1722 * @brief
1723 * Input structure of AddrComputeBaseSwizzle
1724 ****************************************************************************************************
1725 */
1726 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT
1727 {
1728 UINT_32 size; ///< Size of this structure in bytes
1729
1730 ADDR_SWIZZLE_OPTION option; ///< Swizzle option
1731 UINT_32 surfIndex; ///< Index of this surface type
1732 AddrTileMode tileMode; ///< Tile Mode
1733
1734 /// r800 and later HWL parameters
1735 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here!
1736
1737 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1738 /// while the global useTileIndex is set to 1
1739 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1740 ///< README: When tileIndex is not -1, this must be valid
1741 } ADDR_COMPUTE_BASE_SWIZZLE_INPUT;
1742
1743 /**
1744 ****************************************************************************************************
1745 * ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
1746 *
1747 * @brief
1748 * Output structure of AddrComputeBaseSwizzle
1749 ****************************************************************************************************
1750 */
1751 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT
1752 {
1753 UINT_32 size; ///< Size of this structure in bytes
1754
1755 UINT_32 tileSwizzle; ///< Combined swizzle
1756 } ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT;
1757
1758 /**
1759 ****************************************************************************************************
1760 * AddrComputeBaseSwizzle
1761 *
1762 * @brief
1763 * Return a Combined Bank and Pipe swizzle base on surface based on surface type/index
1764 * @return
1765 * ADDR_OK if no error
1766 ****************************************************************************************************
1767 */
1768 ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle(
1769 ADDR_HANDLE hLib,
1770 const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn,
1771 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut);
1772
1773 /**
1774 ****************************************************************************************************
1775 * ELEM_GETEXPORTNORM_INPUT
1776 *
1777 * @brief
1778 * Input structure for ElemGetExportNorm
1779 *
1780 ****************************************************************************************************
1781 */
1782 typedef struct _ELEM_GETEXPORTNORM_INPUT
1783 {
1784 UINT_32 size; ///< Size of this structure in bytes
1785
1786 AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat
1787 AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType
1788 AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap
1789 UINT_32 numSamples; ///< Number of samples
1790 } ELEM_GETEXPORTNORM_INPUT;
1791
1792 /**
1793 ****************************************************************************************************
1794 * ElemGetExportNorm
1795 *
1796 * @brief
1797 * Helper function to check one format can be EXPORT_NUM, which is a register
1798 * CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600
1799 * family
1800 * @note
1801 * The implementation is only for r600.
1802 * 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two
1803 * clocks per export)
1804 * 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one
1805 * clock per export)
1806 *
1807 ****************************************************************************************************
1808 */
1809 BOOL_32 ADDR_API ElemGetExportNorm(
1810 ADDR_HANDLE hLib,
1811 const ELEM_GETEXPORTNORM_INPUT* pIn);
1812
1813 /**
1814 ****************************************************************************************************
1815 * ELEM_FLT32TODEPTHPIXEL_INPUT
1816 *
1817 * @brief
1818 * Input structure for addrFlt32ToDepthPixel
1819 *
1820 ****************************************************************************************************
1821 */
1822 typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT
1823 {
1824 UINT_32 size; ///< Size of this structure in bytes
1825
1826 AddrDepthFormat format; ///< Depth buffer format
1827 ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil)
1828 } ELEM_FLT32TODEPTHPIXEL_INPUT;
1829
1830 /**
1831 ****************************************************************************************************
1832 * ELEM_FLT32TODEPTHPIXEL_INPUT
1833 *
1834 * @brief
1835 * Output structure for ElemFlt32ToDepthPixel
1836 *
1837 ****************************************************************************************************
1838 */
1839 typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT
1840 {
1841 UINT_32 size; ///< Size of this structure in bytes
1842
1843 UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer.
1844 /// Client must provide enough storage for this type.
1845 UINT_32 depthBase; ///< Tile base in bits for depth bits
1846 UINT_32 stencilBase; ///< Tile base in bits for stencil bits
1847 UINT_32 depthBits; ///< Bits for depth
1848 UINT_32 stencilBits; ///< Bits for stencil
1849 } ELEM_FLT32TODEPTHPIXEL_OUTPUT;
1850
1851 /**
1852 ****************************************************************************************************
1853 * ElemFlt32ToDepthPixel
1854 *
1855 * @brief
1856 * Convert a FLT_32 value to a depth/stencil pixel value
1857 *
1858 * @return
1859 * Return code
1860 *
1861 ****************************************************************************************************
1862 */
1863 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel(
1864 ADDR_HANDLE hLib,
1865 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn,
1866 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut);
1867
1868 /**
1869 ****************************************************************************************************
1870 * ELEM_FLT32TOCOLORPIXEL_INPUT
1871 *
1872 * @brief
1873 * Input structure for addrFlt32ToColorPixel
1874 *
1875 ****************************************************************************************************
1876 */
1877 typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT
1878 {
1879 UINT_32 size; ///< Size of this structure in bytes
1880
1881 AddrColorFormat format; ///< Color buffer format
1882 AddrSurfaceNumber surfNum; ///< Surface number
1883 AddrSurfaceSwap surfSwap; ///< Surface swap
1884 ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a)
1885 } ELEM_FLT32TOCOLORPIXEL_INPUT;
1886
1887 /**
1888 ****************************************************************************************************
1889 * ELEM_FLT32TOCOLORPIXEL_INPUT
1890 *
1891 * @brief
1892 * Output structure for ElemFlt32ToColorPixel
1893 *
1894 ****************************************************************************************************
1895 */
1896 typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT
1897 {
1898 UINT_32 size; ///< Size of this structure in bytes
1899
1900 UINT_8* pPixel; ///< Real color value. Same data type as color buffer.
1901 /// Client must provide enough storage for this type.
1902 } ELEM_FLT32TOCOLORPIXEL_OUTPUT;
1903
1904 /**
1905 ****************************************************************************************************
1906 * ElemFlt32ToColorPixel
1907 *
1908 * @brief
1909 * Convert a FLT_32 value to a red/green/blue/alpha pixel value
1910 *
1911 * @return
1912 * Return code
1913 *
1914 ****************************************************************************************************
1915 */
1916 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel(
1917 ADDR_HANDLE hLib,
1918 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn,
1919 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut);
1920
1921 /**
1922 ****************************************************************************************************
1923 * ElemSize
1924 *
1925 * @brief
1926 * Get bits-per-element for specified format
1927 *
1928 * @return
1929 * Bits-per-element of specified format
1930 *
1931 ****************************************************************************************************
1932 */
1933 UINT_32 ADDR_API ElemSize(
1934 ADDR_HANDLE hLib,
1935 AddrFormat format);
1936
1937 /**
1938 ****************************************************************************************************
1939 * ADDR_CONVERT_TILEINFOTOHW_INPUT
1940 *
1941 * @brief
1942 * Input structure for AddrConvertTileInfoToHW
1943 * @note
1944 * When reverse is TRUE, indices are igonred
1945 ****************************************************************************************************
1946 */
1947 typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT
1948 {
1949 UINT_32 size; ///< Size of this structure in bytes
1950 BOOL_32 reverse; ///< Convert control flag.
1951 /// FALSE: convert from real value to HW value;
1952 /// TRUE: convert from HW value to real value.
1953
1954 /// r800 and later HWL parameters
1955 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value
1956
1957 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it
1958 /// while the global useTileIndex is set to 1
1959 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
1960 ///< README: When tileIndex is not -1, this must be valid
1961 UINT_32 bpp; ///< Bits per pixel
1962 } ADDR_CONVERT_TILEINFOTOHW_INPUT;
1963
1964 /**
1965 ****************************************************************************************************
1966 * ADDR_CONVERT_TILEINFOTOHW_OUTPUT
1967 *
1968 * @brief
1969 * Output structure for AddrConvertTileInfoToHW
1970 ****************************************************************************************************
1971 */
1972 typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT
1973 {
1974 UINT_32 size; ///< Size of this structure in bytes
1975
1976 /// r800 and later HWL parameters
1977 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value
1978
1979 } ADDR_CONVERT_TILEINFOTOHW_OUTPUT;
1980
1981 /**
1982 ****************************************************************************************************
1983 * AddrConvertTileInfoToHW
1984 *
1985 * @brief
1986 * Convert tile info from real value to hardware register value
1987 ****************************************************************************************************
1988 */
1989 ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW(
1990 ADDR_HANDLE hLib,
1991 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn,
1992 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut);
1993
1994 /**
1995 ****************************************************************************************************
1996 * ADDR_CONVERT_TILEINDEX_INPUT
1997 *
1998 * @brief
1999 * Input structure for AddrConvertTileIndex
2000 ****************************************************************************************************
2001 */
2002 typedef struct _ADDR_CONVERT_TILEINDEX_INPUT
2003 {
2004 UINT_32 size; ///< Size of this structure in bytes
2005
2006 INT_32 tileIndex; ///< Tile index
2007 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2008 UINT_32 bpp; ///< Bits per pixel
2009 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual
2010 } ADDR_CONVERT_TILEINDEX_INPUT;
2011
2012 /**
2013 ****************************************************************************************************
2014 * ADDR_CONVERT_TILEINDEX_OUTPUT
2015 *
2016 * @brief
2017 * Output structure for AddrConvertTileIndex
2018 ****************************************************************************************************
2019 */
2020 typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT
2021 {
2022 UINT_32 size; ///< Size of this structure in bytes
2023
2024 AddrTileMode tileMode; ///< Tile mode
2025 AddrTileType tileType; ///< Tile type
2026 ADDR_TILEINFO* pTileInfo; ///< Tile info
2027
2028 } ADDR_CONVERT_TILEINDEX_OUTPUT;
2029
2030 /**
2031 ****************************************************************************************************
2032 * AddrConvertTileIndex
2033 *
2034 * @brief
2035 * Convert tile index to tile mode/type/info
2036 ****************************************************************************************************
2037 */
2038 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex(
2039 ADDR_HANDLE hLib,
2040 const ADDR_CONVERT_TILEINDEX_INPUT* pIn,
2041 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);
2042
2043 /**
2044 ****************************************************************************************************
2045 * ADDR_GET_MACROMODEINDEX_INPUT
2046 *
2047 * @brief
2048 * Input structure for AddrGetMacroModeIndex
2049 ****************************************************************************************************
2050 */
2051 typedef struct _ADDR_GET_MACROMODEINDEX_INPUT
2052 {
2053 UINT_32 size; ///< Size of this structure in bytes
2054 ADDR_SURFACE_FLAGS flags; ///< Surface flag
2055 INT_32 tileIndex; ///< Tile index
2056 UINT_32 bpp; ///< Bits per pixel
2057 UINT_32 numFrags; ///< Number of color fragments
2058 } ADDR_GET_MACROMODEINDEX_INPUT;
2059
2060 /**
2061 ****************************************************************************************************
2062 * ADDR_GET_MACROMODEINDEX_OUTPUT
2063 *
2064 * @brief
2065 * Output structure for AddrGetMacroModeIndex
2066 ****************************************************************************************************
2067 */
2068 typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT
2069 {
2070 UINT_32 size; ///< Size of this structure in bytes
2071 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2072 } ADDR_GET_MACROMODEINDEX_OUTPUT;
2073
2074 /**
2075 ****************************************************************************************************
2076 * AddrGetMacroModeIndex
2077 *
2078 * @brief
2079 * Get macro mode index based on input parameters
2080 ****************************************************************************************************
2081 */
2082 ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex(
2083 ADDR_HANDLE hLib,
2084 const ADDR_GET_MACROMODEINDEX_INPUT* pIn,
2085 ADDR_GET_MACROMODEINDEX_OUTPUT* pOut);
2086
2087 /**
2088 ****************************************************************************************************
2089 * ADDR_CONVERT_TILEINDEX1_INPUT
2090 *
2091 * @brief
2092 * Input structure for AddrConvertTileIndex1 (without macro mode index)
2093 ****************************************************************************************************
2094 */
2095 typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT
2096 {
2097 UINT_32 size; ///< Size of this structure in bytes
2098
2099 INT_32 tileIndex; ///< Tile index
2100 UINT_32 bpp; ///< Bits per pixel
2101 UINT_32 numSamples; ///< Number of samples
2102 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual
2103 } ADDR_CONVERT_TILEINDEX1_INPUT;
2104
2105 /**
2106 ****************************************************************************************************
2107 * AddrConvertTileIndex1
2108 *
2109 * @brief
2110 * Convert tile index to tile mode/type/info
2111 ****************************************************************************************************
2112 */
2113 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1(
2114 ADDR_HANDLE hLib,
2115 const ADDR_CONVERT_TILEINDEX1_INPUT* pIn,
2116 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut);
2117
2118 /**
2119 ****************************************************************************************************
2120 * ADDR_GET_TILEINDEX_INPUT
2121 *
2122 * @brief
2123 * Input structure for AddrGetTileIndex
2124 ****************************************************************************************************
2125 */
2126 typedef struct _ADDR_GET_TILEINDEX_INPUT
2127 {
2128 UINT_32 size; ///< Size of this structure in bytes
2129
2130 AddrTileMode tileMode; ///< Tile mode
2131 AddrTileType tileType; ///< Tile-type: disp/non-disp/...
2132 ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D
2133 } ADDR_GET_TILEINDEX_INPUT;
2134
2135 /**
2136 ****************************************************************************************************
2137 * ADDR_GET_TILEINDEX_OUTPUT
2138 *
2139 * @brief
2140 * Output structure for AddrGetTileIndex
2141 ****************************************************************************************************
2142 */
2143 typedef struct _ADDR_GET_TILEINDEX_OUTPUT
2144 {
2145 UINT_32 size; ///< Size of this structure in bytes
2146
2147 INT_32 index; ///< index in table
2148 } ADDR_GET_TILEINDEX_OUTPUT;
2149
2150 /**
2151 ****************************************************************************************************
2152 * AddrGetTileIndex
2153 *
2154 * @brief
2155 * Get the tiling mode index in table
2156 ****************************************************************************************************
2157 */
2158 ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex(
2159 ADDR_HANDLE hLib,
2160 const ADDR_GET_TILEINDEX_INPUT* pIn,
2161 ADDR_GET_TILEINDEX_OUTPUT* pOut);
2162
2163 /**
2164 ****************************************************************************************************
2165 * ADDR_PRT_INFO_INPUT
2166 *
2167 * @brief
2168 * Input structure for AddrComputePrtInfo
2169 ****************************************************************************************************
2170 */
2171 typedef struct _ADDR_PRT_INFO_INPUT
2172 {
2173 AddrFormat format; ///< Surface format
2174 UINT_32 baseMipWidth; ///< Base mipmap width
2175 UINT_32 baseMipHeight; ///< Base mipmap height
2176 UINT_32 baseMipDepth; ///< Base mipmap depth
2177 UINT_32 numFrags; ///< Number of fragments,
2178 } ADDR_PRT_INFO_INPUT;
2179
2180 /**
2181 ****************************************************************************************************
2182 * ADDR_PRT_INFO_OUTPUT
2183 *
2184 * @brief
2185 * Input structure for AddrComputePrtInfo
2186 ****************************************************************************************************
2187 */
2188 typedef struct _ADDR_PRT_INFO_OUTPUT
2189 {
2190 UINT_32 prtTileWidth;
2191 UINT_32 prtTileHeight;
2192 } ADDR_PRT_INFO_OUTPUT;
2193
2194 /**
2195 ****************************************************************************************************
2196 * AddrComputePrtInfo
2197 *
2198 * @brief
2199 * Compute prt surface related information
2200 ****************************************************************************************************
2201 */
2202 ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo(
2203 ADDR_HANDLE hLib,
2204 const ADDR_PRT_INFO_INPUT* pIn,
2205 ADDR_PRT_INFO_OUTPUT* pOut);
2206
2207 ////////////////////////////////////////////////////////////////////////////////////////////////////
2208 // DCC key functions
2209 ////////////////////////////////////////////////////////////////////////////////////////////////////
2210
2211 /**
2212 ****************************************************************************************************
2213 * _ADDR_COMPUTE_DCCINFO_INPUT
2214 *
2215 * @brief
2216 * Input structure of AddrComputeDccInfo
2217 ****************************************************************************************************
2218 */
2219 typedef struct _ADDR_COMPUTE_DCCINFO_INPUT
2220 {
2221 UINT_32 size; ///< Size of this structure in bytes
2222 UINT_32 bpp; ///< BitPP of color surface
2223 UINT_32 numSamples; ///< Sample number of color surface
2224 UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound
2225 AddrTileMode tileMode; ///< Tile mode of color surface
2226 ADDR_TILEINFO tileInfo; ///< Tile info of color surface
2227 UINT_32 tileSwizzle; ///< Tile swizzle
2228 INT_32 tileIndex; ///< Tile index of color surface,
2229 ///< MUST be -1 if you don't want to use it
2230 ///< while the global useTileIndex is set to 1
2231 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI)
2232 ///< README: When tileIndex is not -1, this must be valid
2233 } ADDR_COMPUTE_DCCINFO_INPUT;
2234
2235 /**
2236 ****************************************************************************************************
2237 * ADDR_COMPUTE_DCCINFO_OUTPUT
2238 *
2239 * @brief
2240 * Output structure of AddrComputeDccInfo
2241 ****************************************************************************************************
2242 */
2243 typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
2244 {
2245 UINT_32 size; ///< Size of this structure in bytes
2246 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key
2247 UINT_64 dccRamSize; ///< Size of dcc key
2248 UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared
2249 BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable
2250 BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned
2251 } ADDR_COMPUTE_DCCINFO_OUTPUT;
2252
2253 /**
2254 ****************************************************************************************************
2255 * AddrComputeDccInfo
2256 *
2257 * @brief
2258 * Compute DCC key size, base alignment
2259 * info
2260 ****************************************************************************************************
2261 */
2262 ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo(
2263 ADDR_HANDLE hLib,
2264 const ADDR_COMPUTE_DCCINFO_INPUT* pIn,
2265 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut);
2266
2267 /**
2268 ****************************************************************************************************
2269 * ADDR_GET_MAX_ALINGMENTS_OUTPUT
2270 *
2271 * @brief
2272 * Output structure of AddrGetMaxAlignments
2273 ****************************************************************************************************
2274 */
2275 typedef struct _ADDR_GET_MAX_ALINGMENTS_OUTPUT
2276 {
2277 UINT_32 size; ///< Size of this structure in bytes
2278 UINT_32 baseAlign; ///< Maximum base alignment in bytes
2279 } ADDR_GET_MAX_ALINGMENTS_OUTPUT;
2280
2281 /**
2282 ****************************************************************************************************
2283 * AddrGetMaxAlignments
2284 *
2285 * @brief
2286 * Gets maximnum alignments
2287 ****************************************************************************************************
2288 */
2289 ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments(
2290 ADDR_HANDLE hLib,
2291 ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
2292
2293 /**
2294 ****************************************************************************************************
2295 * AddrGetMaxMetaAlignments
2296 *
2297 * @brief
2298 * Gets maximnum alignments for metadata
2299 ****************************************************************************************************
2300 */
2301 ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments(
2302 ADDR_HANDLE hLib,
2303 ADDR_GET_MAX_ALINGMENTS_OUTPUT* pOut);
2304
2305 /**
2306 ****************************************************************************************************
2307 * Address library interface version 2
2308 * available from Gfx9 hardware
2309 ****************************************************************************************************
2310 * Addr2ComputeSurfaceInfo()
2311 * Addr2ComputeSurfaceAddrFromCoord()
2312 * Addr2ComputeSurfaceCoordFromAddr()
2313
2314 * Addr2ComputeHtileInfo()
2315 * Addr2ComputeHtileAddrFromCoord()
2316 * Addr2ComputeHtileCoordFromAddr()
2317 *
2318 * Addr2ComputeCmaskInfo()
2319 * Addr2ComputeCmaskAddrFromCoord()
2320 * Addr2ComputeCmaskCoordFromAddr()
2321 *
2322 * Addr2ComputeFmaskInfo()
2323 * Addr2ComputeFmaskAddrFromCoord()
2324 * Addr2ComputeFmaskCoordFromAddr()
2325 *
2326 * Addr2ComputeDccInfo()
2327 *
2328 **/
2329
2330 ////////////////////////////////////////////////////////////////////////////////////////////////////
2331 // Surface functions for Gfx9
2332 ////////////////////////////////////////////////////////////////////////////////////////////////////
2333
2334 /**
2335 ****************************************************************************************************
2336 * ADDR2_SURFACE_FLAGS
2337 *
2338 * @brief
2339 * Surface flags
2340 ****************************************************************************************************
2341 */
2342 typedef union _ADDR2_SURFACE_FLAGS
2343 {
2344 struct
2345 {
2346 UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV
2347 UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV
2348 UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV
2349 UINT_32 fmask : 1; ///< This is an fmask surface
2350 UINT_32 overlay : 1; ///< This is an overlay surface
2351 UINT_32 display : 1; ///< This resource is displable, can be used with DRV
2352 UINT_32 prt : 1; ///< This is a partially resident texture
2353 UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface
2354 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding
2355 UINT_32 texture : 1; ///< This resource can be used with SRV
2356 UINT_32 unordered : 1; ///< This resource can be used with UAV
2357 UINT_32 rotated : 1; ///< This resource is rotated and displable
2358 UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible
2359 UINT_32 opt4space : 1; ///< This resource should be optimized for space
2360 UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment
2361 UINT_32 noMetadata : 1; ///< This resource has no metadata
2362 UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata
2363 UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata
2364 UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array
2365 UINT_32 reserved : 13; ///< Reserved bits
2366 };
2367
2368 UINT_32 value;
2369 } ADDR2_SURFACE_FLAGS;
2370
2371 /**
2372 ****************************************************************************************************
2373 * ADDR2_COMPUTE_SURFACE_INFO_INPUT
2374 *
2375 * @brief
2376 * Input structure for Addr2ComputeSurfaceInfo
2377 ****************************************************************************************************
2378 */
2379 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT
2380 {
2381 UINT_32 size; ///< Size of this structure in bytes
2382
2383 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2384 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9
2385 AddrResourceType resourceType; ///< Surface type
2386 AddrFormat format; ///< Surface format
2387 UINT_32 bpp; ///< bits per pixel
2388 UINT_32 width; ///< Width (of mip0), in pixels
2389 UINT_32 height; ///< Height (of mip0), in pixels
2390 UINT_32 numSlices; ///< Number surface slice/depth (of mip0),
2391 UINT_32 numMipLevels; ///< Total mipmap levels.
2392 UINT_32 numSamples; ///< Number of samples
2393 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2394 /// number of samples for normal AA; Set it to the
2395 /// number of fragments for EQAA
2396 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2397 UINT_32 sliceAlign; ///< Required slice size in bytes
2398 } ADDR2_COMPUTE_SURFACE_INFO_INPUT;
2399
2400 /**
2401 ****************************************************************************************************
2402 * ADDR2_MIP_INFO
2403 *
2404 * @brief
2405 * Structure that contains information for mip level
2406 *
2407 ****************************************************************************************************
2408 */
2409 typedef struct _ADDR2_MIP_INFO
2410 {
2411 UINT_32 pitch; ///< Pitch in elements
2412 UINT_32 height; ///< Padded height in elements
2413 UINT_32 depth; ///< Padded depth
2414 UINT_32 pixelPitch; ///< Pitch in pixels
2415 UINT_32 pixelHeight; ///< Padded height in pixels
2416 UINT_32 equationIndex; ///< Equation index in the equation table
2417 UINT_64 offset; ///< Offset in bytes from mip base, should only be used
2418 ///< to setup vam surface descriptor, can't be used
2419 ///< to setup swizzle pattern
2420 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base
2421 UINT_32 mipTailOffset; ///< mip tail offset in bytes
2422 UINT_32 mipTailCoordX; ///< mip tail coord x
2423 UINT_32 mipTailCoordY; ///< mip tail coord y
2424 UINT_32 mipTailCoordZ; ///< mip tail coord z
2425 } ADDR2_MIP_INFO;
2426
2427 /**
2428 ****************************************************************************************************
2429 * ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2430 *
2431 * @brief
2432 * Output structure for Addr2ComputeSurfInfo
2433 * @note
2434 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch
2435 Pixel: Original pixel
2436 ****************************************************************************************************
2437 */
2438 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2439 {
2440 UINT_32 size; ///< Size of this structure in bytes
2441
2442 UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats)
2443 UINT_32 height; ///< Padded height (of mip0) in elements
2444 UINT_32 numSlices; ///< Padded depth for 3d resource
2445 ///< or padded number of slices for 2d array resource
2446 UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements
2447 UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements
2448 UINT_32 mipChainSlice; ///< Padded depth (of total mip chain)
2449 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes
2450 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes
2451 UINT_32 baseAlign; ///< Base address alignment
2452 UINT_32 bpp; ///< Bits per elements
2453 /// (e.g. blocks for BCn, 1/3 for 96bit)
2454 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels
2455 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels
2456 UINT_32 pixelPitch; ///< Pitch in original pixels
2457 UINT_32 pixelHeight; ///< Height in original pixels
2458 UINT_32 pixelBits; ///< Original bits per pixel, passed from input
2459
2460 UINT_32 blockWidth; ///< Width in element inside one block
2461 UINT_32 blockHeight; ///< Height in element inside one block
2462 UINT_32 blockSlices; ///< Slice number inside one block
2463 ///< Prt tile is one block, its width/height/slice
2464 ///< equals to blcok width/height/slice
2465
2466 BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register
2467 /// Stereo info
2468 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE
2469 /// Mip info
2470 ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array
2471 /// if it is not NULL, the array is assumed to
2472 /// contain numMipLevels entries
2473
2474 UINT_32 equationIndex; ///< Equation index in the equation table of mip0
2475 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block
2476 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip
2477 /// in tail, it will be set to number of mip levels
2478 } ADDR2_COMPUTE_SURFACE_INFO_OUTPUT;
2479
2480 /**
2481 ****************************************************************************************************
2482 * Addr2ComputeSurfaceInfo
2483 *
2484 * @brief
2485 * Compute surface width/height/slices/alignments and suitable tiling mode
2486 ****************************************************************************************************
2487 */
2488 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo(
2489 ADDR_HANDLE hLib,
2490 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn,
2491 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut);
2492
2493 /**
2494 ****************************************************************************************************
2495 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
2496 *
2497 * @brief
2498 * Input structure for Addr2ComputeSurfaceAddrFromCoord
2499 ****************************************************************************************************
2500 */
2501 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT
2502 {
2503 UINT_32 size; ///< Size of this structure in bytes
2504
2505 UINT_32 x; ///< X coordinate
2506 UINT_32 y; ///< Y coordinate
2507 UINT_32 slice; ///< Slice index
2508 UINT_32 sample; ///< Sample index, use fragment index for EQAA
2509 UINT_32 mipId; ///< the mip ID in mip chain
2510
2511 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9
2512 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2513 AddrResourceType resourceType; ///< Surface type
2514 UINT_32 bpp; ///< Bits per pixel
2515 UINT_32 unalignedWidth; ///< Surface original width (of mip0)
2516 UINT_32 unalignedHeight; ///< Surface original height (of mip0)
2517 UINT_32 numSlices; ///< Surface original slices (of mip0)
2518 UINT_32 numMipLevels; ///< Total mipmap levels
2519 UINT_32 numSamples; ///< Number of samples
2520 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2521 /// number of samples for normal AA; Set it to the
2522 /// number of fragments for EQAA
2523
2524 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation
2525 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2526 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT;
2527
2528 /**
2529 ****************************************************************************************************
2530 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
2531 *
2532 * @brief
2533 * Output structure for Addr2ComputeSurfaceAddrFromCoord
2534 ****************************************************************************************************
2535 */
2536 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT
2537 {
2538 UINT_32 size; ///< Size of this structure in bytes
2539
2540 UINT_64 addr; ///< Byte address
2541 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7.
2542 /// For surface bpp < 8, e.g. FMT_1.
2543 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block)
2544 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT;
2545
2546 /**
2547 ****************************************************************************************************
2548 * Addr2ComputeSurfaceAddrFromCoord
2549 *
2550 * @brief
2551 * Compute surface address from a given coordinate.
2552 ****************************************************************************************************
2553 */
2554 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord(
2555 ADDR_HANDLE hLib,
2556 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
2557 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut);
2558
2559 /**
2560 ****************************************************************************************************
2561 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
2562 *
2563 * @brief
2564 * Input structure for Addr2ComputeSurfaceCoordFromAddr
2565 ****************************************************************************************************
2566 */
2567 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT
2568 {
2569 UINT_32 size; ///< Size of this structure in bytes
2570
2571 UINT_64 addr; ///< Address in bytes
2572 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8,
2573 /// e.g. FMT_1;
2574
2575 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9
2576 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
2577 AddrResourceType resourceType; ///< Surface type
2578 UINT_32 bpp; ///< Bits per pixel
2579 UINT_32 unalignedWidth; ///< Surface original width (of mip0)
2580 UINT_32 unalignedHeight; ///< Surface original height (of mip0)
2581 UINT_32 numSlices; ///< Surface original slices (of mip0)
2582 UINT_32 numMipLevels; ///< Total mipmap levels.
2583 UINT_32 numSamples; ///< Number of samples
2584 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
2585 /// number of samples for normal AA; Set it to the
2586 /// number of fragments for EQAA
2587
2588 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation
2589 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats)
2590 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT;
2591
2592 /**
2593 ****************************************************************************************************
2594 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
2595 *
2596 * @brief
2597 * Output structure for Addr2ComputeSurfaceCoordFromAddr
2598 ****************************************************************************************************
2599 */
2600 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT
2601 {
2602 UINT_32 size; ///< Size of this structure in bytes
2603
2604 UINT_32 x; ///< X coordinate
2605 UINT_32 y; ///< Y coordinate
2606 UINT_32 slice; ///< Index of slices
2607 UINT_32 sample; ///< Index of samples, means fragment index for EQAA
2608 UINT_32 mipId; ///< mipmap level id
2609 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT;
2610
2611 /**
2612 ****************************************************************************************************
2613 * Addr2ComputeSurfaceCoordFromAddr
2614 *
2615 * @brief
2616 * Compute coordinate from a given surface address
2617 ****************************************************************************************************
2618 */
2619 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr(
2620 ADDR_HANDLE hLib,
2621 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
2622 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut);
2623
2624 ////////////////////////////////////////////////////////////////////////////////////////////////////
2625 // HTile functions for Gfx9
2626 ////////////////////////////////////////////////////////////////////////////////////////////////////
2627
2628 /**
2629 ****************************************************************************************************
2630 * ADDR2_META_FLAGS
2631 *
2632 * @brief
2633 * Metadata flags
2634 ****************************************************************************************************
2635 */
2636 typedef union _ADDR2_META_FLAGS
2637 {
2638 struct
2639 {
2640 UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned
2641 UINT_32 rbAligned : 1; ///< if Metadata being RB aligned
2642 UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this!
2643 UINT_32 reserved : 29; ///< Reserved bits
2644 };
2645
2646 UINT_32 value;
2647 } ADDR2_META_FLAGS;
2648
2649 /**
2650 ****************************************************************************************************
2651 * ADDR2_META_MIP_INFO
2652 *
2653 * @brief
2654 * Structure to store per mip metadata information
2655 ****************************************************************************************************
2656 */
2657 typedef struct _ADDR2_META_MIP_INFO
2658 {
2659 BOOL_32 inMiptail;
2660 union
2661 {
2662 struct
2663 {
2664 UINT_32 startX;
2665 UINT_32 startY;
2666 UINT_32 startZ;
2667 UINT_32 width;
2668 UINT_32 height;
2669 UINT_32 depth;
2670 };
2671
2672 struct
2673 {
2674 UINT_32 offset; ///< Metadata offset within one slice,
2675 /// the thickness of a slice is meta block depth.
2676 UINT_32 sliceSize; ///< Metadata size within one slice,
2677 /// the thickness of a slice is meta block depth.
2678 };
2679 };
2680 } ADDR2_META_MIP_INFO;
2681
2682 /**
2683 ****************************************************************************************************
2684 * ADDR2_COMPUTE_HTILE_INFO_INPUT
2685 *
2686 * @brief
2687 * Input structure of Addr2ComputeHtileInfo
2688 ****************************************************************************************************
2689 */
2690 typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT
2691 {
2692 UINT_32 size; ///< Size of this structure in bytes
2693
2694 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2695 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags
2696 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2697 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2698 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2699 UINT_32 numSlices; ///< Number of slices of depth surface (of mip0)
2700 UINT_32 numMipLevels; ///< Total mipmap levels of color surface
2701 UINT_32 firstMipIdInTail; /// Id of the first mip in tail,
2702 /// if no mip is in tail, it should be set to
2703 /// number of mip levels
2704 } ADDR2_COMPUTE_HTILE_INFO_INPUT;
2705
2706 /**
2707 ****************************************************************************************************
2708 * ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2709 *
2710 * @brief
2711 * Output structure of Addr2ComputeHtileInfo
2712 ****************************************************************************************************
2713 */
2714 typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2715 {
2716 UINT_32 size; ///< Size of this structure in bytes
2717
2718 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this
2719 /// HTile buffer. This might be larger than original depth
2720 /// buffer pitch when called with an unaligned pitch.
2721 UINT_32 height; ///< Height in pixels, as above
2722 UINT_32 baseAlign; ///< Base alignment
2723 UINT_32 sliceSize; ///< Slice size, in bytes.
2724 UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes
2725 UINT_32 metaBlkWidth; ///< Meta block width
2726 UINT_32 metaBlkHeight; ///< Meta block height
2727 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
2728
2729 ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information
2730 } ADDR2_COMPUTE_HTILE_INFO_OUTPUT;
2731
2732 /**
2733 ****************************************************************************************************
2734 * Addr2ComputeHtileInfo
2735 *
2736 * @brief
2737 * Compute Htile pitch, height, base alignment and size in bytes
2738 ****************************************************************************************************
2739 */
2740 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo(
2741 ADDR_HANDLE hLib,
2742 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn,
2743 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut);
2744
2745 /**
2746 ****************************************************************************************************
2747 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
2748 *
2749 * @brief
2750 * Input structure for Addr2ComputeHtileAddrFromCoord
2751 ****************************************************************************************************
2752 */
2753 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
2754 {
2755 UINT_32 size; ///< Size of this structure in bytes
2756
2757 UINT_32 x; ///< X coordinate
2758 UINT_32 y; ///< Y coordinate
2759 UINT_32 slice; ///< Index of slices
2760 UINT_32 mipId; ///< mipmap level id
2761
2762 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2763 ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags
2764 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2765 UINT_32 bpp; ///< Depth surface bits per pixel
2766 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2767 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2768 UINT_32 numSlices; ///< Depth surface original depth (of mip0)
2769 UINT_32 numMipLevels; ///< Depth surface total mipmap levels
2770 UINT_32 numSamples; ///< Depth surface number of samples
2771 UINT_32 pipeXor; ///< Pipe xor setting
2772 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT;
2773
2774 /**
2775 ****************************************************************************************************
2776 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
2777 *
2778 * @brief
2779 * Output structure for Addr2ComputeHtileAddrFromCoord
2780 ****************************************************************************************************
2781 */
2782 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
2783 {
2784 UINT_32 size; ///< Size of this structure in bytes
2785
2786 UINT_64 addr; ///< Address in bytes
2787 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT;
2788
2789 /**
2790 ****************************************************************************************************
2791 * Addr2ComputeHtileAddrFromCoord
2792 *
2793 * @brief
2794 * Compute Htile address according to coordinates (of depth buffer)
2795 ****************************************************************************************************
2796 */
2797 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord(
2798 ADDR_HANDLE hLib,
2799 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn,
2800 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut);
2801
2802 /**
2803 ****************************************************************************************************
2804 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
2805 *
2806 * @brief
2807 * Input structure for Addr2ComputeHtileCoordFromAddr
2808 ****************************************************************************************************
2809 */
2810 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT
2811 {
2812 UINT_32 size; ///< Size of this structure in bytes
2813
2814 UINT_64 addr; ///< Address
2815
2816 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags
2817 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags
2818 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode
2819 UINT_32 bpp; ///< Depth surface bits per pixel
2820 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0)
2821 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0)
2822 UINT_32 numSlices; ///< Depth surface original depth (of mip0)
2823 UINT_32 numMipLevels; ///< Depth surface total mipmap levels
2824 UINT_32 numSamples; ///< Depth surface number of samples
2825 UINT_32 pipeXor; ///< Pipe xor setting
2826 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT;
2827
2828 /**
2829 ****************************************************************************************************
2830 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
2831 *
2832 * @brief
2833 * Output structure for Addr2ComputeHtileCoordFromAddr
2834 ****************************************************************************************************
2835 */
2836 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT
2837 {
2838 UINT_32 size; ///< Size of this structure in bytes
2839
2840 UINT_32 x; ///< X coordinate
2841 UINT_32 y; ///< Y coordinate
2842 UINT_32 slice; ///< Index of slices
2843 UINT_32 mipId; ///< mipmap level id
2844 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT;
2845
2846 /**
2847 ****************************************************************************************************
2848 * Addr2ComputeHtileCoordFromAddr
2849 *
2850 * @brief
2851 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to
2852 * Htile address
2853 ****************************************************************************************************
2854 */
2855 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr(
2856 ADDR_HANDLE hLib,
2857 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn,
2858 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut);
2859
2860 ////////////////////////////////////////////////////////////////////////////////////////////////////
2861 // C-mask functions for Gfx9
2862 ////////////////////////////////////////////////////////////////////////////////////////////////////
2863
2864 /**
2865 ****************************************************************************************************
2866 * ADDR2_COMPUTE_CMASK_INFO_INPUT
2867 *
2868 * @brief
2869 * Input structure of Addr2ComputeCmaskInfo
2870 ****************************************************************************************************
2871 */
2872 typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT
2873 {
2874 UINT_32 size; ///< Size of this structure in bytes
2875
2876 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
2877 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
2878 AddrResourceType resourceType; ///< Color surface type
2879 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
2880 UINT_32 unalignedWidth; ///< Color surface original width
2881 UINT_32 unalignedHeight; ///< Color surface original height
2882 UINT_32 numSlices; ///< Number of slices of color buffer
2883 UINT_32 numMipLevels; ///< Number of mip levels
2884 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
2885 /// it should be number of mip levels
2886 } ADDR2_COMPUTE_CMASK_INFO_INPUT;
2887
2888 /**
2889 ****************************************************************************************************
2890 * ADDR2_COMPUTE_CMASK_INFO_OUTPUT
2891 *
2892 * @brief
2893 * Output structure of Addr2ComputeCmaskInfo
2894 ****************************************************************************************************
2895 */
2896 typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT
2897 {
2898 UINT_32 size; ///< Size of this structure in bytes
2899
2900 UINT_32 pitch; ///< Pitch in pixels of color buffer which
2901 /// this Cmask matches. The size might be larger than
2902 /// original color buffer pitch when called with
2903 /// an unaligned pitch.
2904 UINT_32 height; ///< Height in pixels, as above
2905 UINT_32 baseAlign; ///< Base alignment
2906 UINT_32 sliceSize; ///< Slice size, in bytes.
2907 UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer
2908 UINT_32 metaBlkWidth; ///< Meta block width
2909 UINT_32 metaBlkHeight; ///< Meta block height
2910
2911 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
2912
2913 ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information
2914 } ADDR2_COMPUTE_CMASK_INFO_OUTPUT;
2915
2916 /**
2917 ****************************************************************************************************
2918 * Addr2ComputeCmaskInfo
2919 *
2920 * @brief
2921 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer
2922 * info
2923 ****************************************************************************************************
2924 */
2925 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo(
2926 ADDR_HANDLE hLib,
2927 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn,
2928 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut);
2929
2930 /**
2931 ****************************************************************************************************
2932 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
2933 *
2934 * @brief
2935 * Input structure for Addr2ComputeCmaskAddrFromCoord
2936 *
2937 ****************************************************************************************************
2938 */
2939 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
2940 {
2941 UINT_32 size; ///< Size of this structure in bytes
2942
2943 UINT_32 x; ///< X coordinate
2944 UINT_32 y; ///< Y coordinate
2945 UINT_32 slice; ///< Index of slices
2946
2947 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
2948 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
2949 AddrResourceType resourceType; ///< Color surface type
2950 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
2951
2952 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
2953 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
2954 UINT_32 numSlices; ///< Color surface original slices (of mip0)
2955
2956 UINT_32 numSamples; ///< Color surfae sample number
2957 UINT_32 numFrags; ///< Color surface fragment number
2958
2959 UINT_32 pipeXor; ///< pipe Xor setting
2960 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT;
2961
2962 /**
2963 ****************************************************************************************************
2964 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
2965 *
2966 * @brief
2967 * Output structure for Addr2ComputeCmaskAddrFromCoord
2968 ****************************************************************************************************
2969 */
2970 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
2971 {
2972 UINT_32 size; ///< Size of this structure in bytes
2973
2974 UINT_64 addr; ///< CMASK address in bytes
2975 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4
2976 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT;
2977
2978 /**
2979 ****************************************************************************************************
2980 * Addr2ComputeCmaskAddrFromCoord
2981 *
2982 * @brief
2983 * Compute Cmask address according to coordinates (of MSAA color buffer)
2984 ****************************************************************************************************
2985 */
2986 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord(
2987 ADDR_HANDLE hLib,
2988 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn,
2989 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut);
2990
2991 /**
2992 ****************************************************************************************************
2993 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
2994 *
2995 * @brief
2996 * Input structure for Addr2ComputeCmaskCoordFromAddr
2997 ****************************************************************************************************
2998 */
2999 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT
3000 {
3001 UINT_32 size; ///< Size of this structure in bytes
3002
3003 UINT_64 addr; ///< CMASK address in bytes
3004 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4
3005
3006 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags
3007 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3008 AddrResourceType resourceType; ///< Color surface type
3009 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3010
3011 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3012 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3013 UINT_32 numSlices; ///< Color surface original slices (of mip0)
3014 UINT_32 numMipLevels; ///< Color surface total mipmap levels.
3015 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT;
3016
3017 /**
3018 ****************************************************************************************************
3019 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
3020 *
3021 * @brief
3022 * Output structure for Addr2ComputeCmaskCoordFromAddr
3023 ****************************************************************************************************
3024 */
3025 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT
3026 {
3027 UINT_32 size; ///< Size of this structure in bytes
3028
3029 UINT_32 x; ///< X coordinate
3030 UINT_32 y; ///< Y coordinate
3031 UINT_32 slice; ///< Index of slices
3032 UINT_32 mipId; ///< mipmap level id
3033 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT;
3034
3035 /**
3036 ****************************************************************************************************
3037 * Addr2ComputeCmaskCoordFromAddr
3038 *
3039 * @brief
3040 * Compute coordinates within color buffer (1st pixel of a micro tile) according to
3041 * Cmask address
3042 ****************************************************************************************************
3043 */
3044 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr(
3045 ADDR_HANDLE hLib,
3046 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn,
3047 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut);
3048
3049 ////////////////////////////////////////////////////////////////////////////////////////////////////
3050 // F-mask functions for Gfx9
3051 ////////////////////////////////////////////////////////////////////////////////////////////////////
3052
3053 /**
3054 ****************************************************************************************************
3055 * ADDR2_FMASK_FLAGS
3056 *
3057 * @brief
3058 * FMASK flags
3059 ****************************************************************************************************
3060 */
3061 typedef union _ADDR2_FMASK_FLAGS
3062 {
3063 struct
3064 {
3065 UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients
3066 /// by H/W clients. S/W should always set it to FALSE.
3067 UINT_32 reserved : 31; ///< Reserved for future use.
3068 };
3069
3070 UINT_32 value;
3071 } ADDR2_FMASK_FLAGS;
3072
3073 /**
3074 ****************************************************************************************************
3075 * ADDR2_COMPUTE_FMASK_INFO_INPUT
3076 *
3077 * @brief
3078 * Input structure for Addr2ComputeFmaskInfo
3079 ****************************************************************************************************
3080 */
3081 typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT
3082 {
3083 UINT_32 size; ///< Size of this structure in bytes
3084
3085 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3086 UINT_32 unalignedWidth; ///< Color surface original width
3087 UINT_32 unalignedHeight; ///< Color surface original height
3088 UINT_32 numSlices; ///< Number of slices/depth
3089 UINT_32 numSamples; ///< Number of samples
3090 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3091 /// number of samples for normal AA; Set it to the
3092 /// number of fragments for EQAA
3093 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3094 } ADDR2_COMPUTE_FMASK_INFO_INPUT;
3095
3096 /**
3097 ****************************************************************************************************
3098 * ADDR2_COMPUTE_FMASK_INFO_OUTPUT
3099 *
3100 * @brief
3101 * Output structure for Addr2ComputeFmaskInfo
3102 ****************************************************************************************************
3103 */
3104 typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT
3105 {
3106 UINT_32 size; ///< Size of this structure in bytes
3107
3108 UINT_32 pitch; ///< Pitch of fmask in pixels
3109 UINT_32 height; ///< Height of fmask in pixels
3110 UINT_32 baseAlign; ///< Base alignment
3111 UINT_32 numSlices; ///< Slices of fmask
3112 UINT_32 fmaskBytes; ///< Size of fmask in bytes
3113 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes
3114 UINT_32 numSamples; ///< Number of samples
3115 UINT_32 sliceSize; ///< Size of slice in bytes
3116 } ADDR2_COMPUTE_FMASK_INFO_OUTPUT;
3117
3118 /**
3119 ****************************************************************************************************
3120 * Addr2ComputeFmaskInfo
3121 *
3122 * @brief
3123 * Compute Fmask pitch/height/slices/alignments and size in bytes
3124 ****************************************************************************************************
3125 */
3126 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo(
3127 ADDR_HANDLE hLib,
3128 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn,
3129 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut);
3130
3131 /**
3132 ****************************************************************************************************
3133 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
3134 *
3135 * @brief
3136 * Input structure for Addr2ComputeFmaskAddrFromCoord
3137 ****************************************************************************************************
3138 */
3139 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT
3140 {
3141 UINT_32 size; ///< Size of this structure in bytes
3142
3143 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3144 UINT_32 x; ///< X coordinate
3145 UINT_32 y; ///< Y coordinate
3146 UINT_32 slice; ///< Slice index
3147 UINT_32 sample; ///< Sample index (fragment index for EQAA)
3148 UINT_32 plane; ///< Plane number
3149
3150 UINT_32 unalignedWidth; ///< Color surface original width
3151 UINT_32 unalignedHeight; ///< Color surface original height
3152 UINT_32 numSamples; ///< Number of samples
3153 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3154 /// number of samples for normal AA; Set it to the
3155 /// number of fragments for EQAA
3156 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation
3157
3158 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3159 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT;
3160
3161 /**
3162 ****************************************************************************************************
3163 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
3164 *
3165 * @brief
3166 * Output structure for Addr2ComputeFmaskAddrFromCoord
3167 ****************************************************************************************************
3168 */
3169 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT
3170 {
3171 UINT_32 size; ///< Size of this structure in bytes
3172
3173 UINT_64 addr; ///< Fmask address
3174 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7.
3175 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT;
3176
3177 /**
3178 ****************************************************************************************************
3179 * Addr2ComputeFmaskAddrFromCoord
3180 *
3181 * @brief
3182 * Compute Fmask address according to coordinates (x,y,slice,sample,plane)
3183 ****************************************************************************************************
3184 */
3185 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord(
3186 ADDR_HANDLE hLib,
3187 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
3188 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut);
3189
3190 /**
3191 ****************************************************************************************************
3192 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
3193 *
3194 * @brief
3195 * Input structure for Addr2ComputeFmaskCoordFromAddr
3196 ****************************************************************************************************
3197 */
3198 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT
3199 {
3200 UINT_32 size; ///< Size of this structure in bytes
3201
3202 UINT_64 addr; ///< Address
3203 UINT_32 bitPosition; ///< Bit position within addr, 0-7.
3204 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode
3205
3206 UINT_32 unalignedWidth; ///< Color surface original width
3207 UINT_32 unalignedHeight; ///< Color surface original height
3208 UINT_32 numSamples; ///< Number of samples
3209 UINT_32 numFrags; ///< Number of fragments
3210
3211 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation
3212
3213 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags
3214 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT;
3215
3216 /**
3217 ****************************************************************************************************
3218 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
3219 *
3220 * @brief
3221 * Output structure for Addr2ComputeFmaskCoordFromAddr
3222 ****************************************************************************************************
3223 */
3224 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT
3225 {
3226 UINT_32 size; ///< Size of this structure in bytes
3227
3228 UINT_32 x; ///< X coordinate
3229 UINT_32 y; ///< Y coordinate
3230 UINT_32 slice; ///< Slice index
3231 UINT_32 sample; ///< Sample index (fragment index for EQAA)
3232 UINT_32 plane; ///< Plane number
3233 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT;
3234
3235 /**
3236 ****************************************************************************************************
3237 * Addr2ComputeFmaskCoordFromAddr
3238 *
3239 * @brief
3240 * Compute FMASK coordinate from an given address
3241 ****************************************************************************************************
3242 */
3243 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr(
3244 ADDR_HANDLE hLib,
3245 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
3246 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut);
3247
3248 ////////////////////////////////////////////////////////////////////////////////////////////////////
3249 // DCC key functions for Gfx9
3250 ////////////////////////////////////////////////////////////////////////////////////////////////////
3251
3252 /**
3253 ****************************************************************************************************
3254 * _ADDR2_COMPUTE_DCCINFO_INPUT
3255 *
3256 * @brief
3257 * Input structure of Addr2ComputeDccInfo
3258 ****************************************************************************************************
3259 */
3260 typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT
3261 {
3262 UINT_32 size; ///< Size of this structure in bytes
3263
3264 ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags
3265 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3266 AddrResourceType resourceType; ///< Color surface type
3267 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
3268 UINT_32 bpp; ///< bits per pixel
3269 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3270 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3271 UINT_32 numSlices; ///< Number of slices, of color surface (of mip0)
3272 UINT_32 numFrags; ///< Fragment number of color surface
3273 UINT_32 numMipLevels; ///< Total mipmap levels of color surface
3274 UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels
3275 ///< useful in meta linear case
3276 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail,
3277 /// it should be number of mip levels
3278 } ADDR2_COMPUTE_DCCINFO_INPUT;
3279
3280 /**
3281 ****************************************************************************************************
3282 * ADDR2_COMPUTE_DCCINFO_OUTPUT
3283 *
3284 * @brief
3285 * Output structure of Addr2ComputeDccInfo
3286 ****************************************************************************************************
3287 */
3288 typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT
3289 {
3290 UINT_32 size; ///< Size of this structure in bytes
3291
3292 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key
3293 UINT_32 dccRamSize; ///< Size of dcc key
3294
3295 UINT_32 pitch; ///< DCC surface mip chain pitch
3296 UINT_32 height; ///< DCC surface mip chain height
3297 UINT_32 depth; ///< DCC surface mip chain depth
3298
3299 UINT_32 compressBlkWidth; ///< DCC compress block width
3300 UINT_32 compressBlkHeight; ///< DCC compress block height
3301 UINT_32 compressBlkDepth; ///< DCC compress block depth
3302
3303 UINT_32 metaBlkWidth; ///< DCC meta block width
3304 UINT_32 metaBlkHeight; ///< DCC meta block height
3305 UINT_32 metaBlkDepth; ///< DCC meta block depth
3306
3307 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice
3308
3309 union
3310 {
3311 UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared
3312 UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's
3313 /// the slize size of a mip chain, the thickness of a
3314 /// a slice is meta block depth
3315 };
3316
3317 ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information
3318 } ADDR2_COMPUTE_DCCINFO_OUTPUT;
3319
3320 /**
3321 ****************************************************************************************************
3322 * Addr2ComputeDccInfo
3323 *
3324 * @brief
3325 * Compute DCC key size, base alignment
3326 * info
3327 ****************************************************************************************************
3328 */
3329 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo(
3330 ADDR_HANDLE hLib,
3331 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn,
3332 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut);
3333
3334 /**
3335 ****************************************************************************************************
3336 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
3337 *
3338 * @brief
3339 * Input structure for Addr2ComputeDccAddrFromCoord
3340 *
3341 ****************************************************************************************************
3342 */
3343 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT
3344 {
3345 UINT_32 size; ///< Size of this structure in bytes
3346
3347 UINT_32 x; ///< X coordinate
3348 UINT_32 y; ///< Y coordinate
3349 UINT_32 slice; ///< Index of slices
3350 UINT_32 sample; ///< Index of samples, means fragment index for EQAA
3351 UINT_32 mipId; ///< mipmap level id
3352
3353 ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags
3354 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags
3355 AddrResourceType resourceType; ///< Color surface type
3356 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode
3357 UINT_32 bpp; ///< Color surface bits per pixel
3358 UINT_32 unalignedWidth; ///< Color surface original width (of mip0)
3359 UINT_32 unalignedHeight; ///< Color surface original height (of mip0)
3360 UINT_32 numSlices; ///< Color surface original slices (of mip0)
3361 UINT_32 numMipLevels; ///< Color surface mipmap levels
3362 UINT_32 numFrags; ///< Color surface fragment number
3363
3364 UINT_32 pipeXor; ///< pipe Xor setting
3365 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT;
3366
3367 /**
3368 ****************************************************************************************************
3369 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
3370 *
3371 * @brief
3372 * Output structure for Addr2ComputeDccAddrFromCoord
3373 ****************************************************************************************************
3374 */
3375 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT
3376 {
3377 UINT_32 size; ///< Size of this structure in bytes
3378
3379 UINT_64 addr; ///< DCC address in bytes
3380 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT;
3381
3382 /**
3383 ****************************************************************************************************
3384 * Addr2ComputeDccAddrFromCoord
3385 *
3386 * @brief
3387 * Compute DCC address according to coordinates (of MSAA color buffer)
3388 ****************************************************************************************************
3389 */
3390 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord(
3391 ADDR_HANDLE hLib,
3392 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn,
3393 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut);
3394
3395 ////////////////////////////////////////////////////////////////////////////////////////////////////
3396 // Misc functions for Gfx9
3397 ////////////////////////////////////////////////////////////////////////////////////////////////////
3398
3399 /**
3400 ****************************************************************************************************
3401 * ADDR2_COMPUTE_PIPEBANKXOR_INPUT
3402 *
3403 * @brief
3404 * Input structure of Addr2ComputePipebankXor
3405 ****************************************************************************************************
3406 */
3407 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT
3408 {
3409 UINT_32 size; ///< Size of this structure in bytes
3410 UINT_32 surfIndex; ///< Input surface index
3411 ADDR2_SURFACE_FLAGS flags; ///< Surface flag
3412 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3413 AddrResourceType resourceType; ///< Surface resource type
3414 AddrFormat format; ///< Surface format
3415 UINT_32 numSamples; ///< Number of samples
3416 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3417 /// number of samples for normal AA; Set it to the
3418 /// number of fragments for EQAA
3419 } ADDR2_COMPUTE_PIPEBANKXOR_INPUT;
3420
3421 /**
3422 ****************************************************************************************************
3423 * ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
3424 *
3425 * @brief
3426 * Output structure of Addr2ComputePipebankXor
3427 ****************************************************************************************************
3428 */
3429 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT
3430 {
3431 UINT_32 size; ///< Size of this structure in bytes
3432 UINT_32 pipeBankXor; ///< Pipe bank xor
3433 } ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT;
3434
3435 /**
3436 ****************************************************************************************************
3437 * Addr2ComputePipeBankXor
3438 *
3439 * @brief
3440 * Calculate a valid bank pipe xor value for client to use.
3441 ****************************************************************************************************
3442 */
3443 ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor(
3444 ADDR_HANDLE hLib,
3445 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn,
3446 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut);
3447
3448 /**
3449 ****************************************************************************************************
3450 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
3451 *
3452 * @brief
3453 * Input structure of Addr2ComputeSlicePipeBankXor
3454 ****************************************************************************************************
3455 */
3456 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT
3457 {
3458 UINT_32 size; ///< Size of this structure in bytes
3459 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3460 AddrResourceType resourceType; ///< Surface resource type
3461 UINT_32 basePipeBankXor; ///< Base pipe bank xor
3462 UINT_32 slice; ///< Slice id
3463 UINT_32 numSamples; ///< Number of samples
3464 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT;
3465
3466 /**
3467 ****************************************************************************************************
3468 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
3469 *
3470 * @brief
3471 * Output structure of Addr2ComputeSlicePipeBankXor
3472 ****************************************************************************************************
3473 */
3474 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT
3475 {
3476 UINT_32 size; ///< Size of this structure in bytes
3477 UINT_32 pipeBankXor; ///< Pipe bank xor
3478 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT;
3479
3480 /**
3481 ****************************************************************************************************
3482 * Addr2ComputeSlicePipeBankXor
3483 *
3484 * @brief
3485 * Calculate slice pipe bank xor value based on base pipe bank xor and slice id.
3486 ****************************************************************************************************
3487 */
3488 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor(
3489 ADDR_HANDLE hLib,
3490 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn,
3491 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut);
3492
3493 /**
3494 ****************************************************************************************************
3495 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
3496 *
3497 * @brief
3498 * Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
3499 ****************************************************************************************************
3500 */
3501 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT
3502 {
3503 UINT_32 size; ///< Size of this structure in bytes
3504 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode
3505 AddrResourceType resourceType; ///< Surface resource type
3506 UINT_32 pipeBankXor; ///< Per resource xor
3507 UINT_32 slice; ///< Slice id
3508 UINT_64 sliceSize; ///< Slice size of a mip chain
3509 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO
3510 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO
3511 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT;
3512
3513 /**
3514 ****************************************************************************************************
3515 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
3516 *
3517 * @brief
3518 * Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern
3519 ****************************************************************************************************
3520 */
3521 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT
3522 {
3523 UINT_32 size; ///< Size of this structure in bytes
3524 UINT_64 offset; ///< offset
3525 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT;
3526
3527 /**
3528 ****************************************************************************************************
3529 * Addr2ComputeSubResourceOffsetForSwizzlePattern
3530 *
3531 * @brief
3532 * Calculate sub resource offset to support swizzle pattern.
3533 ****************************************************************************************************
3534 */
3535 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern(
3536 ADDR_HANDLE hLib,
3537 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn,
3538 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut);
3539
3540 /**
3541 ****************************************************************************************************
3542 * ADDR2_BLOCK_SET
3543 *
3544 * @brief
3545 * Bit field that defines block type
3546 ****************************************************************************************************
3547 */
3548 typedef union _ADDR2_BLOCK_SET
3549 {
3550 struct
3551 {
3552 UINT_32 micro : 1; // 256B block for 2D resource
3553 UINT_32 macro4KB : 1; // 4KB for 2D/3D resource
3554 UINT_32 macro64KB : 1; // 64KB for 2D/3D resource
3555 UINT_32 var : 1; // VAR block
3556 UINT_32 linear : 1; // Linear block
3557 UINT_32 reserved : 27;
3558 };
3559
3560 UINT_32 value;
3561 } ADDR2_BLOCK_SET;
3562
3563 /**
3564 ****************************************************************************************************
3565 * ADDR2_SWTYPE_SET
3566 *
3567 * @brief
3568 * Bit field that defines swizzle type
3569 ****************************************************************************************************
3570 */
3571 typedef union _ADDR2_SWTYPE_SET
3572 {
3573 struct
3574 {
3575 UINT_32 sw_Z : 1; // SW_*_Z_*
3576 UINT_32 sw_S : 1; // SW_*_S_*
3577 UINT_32 sw_D : 1; // SW_*_D_*
3578 UINT_32 sw_R : 1; // SW_*_R_*
3579 UINT_32 reserved : 28;
3580 };
3581
3582 UINT_32 value;
3583 } ADDR2_SWTYPE_SET;
3584
3585 /**
3586 ****************************************************************************************************
3587 * ADDR2_SWMODE_SET
3588 *
3589 * @brief
3590 * Bit field that defines swizzle type
3591 ****************************************************************************************************
3592 */
3593 typedef union _ADDR2_SWMODE_SET
3594 {
3595 struct
3596 {
3597 UINT_32 swLinear : 1;
3598 UINT_32 sw256B_S : 1;
3599 UINT_32 sw256B_D : 1;
3600 UINT_32 sw256B_R : 1;
3601 UINT_32 sw4KB_Z : 1;
3602 UINT_32 sw4KB_S : 1;
3603 UINT_32 sw4KB_D : 1;
3604 UINT_32 sw4KB_R : 1;
3605 UINT_32 sw64KB_Z : 1;
3606 UINT_32 sw64KB_S : 1;
3607 UINT_32 sw64KB_D : 1;
3608 UINT_32 sw64KB_R : 1;
3609 UINT_32 swVar_Z : 1;
3610 UINT_32 swVar_S : 1;
3611 UINT_32 swVar_D : 1;
3612 UINT_32 swVar_R : 1;
3613 UINT_32 sw64KB_Z_T : 1;
3614 UINT_32 sw64KB_S_T : 1;
3615 UINT_32 sw64KB_D_T : 1;
3616 UINT_32 sw64KB_R_T : 1;
3617 UINT_32 sw4KB_Z_X : 1;
3618 UINT_32 sw4KB_S_X : 1;
3619 UINT_32 sw4KB_D_X : 1;
3620 UINT_32 sw4KB_R_X : 1;
3621 UINT_32 sw64KB_Z_X : 1;
3622 UINT_32 sw64KB_S_X : 1;
3623 UINT_32 sw64KB_D_X : 1;
3624 UINT_32 sw64KB_R_X : 1;
3625 UINT_32 swVar_Z_X : 1;
3626 UINT_32 swVar_S_X : 1;
3627 UINT_32 swVar_D_X : 1;
3628 UINT_32 swVar_R_X : 1;
3629 };
3630
3631 UINT_32 value;
3632 } ADDR2_SWMODE_SET;
3633
3634 /**
3635 ****************************************************************************************************
3636 * ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
3637 *
3638 * @brief
3639 * Input structure of Addr2GetPreferredSurfaceSetting
3640 ****************************************************************************************************
3641 */
3642 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT
3643 {
3644 UINT_32 size; ///< Size of this structure in bytes
3645
3646 ADDR2_SURFACE_FLAGS flags; ///< Surface flags
3647 AddrResourceType resourceType; ///< Surface type
3648 AddrFormat format; ///< Surface format
3649 AddrResrouceLocation resourceLoction; ///< Surface heap choice
3650 ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting
3651 ///< such as linear for DXTn, tiled for YUV
3652 ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted
3653 BOOL_32 noXor; ///< Do not use xor mode for this resource
3654 UINT_32 bpp; ///< bits per pixel
3655 UINT_32 width; ///< Width (of mip0), in pixels
3656 UINT_32 height; ///< Height (of mip0), in pixels
3657 UINT_32 numSlices; ///< Number surface slice/depth (of mip0),
3658 UINT_32 numMipLevels; ///< Total mipmap levels.
3659 UINT_32 numSamples; ///< Number of samples
3660 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as
3661 /// number of samples for normal AA; Set it to the
3662 /// number of fragments for EQAA
3663 UINT_32 maxAlign; ///< maximum base/size alignment requested by client
3664 UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will
3665 /// be padded to multiple of this value (in bytes)
3666 } ADDR2_GET_PREFERRED_SURF_SETTING_INPUT;
3667
3668 /**
3669 ****************************************************************************************************
3670 * ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
3671 *
3672 * @brief
3673 * Output structure of Addr2GetPreferredSurfaceSetting
3674 ****************************************************************************************************
3675 */
3676 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT
3677 {
3678 UINT_32 size; ///< Size of this structure in bytes
3679
3680 AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used
3681 AddrResourceType resourceType; ///< Suggested resource type to program HW
3682 ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination
3683 BOOL_32 canXor; ///< If client can use xor on a valid macro block
3684 /// type
3685 ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination
3686 ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination
3687 ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination
3688 } ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT;
3689
3690 /**
3691 ****************************************************************************************************
3692 * Addr2GetPreferredSurfaceSetting
3693 *
3694 * @brief
3695 * Suggest a preferred setting for client driver to program HW register
3696 ****************************************************************************************************
3697 */
3698 ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting(
3699 ADDR_HANDLE hLib,
3700 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn,
3701 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut);
3702
3703 /**
3704 ****************************************************************************************************
3705 * Addr2IsValidDisplaySwizzleMode
3706 *
3707 * @brief
3708 * Return whether the swizzle mode is supported by DCE / DCN.
3709 ****************************************************************************************************
3710 */
3711 ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode(
3712 ADDR_HANDLE hLib,
3713 AddrSwizzleMode swizzleMode,
3714 UINT_32 bpp,
3715 bool *result);
3716
3717 #if defined(__cplusplus)
3718 }
3719 #endif
3720
3721 #endif // __ADDR_INTERFACE_H__