1 #if !defined (__SI_GB_REG_H__)
2 #define __SI_GB_REG_H__
5 * Copyright © 2014 Advanced Micro Devices, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining
9 * a copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
18 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
20 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * The above copyright notice and this permission notice (including the
26 * next paragraph) shall be included in all copies or substantial portions
31 // Make sure the necessary endian defines are there.
33 #if defined(LITTLEENDIAN_CPU)
34 #elif defined(BIGENDIAN_CPU)
36 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
40 * GB_ADDR_CONFIG struct
43 #if defined(LITTLEENDIAN_CPU)
45 typedef struct _GB_ADDR_CONFIG_T
{
46 unsigned int num_pipes
: 3;
48 unsigned int pipe_interleave_size
: 3;
50 unsigned int bank_interleave_size
: 3;
52 unsigned int num_shader_engines
: 2;
54 unsigned int shader_engine_tile_size
: 3;
56 unsigned int num_gpus
: 3;
58 unsigned int multi_gpu_tile_size
: 2;
60 unsigned int row_size
: 2;
61 unsigned int num_lower_pipes
: 1;
65 #elif defined(BIGENDIAN_CPU)
67 typedef struct _GB_ADDR_CONFIG_T
{
69 unsigned int num_lower_pipes
: 1;
70 unsigned int row_size
: 2;
72 unsigned int multi_gpu_tile_size
: 2;
74 unsigned int num_gpus
: 3;
76 unsigned int shader_engine_tile_size
: 3;
78 unsigned int num_shader_engines
: 2;
80 unsigned int bank_interleave_size
: 3;
82 unsigned int pipe_interleave_size
: 3;
84 unsigned int num_pipes
: 3;
90 unsigned int val
: 32;
94 #if defined(LITTLEENDIAN_CPU)
96 typedef struct _GB_TILE_MODE_T
{
97 unsigned int micro_tile_mode
: 2;
98 unsigned int array_mode
: 4;
99 unsigned int pipe_config
: 5;
100 unsigned int tile_split
: 3;
101 unsigned int bank_width
: 2;
102 unsigned int bank_height
: 2;
103 unsigned int macro_tile_aspect
: 2;
104 unsigned int num_banks
: 2;
105 unsigned int micro_tile_mode_new
: 3;
106 unsigned int sample_split
: 2;
110 typedef struct _GB_MACROTILE_MODE_T
{
111 unsigned int bank_width
: 2;
112 unsigned int bank_height
: 2;
113 unsigned int macro_tile_aspect
: 2;
114 unsigned int num_banks
: 2;
116 } GB_MACROTILE_MODE_T
;
118 #elif defined(BIGENDIAN_CPU)
120 typedef struct _GB_TILE_MODE_T
{
122 unsigned int sample_split
: 2;
123 unsigned int micro_tile_mode_new
: 3;
124 unsigned int num_banks
: 2;
125 unsigned int macro_tile_aspect
: 2;
126 unsigned int bank_height
: 2;
127 unsigned int bank_width
: 2;
128 unsigned int tile_split
: 3;
129 unsigned int pipe_config
: 5;
130 unsigned int array_mode
: 4;
131 unsigned int micro_tile_mode
: 2;
134 typedef struct _GB_MACROTILE_MODE_T
{
136 unsigned int num_banks
: 2;
137 unsigned int macro_tile_aspect
: 2;
138 unsigned int bank_height
: 2;
139 unsigned int bank_width
: 2;
140 } GB_MACROTILE_MODE_T
;
145 unsigned int val
: 32;
150 unsigned int val
: 32;
151 GB_MACROTILE_MODE_T f
;