2 * Copyright © 2014 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
28 ****************************************************************************************************
30 * @brief Contains the implementation for the CiLib class.
31 ****************************************************************************************************
34 #include "ciaddrlib.h"
36 #include "si_gb_reg.h"
38 #include "amdgpu_asic_addr.h"
40 ////////////////////////////////////////////////////////////////////////////////////////////////////
41 ////////////////////////////////////////////////////////////////////////////////////////////////////
47 ****************************************************************************************************
51 * Creates an CiLib object.
54 * Returns an CiLib object pointer.
55 ****************************************************************************************************
57 Lib
* CiHwlInit(const Client
* pClient
)
59 return V1::CiLib::CreateObj(pClient
);
66 ****************************************************************************************************
70 * Gets a mask of "width"
73 ****************************************************************************************************
76 UINT_32 width
) ///< Width of bits
80 if (width
>= sizeof(UINT_64
)*8)
86 return (((UINT_64
) 1) << width
) - 1;
92 ****************************************************************************************************
96 * Gets bits within a range of [msb, lsb]
99 ****************************************************************************************************
101 static UINT_64
GetBits(
102 UINT_64 bits
, ///< Source bits
103 UINT_32 msb
, ///< Most signicant bit
104 UINT_32 lsb
) ///< Least signicant bit
110 ret
= (bits
>> lsb
) & (Mask(1 + msb
- lsb
));
116 ****************************************************************************************************
120 * Removes bits within the range of [msb, lsb]
123 ****************************************************************************************************
125 static UINT_64
RemoveBits(
126 UINT_64 bits
, ///< Source bits
127 UINT_32 msb
, ///< Most signicant bit
128 UINT_32 lsb
) ///< Least signicant bit
134 ret
= GetBits(bits
, lsb
- 1, 0) // low bits
135 | (GetBits(bits
, 8 * sizeof(bits
) - 1, msb
+ 1) << lsb
); //high bits
141 ****************************************************************************************************
145 * Inserts new bits into the range of [msb, lsb]
148 ****************************************************************************************************
150 static UINT_64
InsertBits(
151 UINT_64 bits
, ///< Source bits
152 UINT_64 newBits
, ///< New bits to be inserted
153 UINT_32 msb
, ///< Most signicant bit
154 UINT_32 lsb
) ///< Least signicant bit
160 ret
= GetBits(bits
, lsb
- 1, 0) // old low bitss
161 | (GetBits(newBits
, msb
- lsb
, 0) << lsb
) //new bits
162 | (GetBits(bits
, 8 * sizeof(bits
) - 1, lsb
) << (msb
+ 1)); //old high bits
168 ****************************************************************************************************
174 ****************************************************************************************************
176 CiLib::CiLib(const Client
* pClient
)
179 m_noOfMacroEntries(0),
180 m_allowNonDispThickModes(FALSE
)
182 m_class
= CI_ADDRLIB
;
186 ****************************************************************************************************
191 ****************************************************************************************************
198 ****************************************************************************************************
199 * CiLib::HwlComputeDccInfo
202 * Compute DCC key size, base alignment
205 ****************************************************************************************************
207 ADDR_E_RETURNCODE
CiLib::HwlComputeDccInfo(
208 const ADDR_COMPUTE_DCCINFO_INPUT
* pIn
,
209 ADDR_COMPUTE_DCCINFO_OUTPUT
* pOut
) const
211 ADDR_E_RETURNCODE returnCode
= ADDR_OK
;
213 if (m_settings
.isVolcanicIslands
&& IsMacroTiled(pIn
->tileMode
))
215 UINT_64 dccFastClearSize
= pIn
->colorSurfSize
>> 8;
217 ADDR_ASSERT(0 == (pIn
->colorSurfSize
& 0xff));
219 if (pIn
->numSamples
> 1)
221 UINT_32 tileSizePerSample
= BITS_TO_BYTES(pIn
->bpp
* MicroTileWidth
* MicroTileHeight
);
222 UINT_32 samplesPerSplit
= pIn
->tileInfo
.tileSplitBytes
/ tileSizePerSample
;
224 if (samplesPerSplit
< pIn
->numSamples
)
226 UINT_32 numSplits
= pIn
->numSamples
/ samplesPerSplit
;
227 UINT_32 fastClearBaseAlign
= HwlGetPipes(&pIn
->tileInfo
) * m_pipeInterleaveBytes
;
229 ADDR_ASSERT(IsPow2(fastClearBaseAlign
));
231 dccFastClearSize
/= numSplits
;
233 if (0 != (dccFastClearSize
& (fastClearBaseAlign
- 1)))
235 // Disable dcc fast clear
236 // if key size of fisrt sample split is not pipe*interleave aligned
237 dccFastClearSize
= 0;
242 pOut
->dccRamSize
= pIn
->colorSurfSize
>> 8;
243 pOut
->dccRamBaseAlign
= pIn
->tileInfo
.banks
*
244 HwlGetPipes(&pIn
->tileInfo
) *
245 m_pipeInterleaveBytes
;
246 pOut
->dccFastClearSize
= dccFastClearSize
;
247 pOut
->dccRamSizeAligned
= TRUE
;
249 ADDR_ASSERT(IsPow2(pOut
->dccRamBaseAlign
));
251 if (0 == (pOut
->dccRamSize
& (pOut
->dccRamBaseAlign
- 1)))
253 pOut
->subLvlCompressible
= TRUE
;
257 UINT_64 dccRamSizeAlign
= HwlGetPipes(&pIn
->tileInfo
) * m_pipeInterleaveBytes
;
259 if (pOut
->dccRamSize
== pOut
->dccFastClearSize
)
261 pOut
->dccFastClearSize
= PowTwoAlign(pOut
->dccRamSize
, dccRamSizeAlign
);
263 if ((pOut
->dccRamSize
& (dccRamSizeAlign
- 1)) != 0)
265 pOut
->dccRamSizeAligned
= FALSE
;
267 pOut
->dccRamSize
= PowTwoAlign(pOut
->dccRamSize
, dccRamSizeAlign
);
268 pOut
->subLvlCompressible
= FALSE
;
273 returnCode
= ADDR_NOTSUPPORTED
;
280 ****************************************************************************************************
281 * CiLib::HwlComputeCmaskAddrFromCoord
284 * Compute tc compatible Cmask address from fmask ram address
288 ****************************************************************************************************
290 ADDR_E_RETURNCODE
CiLib::HwlComputeCmaskAddrFromCoord(
291 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT
* pIn
, ///< [in] fmask addr/bpp/tile input
292 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT
* pOut
///< [out] cmask address
295 ADDR_E_RETURNCODE returnCode
= ADDR_NOTSUPPORTED
;
297 if ((m_settings
.isVolcanicIslands
== TRUE
) &&
298 (pIn
->flags
.tcCompatible
== TRUE
))
300 UINT_32 numOfPipes
= HwlGetPipes(pIn
->pTileInfo
);
301 UINT_32 numOfBanks
= pIn
->pTileInfo
->banks
;
302 UINT_64 fmaskAddress
= pIn
->fmaskAddr
;
303 UINT_32 elemBits
= pIn
->bpp
;
304 UINT_32 blockByte
= 64 * elemBits
/ 8;
305 UINT_64 metaNibbleAddress
= HwlComputeMetadataNibbleAddress(fmaskAddress
,
311 m_pipeInterleaveBytes
,
315 pOut
->addr
= (metaNibbleAddress
>> 1);
316 pOut
->bitPosition
= (metaNibbleAddress
% 2) ? 4 : 0;
317 returnCode
= ADDR_OK
;
324 ****************************************************************************************************
325 * CiLib::HwlComputeHtileAddrFromCoord
328 * Compute tc compatible Htile address from depth/stencil address
332 ****************************************************************************************************
334 ADDR_E_RETURNCODE
CiLib::HwlComputeHtileAddrFromCoord(
335 const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT
* pIn
, ///< [in] depth/stencil addr/bpp/tile input
336 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT
* pOut
///< [out] htile address
339 ADDR_E_RETURNCODE returnCode
= ADDR_NOTSUPPORTED
;
341 if ((m_settings
.isVolcanicIslands
== TRUE
) &&
342 (pIn
->flags
.tcCompatible
== TRUE
))
344 UINT_32 numOfPipes
= HwlGetPipes(pIn
->pTileInfo
);
345 UINT_32 numOfBanks
= pIn
->pTileInfo
->banks
;
346 UINT_64 zStencilAddr
= pIn
->zStencilAddr
;
347 UINT_32 elemBits
= pIn
->bpp
;
348 UINT_32 blockByte
= 64 * elemBits
/ 8;
349 UINT_64 metaNibbleAddress
= HwlComputeMetadataNibbleAddress(zStencilAddr
,
355 m_pipeInterleaveBytes
,
359 pOut
->addr
= (metaNibbleAddress
>> 1);
360 pOut
->bitPosition
= 0;
361 returnCode
= ADDR_OK
;
368 ****************************************************************************************************
369 * CiLib::HwlConvertChipFamily
372 * Convert familyID defined in atiid.h to ChipFamily and set m_chipFamily/m_chipRevision
375 ****************************************************************************************************
377 ChipFamily
CiLib::HwlConvertChipFamily(
378 UINT_32 uChipFamily
, ///< [in] chip family defined in atiih.h
379 UINT_32 uChipRevision
) ///< [in] chip revision defined in "asic_family"_id.h
381 ChipFamily family
= ADDR_CHIP_FAMILY_CI
;
386 m_settings
.isSeaIsland
= 1;
387 m_settings
.isBonaire
= ASICREV_IS_BONAIRE_M(uChipRevision
);
388 m_settings
.isHawaii
= ASICREV_IS_HAWAII_P(uChipRevision
);
391 m_settings
.isKaveri
= 1;
392 m_settings
.isSpectre
= ASICREV_IS_SPECTRE(uChipRevision
);
393 m_settings
.isSpooky
= ASICREV_IS_SPOOKY(uChipRevision
);
394 m_settings
.isKalindi
= ASICREV_IS_KALINDI(uChipRevision
);
397 m_settings
.isVolcanicIslands
= 1;
398 m_settings
.isIceland
= ASICREV_IS_ICELAND_M(uChipRevision
);
399 m_settings
.isTonga
= ASICREV_IS_TONGA_P(uChipRevision
);
400 m_settings
.isFiji
= ASICREV_IS_FIJI_P(uChipRevision
);
401 m_settings
.isPolaris10
= ASICREV_IS_POLARIS10_P(uChipRevision
);
402 m_settings
.isPolaris11
= ASICREV_IS_POLARIS11_M(uChipRevision
);
403 m_settings
.isPolaris12
= ASICREV_IS_POLARIS12_V(uChipRevision
);
404 m_settings
.isVegaM
= ASICREV_IS_VEGAM_P(uChipRevision
);
405 family
= ADDR_CHIP_FAMILY_VI
;
408 m_settings
.isCarrizo
= 1;
409 m_settings
.isVolcanicIslands
= 1;
410 family
= ADDR_CHIP_FAMILY_VI
;
413 ADDR_ASSERT(!"This should be a unexpected Fusion");
421 ****************************************************************************************************
422 * CiLib::HwlInitGlobalParams
425 * Initializes global parameters
428 * TRUE if all settings are valid
430 ****************************************************************************************************
432 BOOL_32
CiLib::HwlInitGlobalParams(
433 const ADDR_CREATE_INPUT
* pCreateIn
) ///< [in] create input
435 BOOL_32 valid
= TRUE
;
437 const ADDR_REGISTER_VALUE
* pRegValue
= &pCreateIn
->regValue
;
439 valid
= DecodeGbRegs(pRegValue
);
441 // The following assignments for m_pipes is only for fail-safe, InitTileSettingTable should
442 // read the correct pipes from tile mode table
443 if (m_settings
.isHawaii
)
447 else if (m_settings
.isBonaire
|| m_settings
.isSpectre
)
451 else // Treat other KV asics to be 2-pipe
457 // Move this to VI code path once created
458 if (m_settings
.isTonga
|| m_settings
.isPolaris10
)
462 else if (m_settings
.isIceland
)
466 else if (m_settings
.isFiji
)
470 else if (m_settings
.isPolaris11
|| m_settings
.isPolaris12
)
474 else if (m_settings
.isVegaM
)
481 valid
= InitTileSettingTable(pRegValue
->pTileConfig
, pRegValue
->noOfEntries
);
485 valid
= InitMacroTileCfgTable(pRegValue
->pMacroTileConfig
, pRegValue
->noOfMacroEntries
);
497 ****************************************************************************************************
498 * CiLib::HwlPostCheckTileIndex
501 * Map a tile setting to index if curIndex is invalid, otherwise check if curIndex matches
502 * tile mode/type/info and change the index if needed
505 ****************************************************************************************************
507 INT_32
CiLib::HwlPostCheckTileIndex(
508 const ADDR_TILEINFO
* pInfo
, ///< [in] Tile Info
509 AddrTileMode mode
, ///< [in] Tile mode
510 AddrTileType type
, ///< [in] Tile type
511 INT curIndex
///< [in] Current index assigned in HwlSetupTileInfo
514 INT_32 index
= curIndex
;
516 if (mode
== ADDR_TM_LINEAR_GENERAL
)
518 index
= TileIndexLinearGeneral
;
522 BOOL_32 macroTiled
= IsMacroTiled(mode
);
524 // We need to find a new index if either of them is true
525 // 1. curIndex is invalid
526 // 2. tile mode is changed
527 // 3. tile info does not match for macro tiled
528 if ((index
== TileIndexInvalid
) ||
529 (mode
!= m_tileTable
[index
].mode
) ||
530 (macroTiled
&& pInfo
->pipeConfig
!= m_tileTable
[index
].info
.pipeConfig
))
532 for (index
= 0; index
< static_cast<INT_32
>(m_noOfEntries
); index
++)
536 // macro tile modes need all to match
537 if ((pInfo
->pipeConfig
== m_tileTable
[index
].info
.pipeConfig
) &&
538 (mode
== m_tileTable
[index
].mode
) &&
539 (type
== m_tileTable
[index
].type
))
541 // tileSplitBytes stored in m_tileTable is only valid for depth entries
542 if (type
== ADDR_DEPTH_SAMPLE_ORDER
)
544 if (Min(m_tileTable
[index
].info
.tileSplitBytes
,
545 m_rowSize
) == pInfo
->tileSplitBytes
)
550 else // other entries are determined by other 3 fields
556 else if (mode
== ADDR_TM_LINEAR_ALIGNED
)
558 // linear mode only needs tile mode to match
559 if (mode
== m_tileTable
[index
].mode
)
566 // micro tile modes only need tile mode and tile type to match
567 if (mode
== m_tileTable
[index
].mode
&&
568 type
== m_tileTable
[index
].type
)
577 ADDR_ASSERT(index
< static_cast<INT_32
>(m_noOfEntries
));
579 if (index
>= static_cast<INT_32
>(m_noOfEntries
))
581 index
= TileIndexInvalid
;
588 ****************************************************************************************************
589 * CiLib::HwlSetupTileCfg
592 * Map tile index to tile setting.
595 ****************************************************************************************************
597 ADDR_E_RETURNCODE
CiLib::HwlSetupTileCfg(
598 UINT_32 bpp
, ///< Bits per pixel
599 INT_32 index
, ///< Tile index
600 INT_32 macroModeIndex
, ///< Index in macro tile mode table(CI)
601 ADDR_TILEINFO
* pInfo
, ///< [out] Tile Info
602 AddrTileMode
* pMode
, ///< [out] Tile mode
603 AddrTileType
* pType
///< [out] Tile type
606 ADDR_E_RETURNCODE returnCode
= ADDR_OK
;
608 // Global flag to control usage of tileIndex
609 if (UseTileIndex(index
))
611 if (index
== TileIndexLinearGeneral
)
614 pInfo
->bankWidth
= 1;
615 pInfo
->bankHeight
= 1;
616 pInfo
->macroAspectRatio
= 1;
617 pInfo
->tileSplitBytes
= 64;
618 pInfo
->pipeConfig
= ADDR_PIPECFG_P2
;
620 else if (static_cast<UINT_32
>(index
) >= m_noOfEntries
)
622 returnCode
= ADDR_INVALIDPARAMS
;
626 const TileConfig
* pCfgTable
= GetTileSetting(index
);
630 if (IsMacroTiled(pCfgTable
->mode
))
632 ADDR_ASSERT((macroModeIndex
!= TileIndexInvalid
) &&
633 (macroModeIndex
!= TileIndexNoMacroIndex
));
637 *pInfo
= m_macroTileTable
[macroModeIndex
];
639 if (pCfgTable
->type
== ADDR_DEPTH_SAMPLE_ORDER
)
641 tileSplit
= pCfgTable
->info
.tileSplitBytes
;
647 UINT_32 thickness
= Thickness(pCfgTable
->mode
);
648 UINT_32 tileBytes1x
= BITS_TO_BYTES(bpp
* MicroTilePixels
* thickness
);
649 // Non-depth entries store a split factor
650 UINT_32 sampleSplit
= m_tileTable
[index
].info
.tileSplitBytes
;
651 tileSplit
= Max(256u, sampleSplit
* tileBytes1x
);
655 // Return tileBytes instead if not enough info
656 tileSplit
= pInfo
->tileSplitBytes
;
661 pInfo
->tileSplitBytes
= Min(m_rowSize
, tileSplit
);
663 pInfo
->pipeConfig
= pCfgTable
->info
.pipeConfig
;
665 else // 1D and linear modes, we return default value stored in table
667 *pInfo
= pCfgTable
->info
;
673 *pMode
= pCfgTable
->mode
;
678 *pType
= pCfgTable
->type
;
687 ****************************************************************************************************
688 * CiLib::HwlComputeSurfaceInfo
691 * Entry of CI's ComputeSurfaceInfo
694 ****************************************************************************************************
696 ADDR_E_RETURNCODE
CiLib::HwlComputeSurfaceInfo(
697 const ADDR_COMPUTE_SURFACE_INFO_INPUT
* pIn
, ///< [in] input structure
698 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
///< [out] output structure
701 // If tileIndex is invalid, force macroModeIndex to be invalid, too
702 if (pIn
->tileIndex
== TileIndexInvalid
)
704 pOut
->macroModeIndex
= TileIndexInvalid
;
707 ADDR_E_RETURNCODE retCode
= SiLib::HwlComputeSurfaceInfo(pIn
, pOut
);
709 if ((pIn
->mipLevel
> 0) &&
710 (pOut
->tcCompatible
== TRUE
) &&
711 (pOut
->tileMode
!= pIn
->tileMode
) &&
712 (m_settings
.isVolcanicIslands
== TRUE
))
714 pOut
->tcCompatible
= CheckTcCompatibility(pOut
->pTileInfo
, pIn
->bpp
, pOut
->tileMode
, pOut
->tileType
, pOut
);
717 if (pOut
->macroModeIndex
== TileIndexNoMacroIndex
)
719 pOut
->macroModeIndex
= TileIndexInvalid
;
722 if ((pIn
->flags
.matchStencilTileCfg
== TRUE
) &&
723 (pIn
->flags
.depth
== TRUE
))
725 pOut
->stencilTileIdx
= TileIndexInvalid
;
727 if ((MinDepth2DThinIndex
<= pOut
->tileIndex
) &&
728 (MaxDepth2DThinIndex
>= pOut
->tileIndex
))
730 BOOL_32 depthStencil2DTileConfigMatch
= DepthStencilTileCfgMatch(pIn
, pOut
);
732 if ((depthStencil2DTileConfigMatch
== FALSE
) &&
733 (pOut
->tcCompatible
== TRUE
))
735 pOut
->macroModeIndex
= TileIndexInvalid
;
737 ADDR_COMPUTE_SURFACE_INFO_INPUT localIn
= *pIn
;
738 localIn
.tileIndex
= TileIndexInvalid
;
739 localIn
.pTileInfo
= NULL
;
740 localIn
.flags
.tcCompatible
= FALSE
;
742 SiLib::HwlComputeSurfaceInfo(&localIn
, pOut
);
744 ADDR_ASSERT((MinDepth2DThinIndex
<= pOut
->tileIndex
) && (MaxDepth2DThinIndex
>= pOut
->tileIndex
));
746 depthStencil2DTileConfigMatch
= DepthStencilTileCfgMatch(pIn
, pOut
);
749 if ((depthStencil2DTileConfigMatch
== FALSE
) &&
750 (pIn
->numSamples
<= 1))
752 pOut
->macroModeIndex
= TileIndexInvalid
;
754 ADDR_COMPUTE_SURFACE_INFO_INPUT localIn
= *pIn
;
755 localIn
.tileMode
= ADDR_TM_1D_TILED_THIN1
;
756 localIn
.tileIndex
= TileIndexInvalid
;
757 localIn
.pTileInfo
= NULL
;
759 retCode
= SiLib::HwlComputeSurfaceInfo(&localIn
, pOut
);
763 if (pOut
->tileIndex
== Depth1DThinIndex
)
765 pOut
->stencilTileIdx
= Depth1DThinIndex
;
773 ****************************************************************************************************
774 * CiLib::HwlFmaskSurfaceInfo
776 * Entry of r800's ComputeFmaskInfo
779 ****************************************************************************************************
781 ADDR_E_RETURNCODE
CiLib::HwlComputeFmaskInfo(
782 const ADDR_COMPUTE_FMASK_INFO_INPUT
* pIn
, ///< [in] input structure
783 ADDR_COMPUTE_FMASK_INFO_OUTPUT
* pOut
///< [out] output structure
786 ADDR_E_RETURNCODE retCode
= ADDR_OK
;
788 ADDR_TILEINFO tileInfo
= {0};
789 ADDR_COMPUTE_FMASK_INFO_INPUT fmaskIn
;
792 AddrTileMode tileMode
= pIn
->tileMode
;
794 // Use internal tile info if pOut does not have a valid pTileInfo
795 if (pOut
->pTileInfo
== NULL
)
797 pOut
->pTileInfo
= &tileInfo
;
800 ADDR_ASSERT(tileMode
== ADDR_TM_2D_TILED_THIN1
||
801 tileMode
== ADDR_TM_3D_TILED_THIN1
||
802 tileMode
== ADDR_TM_PRT_TILED_THIN1
||
803 tileMode
== ADDR_TM_PRT_2D_TILED_THIN1
||
804 tileMode
== ADDR_TM_PRT_3D_TILED_THIN1
);
806 ADDR_ASSERT(m_tileTable
[14].mode
== ADDR_TM_2D_TILED_THIN1
);
807 ADDR_ASSERT(m_tileTable
[15].mode
== ADDR_TM_3D_TILED_THIN1
);
809 // The only valid tile modes for fmask are 2D_THIN1 and 3D_THIN1 plus non-displayable
810 INT_32 tileIndex
= tileMode
== ADDR_TM_2D_TILED_THIN1
? 14 : 15;
811 ADDR_SURFACE_FLAGS flags
= {{0}};
814 INT_32 macroModeIndex
= TileIndexInvalid
;
816 UINT_32 numSamples
= pIn
->numSamples
;
817 UINT_32 numFrags
= pIn
->numFrags
== 0 ? numSamples
: pIn
->numFrags
;
819 UINT_32 bpp
= QLog2(numFrags
);
821 // EQAA needs one more bit
822 if (numSamples
> numFrags
)
832 bpp
= Max(8u, bpp
* numSamples
);
834 macroModeIndex
= HwlComputeMacroModeIndex(tileIndex
, flags
, bpp
, numSamples
, pOut
->pTileInfo
);
836 fmaskIn
.tileIndex
= tileIndex
;
837 fmaskIn
.pTileInfo
= pOut
->pTileInfo
;
838 pOut
->macroModeIndex
= macroModeIndex
;
839 pOut
->tileIndex
= tileIndex
;
841 retCode
= DispatchComputeFmaskInfo(&fmaskIn
, pOut
);
843 if (retCode
== ADDR_OK
)
846 HwlPostCheckTileIndex(pOut
->pTileInfo
, pIn
->tileMode
, ADDR_NON_DISPLAYABLE
,
850 // Resets pTileInfo to NULL if the internal tile info is used
851 if (pOut
->pTileInfo
== &tileInfo
)
853 pOut
->pTileInfo
= NULL
;
860 ****************************************************************************************************
861 * CiLib::HwlFmaskPreThunkSurfInfo
864 * Some preparation before thunking a ComputeSurfaceInfo call for Fmask
867 ****************************************************************************************************
869 VOID
CiLib::HwlFmaskPreThunkSurfInfo(
870 const ADDR_COMPUTE_FMASK_INFO_INPUT
* pFmaskIn
, ///< [in] Input of fmask info
871 const ADDR_COMPUTE_FMASK_INFO_OUTPUT
* pFmaskOut
, ///< [in] Output of fmask info
872 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pSurfIn
, ///< [out] Input of thunked surface info
873 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pSurfOut
///< [out] Output of thunked surface info
876 pSurfIn
->tileIndex
= pFmaskIn
->tileIndex
;
877 pSurfOut
->macroModeIndex
= pFmaskOut
->macroModeIndex
;
881 ****************************************************************************************************
882 * CiLib::HwlFmaskPostThunkSurfInfo
885 * Copy hwl extra field after calling thunked ComputeSurfaceInfo
888 ****************************************************************************************************
890 VOID
CiLib::HwlFmaskPostThunkSurfInfo(
891 const ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pSurfOut
, ///< [in] Output of surface info
892 ADDR_COMPUTE_FMASK_INFO_OUTPUT
* pFmaskOut
///< [out] Output of fmask info
895 pFmaskOut
->tileIndex
= pSurfOut
->tileIndex
;
896 pFmaskOut
->macroModeIndex
= pSurfOut
->macroModeIndex
;
900 ****************************************************************************************************
901 * CiLib::HwlDegradeThickTileMode
904 * Degrades valid tile mode for thick modes if needed
908 ****************************************************************************************************
910 AddrTileMode
CiLib::HwlDegradeThickTileMode(
911 AddrTileMode baseTileMode
, ///< [in] base tile mode
912 UINT_32 numSlices
, ///< [in] current number of slices
913 UINT_32
* pBytesPerTile
///< [in,out] pointer to bytes per slice
920 ****************************************************************************************************
921 * CiLib::HwlOptimizeTileMode
924 * Optimize tile mode on CI
929 ****************************************************************************************************
931 VOID
CiLib::HwlOptimizeTileMode(
932 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pInOut
///< [in,out] input output structure
935 AddrTileMode tileMode
= pInOut
->tileMode
;
937 // Override 2D/3D macro tile mode to PRT_* tile mode if
938 // client driver requests this surface is equation compatible
939 if (IsMacroTiled(tileMode
) == TRUE
)
941 if ((pInOut
->flags
.needEquation
== TRUE
) &&
942 (pInOut
->numSamples
<= 1) &&
943 (IsPrtTileMode(tileMode
) == FALSE
))
945 if ((pInOut
->numSlices
> 1) && ((pInOut
->maxBaseAlign
== 0) || (pInOut
->maxBaseAlign
>= Block64K
)))
947 UINT_32 thickness
= Thickness(tileMode
);
951 tileMode
= ADDR_TM_PRT_TILED_THIN1
;
955 static const UINT_32 PrtTileBytes
= 0x10000;
956 // First prt thick tile index in the tile mode table
957 static const UINT_32 PrtThickTileIndex
= 22;
958 ADDR_TILEINFO tileInfo
= {0};
960 HwlComputeMacroModeIndex(PrtThickTileIndex
,
966 UINT_32 macroTileBytes
= ((pInOut
->bpp
) >> 3) * 64 * pInOut
->numSamples
*
967 thickness
* HwlGetPipes(&tileInfo
) *
968 tileInfo
.banks
* tileInfo
.bankWidth
*
971 if (macroTileBytes
<= PrtTileBytes
)
973 tileMode
= ADDR_TM_PRT_TILED_THICK
;
977 tileMode
= ADDR_TM_PRT_TILED_THIN1
;
983 if (pInOut
->maxBaseAlign
!= 0)
985 pInOut
->flags
.dccPipeWorkaround
= FALSE
;
989 if (tileMode
!= pInOut
->tileMode
)
991 pInOut
->tileMode
= tileMode
;
996 ****************************************************************************************************
997 * CiLib::HwlOverrideTileMode
1000 * Override THICK to THIN, for specific formats on CI
1005 ****************************************************************************************************
1007 VOID
CiLib::HwlOverrideTileMode(
1008 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pInOut
///< [in,out] input output structure
1011 AddrTileMode tileMode
= pInOut
->tileMode
;
1012 AddrTileType tileType
= pInOut
->tileType
;
1014 // currently, all CI/VI family do not
1015 // support ADDR_TM_PRT_2D_TILED_THICK,ADDR_TM_PRT_3D_TILED_THICK and
1016 // ADDR_TM_PRT_2D_TILED_THIN1, ADDR_TM_PRT_3D_TILED_THIN1
1019 case ADDR_TM_PRT_2D_TILED_THICK
:
1020 case ADDR_TM_PRT_3D_TILED_THICK
:
1021 tileMode
= ADDR_TM_PRT_TILED_THICK
;
1023 case ADDR_TM_PRT_2D_TILED_THIN1
:
1024 case ADDR_TM_PRT_3D_TILED_THIN1
:
1025 tileMode
= ADDR_TM_PRT_TILED_THIN1
;
1031 // UBTS#404321, we do not need such overriding, as THICK+THICK entries removed from the tile-mode table
1032 if (!m_settings
.isBonaire
)
1034 UINT_32 thickness
= Thickness(tileMode
);
1036 // tile_thickness = (array_mode == XTHICK) ? 8 : ((array_mode == THICK) ? 4 : 1)
1039 switch (pInOut
->format
)
1041 // see //gfxip/gcB/devel/cds/src/verif/tc/models/csim/tcp.cpp
1042 // tcpError("Thick micro tiling is not supported for format...
1043 case ADDR_FMT_X24_8_32_FLOAT
:
1044 case ADDR_FMT_32_AS_8
:
1045 case ADDR_FMT_32_AS_8_8
:
1046 case ADDR_FMT_32_AS_32_32_32_32
:
1049 case ADDR_FMT_GB_GR
:
1050 case ADDR_FMT_BG_RG
:
1051 case ADDR_FMT_1_REVERSED
:
1062 case ADDR_TM_1D_TILED_THICK
:
1063 tileMode
= ADDR_TM_1D_TILED_THIN1
;
1066 case ADDR_TM_2D_TILED_XTHICK
:
1067 case ADDR_TM_2D_TILED_THICK
:
1068 tileMode
= ADDR_TM_2D_TILED_THIN1
;
1071 case ADDR_TM_3D_TILED_XTHICK
:
1072 case ADDR_TM_3D_TILED_THICK
:
1073 tileMode
= ADDR_TM_3D_TILED_THIN1
;
1076 case ADDR_TM_PRT_TILED_THICK
:
1077 tileMode
= ADDR_TM_PRT_TILED_THIN1
;
1080 case ADDR_TM_PRT_2D_TILED_THICK
:
1081 tileMode
= ADDR_TM_PRT_2D_TILED_THIN1
;
1084 case ADDR_TM_PRT_3D_TILED_THICK
:
1085 tileMode
= ADDR_TM_PRT_3D_TILED_THIN1
;
1093 // Switch tile type from thick to thin
1094 if (tileMode
!= pInOut
->tileMode
)
1096 // see tileIndex: 13-18
1097 tileType
= ADDR_NON_DISPLAYABLE
;
1107 if (tileMode
!= pInOut
->tileMode
)
1109 pInOut
->tileMode
= tileMode
;
1110 pInOut
->tileType
= tileType
;
1115 ****************************************************************************************************
1116 * CiLib::HwlSelectTileMode
1119 * Select tile modes.
1124 ****************************************************************************************************
1126 VOID
CiLib::HwlSelectTileMode(
1127 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pInOut
///< [in,out] input output structure
1130 AddrTileMode tileMode
;
1131 AddrTileType tileType
;
1133 if (pInOut
->flags
.rotateDisplay
)
1135 tileMode
= ADDR_TM_2D_TILED_THIN1
;
1136 tileType
= ADDR_ROTATED
;
1138 else if (pInOut
->flags
.volume
)
1140 BOOL_32 bThin
= (m_settings
.isBonaire
== TRUE
) ||
1141 ((m_allowNonDispThickModes
== TRUE
) && (pInOut
->flags
.color
== TRUE
));
1143 if (pInOut
->numSlices
>= 8)
1145 tileMode
= ADDR_TM_2D_TILED_XTHICK
;
1146 tileType
= (bThin
== TRUE
) ? ADDR_NON_DISPLAYABLE
: ADDR_THICK
;
1148 else if (pInOut
->numSlices
>= 4)
1150 tileMode
= ADDR_TM_2D_TILED_THICK
;
1151 tileType
= (bThin
== TRUE
) ? ADDR_NON_DISPLAYABLE
: ADDR_THICK
;
1155 tileMode
= ADDR_TM_2D_TILED_THIN1
;
1156 tileType
= ADDR_NON_DISPLAYABLE
;
1161 tileMode
= ADDR_TM_2D_TILED_THIN1
;
1163 if (pInOut
->flags
.depth
|| pInOut
->flags
.stencil
)
1165 tileType
= ADDR_DEPTH_SAMPLE_ORDER
;
1167 else if ((pInOut
->bpp
<= 32) ||
1168 (pInOut
->flags
.display
== TRUE
) ||
1169 (pInOut
->flags
.overlay
== TRUE
))
1171 tileType
= ADDR_DISPLAYABLE
;
1175 tileType
= ADDR_NON_DISPLAYABLE
;
1179 if (pInOut
->flags
.prt
)
1181 if (Thickness(tileMode
) > 1)
1183 tileMode
= ADDR_TM_PRT_TILED_THICK
;
1184 tileType
= (m_settings
.isBonaire
== TRUE
) ? ADDR_NON_DISPLAYABLE
: ADDR_THICK
;
1188 tileMode
= ADDR_TM_PRT_TILED_THIN1
;
1192 pInOut
->tileMode
= tileMode
;
1193 pInOut
->tileType
= tileType
;
1195 if ((pInOut
->flags
.dccCompatible
== FALSE
) &&
1196 (pInOut
->flags
.tcCompatible
== FALSE
))
1198 pInOut
->flags
.opt4Space
= TRUE
;
1199 pInOut
->maxBaseAlign
= Block64K
;
1202 // Optimize tile mode if possible
1203 OptimizeTileMode(pInOut
);
1205 HwlOverrideTileMode(pInOut
);
1209 ****************************************************************************************************
1210 * CiLib::HwlSetPrtTileMode
1213 * Set PRT tile mode.
1218 ****************************************************************************************************
1220 VOID
CiLib::HwlSetPrtTileMode(
1221 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pInOut
///< [in,out] input output structure
1224 AddrTileMode tileMode
= pInOut
->tileMode
;
1225 AddrTileType tileType
= pInOut
->tileType
;
1227 if (Thickness(tileMode
) > 1)
1229 tileMode
= ADDR_TM_PRT_TILED_THICK
;
1230 tileType
= (m_settings
.isBonaire
== TRUE
) ? ADDR_NON_DISPLAYABLE
: ADDR_THICK
;
1234 tileMode
= ADDR_TM_PRT_TILED_THIN1
;
1235 tileType
= (tileType
== ADDR_THICK
) ? ADDR_NON_DISPLAYABLE
: tileType
;
1238 pInOut
->tileMode
= tileMode
;
1239 pInOut
->tileType
= tileType
;
1243 ****************************************************************************************************
1244 * CiLib::HwlSetupTileInfo
1247 * Setup default value of tile info for SI
1248 ****************************************************************************************************
1250 VOID
CiLib::HwlSetupTileInfo(
1251 AddrTileMode tileMode
, ///< [in] Tile mode
1252 ADDR_SURFACE_FLAGS flags
, ///< [in] Surface type flags
1253 UINT_32 bpp
, ///< [in] Bits per pixel
1254 UINT_32 pitch
, ///< [in] Pitch in pixels
1255 UINT_32 height
, ///< [in] Height in pixels
1256 UINT_32 numSamples
, ///< [in] Number of samples
1257 ADDR_TILEINFO
* pTileInfoIn
, ///< [in] Tile info input: NULL for default
1258 ADDR_TILEINFO
* pTileInfoOut
, ///< [out] Tile info output
1259 AddrTileType inTileType
, ///< [in] Tile type
1260 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
///< [out] Output
1263 UINT_32 thickness
= Thickness(tileMode
);
1264 ADDR_TILEINFO
* pTileInfo
= pTileInfoOut
;
1265 INT index
= TileIndexInvalid
;
1266 INT macroModeIndex
= TileIndexInvalid
;
1269 if (IsLinear(tileMode
) == FALSE
)
1271 // Thick tile modes must use thick micro tile mode but Bonaire does not support due to
1272 // old derived netlists (UBTS 404321)
1275 if (m_settings
.isBonaire
)
1277 inTileType
= ADDR_NON_DISPLAYABLE
;
1279 else if ((m_allowNonDispThickModes
== FALSE
) ||
1280 (inTileType
!= ADDR_NON_DISPLAYABLE
) ||
1281 // There is no PRT_THICK + THIN entry in tile mode table except Bonaire
1282 (IsPrtTileMode(tileMode
) == TRUE
))
1284 inTileType
= ADDR_THICK
;
1287 // 128 bpp tiling must be non-displayable.
1288 // Fmask reuse color buffer's entry but bank-height field can be from another entry
1289 // To simplify the logic, fmask entry should be picked from non-displayable ones
1290 else if (bpp
== 128 || flags
.fmask
)
1292 inTileType
= ADDR_NON_DISPLAYABLE
;
1294 // These two modes only have non-disp entries though they can be other micro tile modes
1295 else if (tileMode
== ADDR_TM_3D_TILED_THIN1
|| tileMode
== ADDR_TM_PRT_3D_TILED_THIN1
)
1297 inTileType
= ADDR_NON_DISPLAYABLE
;
1300 if (flags
.depth
|| flags
.stencil
)
1302 inTileType
= ADDR_DEPTH_SAMPLE_ORDER
;
1306 // tcCompatible flag is only meaningful for gfx8.
1307 if (m_settings
.isVolcanicIslands
== FALSE
)
1309 flags
.tcCompatible
= FALSE
;
1312 if (IsTileInfoAllZero(pTileInfo
))
1314 // See table entries 0-4
1315 if (flags
.depth
|| flags
.stencil
)
1317 // tileSize = thickness * bpp * numSamples * 8 * 8 / 8
1318 UINT_32 tileSize
= thickness
* bpp
* numSamples
* 8;
1320 // Turn off tc compatible if row_size is smaller than tile size (tile split occurs).
1321 if (m_rowSize
< tileSize
)
1323 flags
.tcCompatible
= FALSE
;
1326 if (flags
.nonSplit
| flags
.tcCompatible
| flags
.needEquation
)
1328 // Texture readable depth surface should not be split
1350 // Depth and stencil need to use the same index, thus the pre-defined tile_split
1351 // can meet the requirement to choose the same macro mode index
1352 // uncompressed depth/stencil are not supported for now
1371 // See table entries 5-6
1372 if (inTileType
== ADDR_DEPTH_SAMPLE_ORDER
)
1376 case ADDR_TM_1D_TILED_THIN1
:
1379 case ADDR_TM_PRT_TILED_THIN1
:
1387 // See table entries 8-12
1388 if (inTileType
== ADDR_DISPLAYABLE
)
1392 case ADDR_TM_1D_TILED_THIN1
:
1395 case ADDR_TM_2D_TILED_THIN1
:
1398 case ADDR_TM_PRT_TILED_THIN1
:
1406 // See table entries 13-18
1407 if (inTileType
== ADDR_NON_DISPLAYABLE
)
1411 case ADDR_TM_1D_TILED_THIN1
:
1414 case ADDR_TM_2D_TILED_THIN1
:
1417 case ADDR_TM_3D_TILED_THIN1
:
1420 case ADDR_TM_PRT_TILED_THIN1
:
1428 // See table entries 19-26
1433 case ADDR_TM_1D_TILED_THICK
:
1434 // special check for bonaire, for the compatablity between old KMD and new UMD
1435 index
= ((inTileType
== ADDR_THICK
) || m_settings
.isBonaire
) ? 19 : 18;
1437 case ADDR_TM_2D_TILED_THICK
:
1438 // special check for bonaire, for the compatablity between old KMD and new UMD
1439 index
= ((inTileType
== ADDR_THICK
) || m_settings
.isBonaire
) ? 20 : 24;
1441 case ADDR_TM_3D_TILED_THICK
:
1444 case ADDR_TM_PRT_TILED_THICK
:
1447 case ADDR_TM_2D_TILED_XTHICK
:
1450 case ADDR_TM_3D_TILED_XTHICK
:
1458 // See table entries 27-30
1459 if (inTileType
== ADDR_ROTATED
)
1463 case ADDR_TM_1D_TILED_THIN1
:
1466 case ADDR_TM_2D_TILED_THIN1
:
1469 case ADDR_TM_PRT_TILED_THIN1
:
1472 case ADDR_TM_PRT_2D_TILED_THIN1
:
1482 ADDR_ASSERT((index
+ 1) < static_cast<INT_32
>(m_noOfEntries
));
1483 // Only do this when tile mode table is updated.
1484 if (((tileMode
== ADDR_TM_PRT_TILED_THIN1
) || (tileMode
== ADDR_TM_PRT_TILED_THICK
)) &&
1485 (m_tileTable
[index
+ 1].mode
== tileMode
))
1487 static const UINT_32 PrtTileBytes
= 0x10000;
1488 ADDR_TILEINFO tileInfo
= {0};
1490 HwlComputeMacroModeIndex(index
, flags
, bpp
, numSamples
, &tileInfo
);
1492 UINT_32 macroTileBytes
= (bpp
>> 3) * 64 * numSamples
* thickness
*
1493 HwlGetPipes(&tileInfo
) * tileInfo
.banks
*
1494 tileInfo
.bankWidth
* tileInfo
.bankHeight
;
1496 if (macroTileBytes
!= PrtTileBytes
)
1498 // Switching to next tile mode entry to make sure macro tile size is 64KB
1501 tileInfo
.pipeConfig
= m_tileTable
[index
].info
.pipeConfig
;
1503 macroTileBytes
= (bpp
>> 3) * 64 * numSamples
* thickness
*
1504 HwlGetPipes(&tileInfo
) * tileInfo
.banks
*
1505 tileInfo
.bankWidth
* tileInfo
.bankHeight
;
1507 ADDR_ASSERT(macroTileBytes
== PrtTileBytes
);
1509 flags
.tcCompatible
= FALSE
;
1510 pOut
->dccUnsupport
= TRUE
;
1517 // A pre-filled tile info is ready
1518 index
= pOut
->tileIndex
;
1519 macroModeIndex
= pOut
->macroModeIndex
;
1521 // pass tile type back for post tile index compute
1522 pOut
->tileType
= inTileType
;
1524 if (flags
.depth
|| flags
.stencil
)
1526 // tileSize = thickness * bpp * numSamples * 8 * 8 / 8
1527 UINT_32 tileSize
= thickness
* bpp
* numSamples
* 8;
1529 // Turn off tc compatible if row_size is smaller than tile size (tile split occurs).
1530 if (m_rowSize
< tileSize
)
1532 flags
.tcCompatible
= FALSE
;
1536 UINT_32 numPipes
= GetPipePerSurf(pTileInfo
->pipeConfig
);
1538 if (m_pipes
!= numPipes
)
1540 pOut
->dccUnsupport
= TRUE
;
1544 // We only need to set up tile info if there is a valid index but macroModeIndex is invalid
1545 if ((index
!= TileIndexInvalid
) && (macroModeIndex
== TileIndexInvalid
))
1547 macroModeIndex
= HwlComputeMacroModeIndex(index
, flags
, bpp
, numSamples
, pTileInfo
);
1549 // Copy to pOut->tileType/tileIndex/macroModeIndex
1550 pOut
->tileIndex
= index
;
1551 pOut
->tileType
= m_tileTable
[index
].type
; // Or inTileType, the samea
1552 pOut
->macroModeIndex
= macroModeIndex
;
1554 else if (tileMode
== ADDR_TM_LINEAR_GENERAL
)
1556 pOut
->tileIndex
= TileIndexLinearGeneral
;
1558 // Copy linear-aligned entry??
1559 *pTileInfo
= m_tileTable
[8].info
;
1561 else if (tileMode
== ADDR_TM_LINEAR_ALIGNED
)
1563 pOut
->tileIndex
= 8;
1564 *pTileInfo
= m_tileTable
[8].info
;
1567 if (flags
.tcCompatible
)
1569 flags
.tcCompatible
= CheckTcCompatibility(pTileInfo
, bpp
, tileMode
, inTileType
, pOut
);
1572 pOut
->tcCompatible
= flags
.tcCompatible
;
1576 ****************************************************************************************************
1577 * CiLib::ReadGbTileMode
1580 * Convert GB_TILE_MODE HW value to ADDR_TILE_CONFIG.
1581 ****************************************************************************************************
1583 VOID
CiLib::ReadGbTileMode(
1584 UINT_32 regValue
, ///< [in] GB_TILE_MODE register
1585 TileConfig
* pCfg
///< [out] output structure
1588 GB_TILE_MODE gbTileMode
;
1589 gbTileMode
.val
= regValue
;
1591 pCfg
->type
= static_cast<AddrTileType
>(gbTileMode
.f
.micro_tile_mode_new
);
1592 pCfg
->info
.pipeConfig
= static_cast<AddrPipeCfg
>(gbTileMode
.f
.pipe_config
+ 1);
1594 if (pCfg
->type
== ADDR_DEPTH_SAMPLE_ORDER
)
1596 pCfg
->info
.tileSplitBytes
= 64 << gbTileMode
.f
.tile_split
;
1600 pCfg
->info
.tileSplitBytes
= 1 << gbTileMode
.f
.sample_split
;
1603 UINT_32 regArrayMode
= gbTileMode
.f
.array_mode
;
1605 pCfg
->mode
= static_cast<AddrTileMode
>(regArrayMode
);
1607 switch (regArrayMode
)
1610 pCfg
->mode
= ADDR_TM_PRT_TILED_THIN1
;
1613 pCfg
->mode
= ADDR_TM_PRT_2D_TILED_THIN1
;
1616 pCfg
->mode
= ADDR_TM_2D_TILED_XTHICK
;
1619 pCfg
->mode
= ADDR_TM_PRT_TILED_THICK
;
1622 pCfg
->mode
= ADDR_TM_PRT_2D_TILED_THICK
;
1625 pCfg
->mode
= ADDR_TM_PRT_3D_TILED_THIN1
;
1628 pCfg
->mode
= ADDR_TM_3D_TILED_XTHICK
;
1631 pCfg
->mode
= ADDR_TM_PRT_3D_TILED_THICK
;
1637 // Fail-safe code for these always convert tile info, as the non-macro modes
1638 // return the entry of tile mode table directly without looking up macro mode table
1639 if (!IsMacroTiled(pCfg
->mode
))
1641 pCfg
->info
.banks
= 2;
1642 pCfg
->info
.bankWidth
= 1;
1643 pCfg
->info
.bankHeight
= 1;
1644 pCfg
->info
.macroAspectRatio
= 1;
1645 pCfg
->info
.tileSplitBytes
= 64;
1650 ****************************************************************************************************
1651 * CiLib::InitTileSettingTable
1654 * Initialize the ADDR_TILE_CONFIG table.
1656 * TRUE if tile table is correctly initialized
1657 ****************************************************************************************************
1659 BOOL_32
CiLib::InitTileSettingTable(
1660 const UINT_32
* pCfg
, ///< [in] Pointer to table of tile configs
1661 UINT_32 noOfEntries
///< [in] Numbe of entries in the table above
1664 BOOL_32 initOk
= TRUE
;
1666 ADDR_ASSERT(noOfEntries
<= TileTableSize
);
1668 memset(m_tileTable
, 0, sizeof(m_tileTable
));
1670 if (noOfEntries
!= 0)
1672 m_noOfEntries
= noOfEntries
;
1676 m_noOfEntries
= TileTableSize
;
1679 if (pCfg
) // From Client
1681 for (UINT_32 i
= 0; i
< m_noOfEntries
; i
++)
1683 ReadGbTileMode(*(pCfg
+ i
), &m_tileTable
[i
]);
1688 ADDR_ASSERT_ALWAYS();
1694 ADDR_ASSERT(m_tileTable
[TILEINDEX_LINEAR_ALIGNED
].mode
== ADDR_TM_LINEAR_ALIGNED
);
1696 if (m_settings
.isBonaire
== FALSE
)
1698 // Check if entry 18 is "thick+thin" combination
1699 if ((m_tileTable
[18].mode
== ADDR_TM_1D_TILED_THICK
) &&
1700 (m_tileTable
[18].type
== ADDR_NON_DISPLAYABLE
))
1702 m_allowNonDispThickModes
= TRUE
;
1703 ADDR_ASSERT(m_tileTable
[24].mode
== ADDR_TM_2D_TILED_THICK
);
1708 m_allowNonDispThickModes
= TRUE
;
1711 // Assume the first entry is always programmed with full pipes
1712 m_pipes
= HwlGetPipes(&m_tileTable
[0].info
);
1719 ****************************************************************************************************
1720 * CiLib::ReadGbMacroTileCfg
1723 * Convert GB_MACRO_TILE_CFG HW value to ADDR_TILE_CONFIG.
1724 ****************************************************************************************************
1726 VOID
CiLib::ReadGbMacroTileCfg(
1727 UINT_32 regValue
, ///< [in] GB_MACRO_TILE_MODE register
1728 ADDR_TILEINFO
* pCfg
///< [out] output structure
1731 GB_MACROTILE_MODE gbTileMode
;
1732 gbTileMode
.val
= regValue
;
1734 pCfg
->bankHeight
= 1 << gbTileMode
.f
.bank_height
;
1735 pCfg
->bankWidth
= 1 << gbTileMode
.f
.bank_width
;
1736 pCfg
->banks
= 1 << (gbTileMode
.f
.num_banks
+ 1);
1737 pCfg
->macroAspectRatio
= 1 << gbTileMode
.f
.macro_tile_aspect
;
1741 ****************************************************************************************************
1742 * CiLib::InitMacroTileCfgTable
1745 * Initialize the ADDR_MACRO_TILE_CONFIG table.
1747 * TRUE if macro tile table is correctly initialized
1748 ****************************************************************************************************
1750 BOOL_32
CiLib::InitMacroTileCfgTable(
1751 const UINT_32
* pCfg
, ///< [in] Pointer to table of tile configs
1752 UINT_32 noOfMacroEntries
///< [in] Numbe of entries in the table above
1755 BOOL_32 initOk
= TRUE
;
1757 ADDR_ASSERT(noOfMacroEntries
<= MacroTileTableSize
);
1759 memset(m_macroTileTable
, 0, sizeof(m_macroTileTable
));
1761 if (noOfMacroEntries
!= 0)
1763 m_noOfMacroEntries
= noOfMacroEntries
;
1767 m_noOfMacroEntries
= MacroTileTableSize
;
1770 if (pCfg
) // From Client
1772 for (UINT_32 i
= 0; i
< m_noOfMacroEntries
; i
++)
1774 ReadGbMacroTileCfg(*(pCfg
+ i
), &m_macroTileTable
[i
]);
1776 m_macroTileTable
[i
].tileSplitBytes
= 64 << (i
% 8);
1781 ADDR_ASSERT_ALWAYS();
1788 ****************************************************************************************************
1789 * CiLib::HwlComputeMacroModeIndex
1792 * Computes macro tile mode index
1794 * TRUE if macro tile table is correctly initialized
1795 ****************************************************************************************************
1797 INT_32
CiLib::HwlComputeMacroModeIndex(
1798 INT_32 tileIndex
, ///< [in] Tile mode index
1799 ADDR_SURFACE_FLAGS flags
, ///< [in] Surface flags
1800 UINT_32 bpp
, ///< [in] Bit per pixel
1801 UINT_32 numSamples
, ///< [in] Number of samples
1802 ADDR_TILEINFO
* pTileInfo
, ///< [out] Pointer to ADDR_TILEINFO
1803 AddrTileMode
* pTileMode
, ///< [out] Pointer to AddrTileMode
1804 AddrTileType
* pTileType
///< [out] Pointer to AddrTileType
1807 INT_32 macroModeIndex
= TileIndexInvalid
;
1809 AddrTileMode tileMode
= m_tileTable
[tileIndex
].mode
;
1810 AddrTileType tileType
= m_tileTable
[tileIndex
].type
;
1811 UINT_32 thickness
= Thickness(tileMode
);
1813 if (!IsMacroTiled(tileMode
))
1815 *pTileInfo
= m_tileTable
[tileIndex
].info
;
1816 macroModeIndex
= TileIndexNoMacroIndex
;
1820 UINT_32 tileBytes1x
= BITS_TO_BYTES(bpp
* MicroTilePixels
* thickness
);
1823 if (m_tileTable
[tileIndex
].type
== ADDR_DEPTH_SAMPLE_ORDER
)
1825 // Depth entries store real tileSplitBytes
1826 tileSplit
= m_tileTable
[tileIndex
].info
.tileSplitBytes
;
1830 // Non-depth entries store a split factor
1831 UINT_32 sampleSplit
= m_tileTable
[tileIndex
].info
.tileSplitBytes
;
1832 UINT_32 colorTileSplit
= Max(256u, sampleSplit
* tileBytes1x
);
1834 tileSplit
= colorTileSplit
;
1837 UINT_32 tileSplitC
= Min(m_rowSize
, tileSplit
);
1842 tileBytes
= Min(tileSplitC
, tileBytes1x
);
1846 tileBytes
= Min(tileSplitC
, numSamples
* tileBytes1x
);
1854 macroModeIndex
= Log2(tileBytes
/ 64);
1856 if (flags
.prt
|| IsPrtTileMode(tileMode
))
1858 macroModeIndex
+= PrtMacroModeOffset
;
1859 *pTileInfo
= m_macroTileTable
[macroModeIndex
];
1863 *pTileInfo
= m_macroTileTable
[macroModeIndex
];
1866 pTileInfo
->pipeConfig
= m_tileTable
[tileIndex
].info
.pipeConfig
;
1868 pTileInfo
->tileSplitBytes
= tileSplitC
;
1871 if (NULL
!= pTileMode
)
1873 *pTileMode
= tileMode
;
1876 if (NULL
!= pTileType
)
1878 *pTileType
= tileType
;
1881 return macroModeIndex
;
1885 ****************************************************************************************************
1886 * CiLib::HwlComputeTileDataWidthAndHeightLinear
1889 * Compute the squared cache shape for per-tile data (CMASK and HTILE) for linear layout
1892 * MacroWidth and macroHeight are measured in pixels
1893 ****************************************************************************************************
1895 VOID
CiLib::HwlComputeTileDataWidthAndHeightLinear(
1896 UINT_32
* pMacroWidth
, ///< [out] macro tile width
1897 UINT_32
* pMacroHeight
, ///< [out] macro tile height
1898 UINT_32 bpp
, ///< [in] bits per pixel
1899 ADDR_TILEINFO
* pTileInfo
///< [in] tile info
1902 ADDR_ASSERT(pTileInfo
!= NULL
);
1906 switch (pTileInfo
->pipeConfig
)
1908 case ADDR_PIPECFG_P16_32x32_8x16
:
1909 case ADDR_PIPECFG_P16_32x32_16x16
:
1910 case ADDR_PIPECFG_P8_32x64_32x32
:
1911 case ADDR_PIPECFG_P8_32x32_16x32
:
1912 case ADDR_PIPECFG_P8_32x32_16x16
:
1913 case ADDR_PIPECFG_P8_32x32_8x16
:
1914 case ADDR_PIPECFG_P4_32x32
:
1922 *pMacroWidth
= numTiles
* MicroTileWidth
;
1923 *pMacroHeight
= numTiles
* MicroTileHeight
;
1927 ****************************************************************************************************
1928 * CiLib::HwlComputeMetadataNibbleAddress
1931 * calculate meta data address based on input information
1934 * uncompressedDataByteAddress - address of a pixel in color surface
1935 * dataBaseByteAddress - base address of color surface
1936 * metadataBaseByteAddress - base address of meta ram
1937 * metadataBitSize - meta key size, 8 for DCC, 4 for cmask
1938 * elementBitSize - element size of color surface
1939 * blockByteSize - compression block size, 256 for DCC
1940 * pipeInterleaveBytes - pipe interleave size
1941 * numOfPipes - number of pipes
1942 * numOfBanks - number of banks
1943 * numOfSamplesPerSplit - number of samples per tile split
1945 * meta data nibble address (nibble address is used to support DCC compatible cmask)
1947 ****************************************************************************************************
1949 UINT_64
CiLib::HwlComputeMetadataNibbleAddress(
1950 UINT_64 uncompressedDataByteAddress
,
1951 UINT_64 dataBaseByteAddress
,
1952 UINT_64 metadataBaseByteAddress
,
1953 UINT_32 metadataBitSize
,
1954 UINT_32 elementBitSize
,
1955 UINT_32 blockByteSize
,
1956 UINT_32 pipeInterleaveBytes
,
1959 UINT_32 numOfSamplesPerSplit
) const
1961 ///--------------------------------------------------------------------------------------------
1962 /// Get pipe interleave, bank and pipe bits
1963 ///--------------------------------------------------------------------------------------------
1964 UINT_32 pipeInterleaveBits
= Log2(pipeInterleaveBytes
);
1965 UINT_32 pipeBits
= Log2(numOfPipes
);
1966 UINT_32 bankBits
= Log2(numOfBanks
);
1968 ///--------------------------------------------------------------------------------------------
1969 /// Clear pipe and bank swizzles
1970 ///--------------------------------------------------------------------------------------------
1971 UINT_32 dataMacrotileBits
= pipeInterleaveBits
+ pipeBits
+ bankBits
;
1972 UINT_32 metadataMacrotileBits
= pipeInterleaveBits
+ pipeBits
+ bankBits
;
1974 UINT_64 dataMacrotileClearMask
= ~((1L << dataMacrotileBits
) - 1);
1975 UINT_64 metadataMacrotileClearMask
= ~((1L << metadataMacrotileBits
) - 1);
1977 UINT_64 dataBaseByteAddressNoSwizzle
= dataBaseByteAddress
& dataMacrotileClearMask
;
1978 UINT_64 metadataBaseByteAddressNoSwizzle
= metadataBaseByteAddress
& metadataMacrotileClearMask
;
1980 ///--------------------------------------------------------------------------------------------
1981 /// Modify metadata base before adding in so that when final address is divided by data ratio,
1982 /// the base address returns to where it should be
1983 ///--------------------------------------------------------------------------------------------
1984 ADDR_ASSERT((0 != metadataBitSize
));
1985 UINT_64 metadataBaseShifted
= metadataBaseByteAddressNoSwizzle
* blockByteSize
* 8 /
1987 UINT_64 offset
= uncompressedDataByteAddress
-
1988 dataBaseByteAddressNoSwizzle
+
1989 metadataBaseShifted
;
1991 ///--------------------------------------------------------------------------------------------
1992 /// Save bank data bits
1993 ///--------------------------------------------------------------------------------------------
1994 UINT_32 lsb
= pipeBits
+ pipeInterleaveBits
;
1995 UINT_32 msb
= bankBits
- 1 + lsb
;
1997 UINT_64 bankDataBits
= GetBits(offset
, msb
, lsb
);
1999 ///--------------------------------------------------------------------------------------------
2000 /// Save pipe data bits
2001 ///--------------------------------------------------------------------------------------------
2002 lsb
= pipeInterleaveBits
;
2003 msb
= pipeBits
- 1 + lsb
;
2005 UINT_64 pipeDataBits
= GetBits(offset
, msb
, lsb
);
2007 ///--------------------------------------------------------------------------------------------
2008 /// Remove pipe and bank bits
2009 ///--------------------------------------------------------------------------------------------
2010 lsb
= pipeInterleaveBits
;
2011 msb
= dataMacrotileBits
- 1;
2013 UINT_64 offsetWithoutPipeBankBits
= RemoveBits(offset
, msb
, lsb
);
2015 ADDR_ASSERT((0 != blockByteSize
));
2016 UINT_64 blockInBankpipe
= offsetWithoutPipeBankBits
/ blockByteSize
;
2018 UINT_32 tileSize
= 8 * 8 * elementBitSize
/8 * numOfSamplesPerSplit
;
2019 UINT_32 blocksInTile
= tileSize
/ blockByteSize
;
2021 if (0 == blocksInTile
)
2027 lsb
= Log2(blocksInTile
);
2029 msb
= bankBits
- 1 + lsb
;
2031 UINT_64 blockInBankpipeWithBankBits
= InsertBits(blockInBankpipe
, bankDataBits
, msb
, lsb
);
2033 /// NOTE *2 because we are converting to Nibble address in this step
2034 UINT_64 metaAddressInPipe
= blockInBankpipeWithBankBits
* 2 * metadataBitSize
/ 8;
2037 ///--------------------------------------------------------------------------------------------
2038 /// Reinsert pipe bits back into the final address
2039 ///--------------------------------------------------------------------------------------------
2040 lsb
= pipeInterleaveBits
+ 1; ///<+1 due to Nibble address now gives interleave bits extra lsb.
2041 msb
= pipeBits
- 1 + lsb
;
2042 UINT_64 metadataAddress
= InsertBits(metaAddressInPipe
, pipeDataBits
, msb
, lsb
);
2044 return metadataAddress
;
2048 ****************************************************************************************************
2049 * CiLib::HwlComputeSurfaceAlignmentsMacroTiled
2052 * Hardware layer function to compute alignment request for macro tile mode
2054 ****************************************************************************************************
2056 VOID
CiLib::HwlComputeSurfaceAlignmentsMacroTiled(
2057 AddrTileMode tileMode
, ///< [in] tile mode
2058 UINT_32 bpp
, ///< [in] bits per pixel
2059 ADDR_SURFACE_FLAGS flags
, ///< [in] surface flags
2060 UINT_32 mipLevel
, ///< [in] mip level
2061 UINT_32 numSamples
, ///< [in] number of samples
2062 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
///< [in,out] Surface output
2065 // This is to workaround a H/W limitation that DCC doesn't work when pipe config is switched to
2066 // P4. In theory, all asics that have such switching should be patched but we now only know what
2068 if ((m_settings
.isFiji
== TRUE
) &&
2069 (flags
.dccPipeWorkaround
== TRUE
) &&
2070 (flags
.prt
== FALSE
) &&
2072 (tileMode
== ADDR_TM_PRT_TILED_THIN1
) &&
2073 (pOut
->dccUnsupport
== TRUE
))
2075 pOut
->pitchAlign
= PowTwoAlign(pOut
->pitchAlign
, 256);
2076 // In case the client still requests DCC usage.
2077 pOut
->dccUnsupport
= FALSE
;
2082 ****************************************************************************************************
2083 * CiLib::HwlPadDimensions
2086 * Helper function to pad dimensions
2088 ****************************************************************************************************
2090 VOID
CiLib::HwlPadDimensions(
2091 AddrTileMode tileMode
, ///< [in] tile mode
2092 UINT_32 bpp
, ///< [in] bits per pixel
2093 ADDR_SURFACE_FLAGS flags
, ///< [in] surface flags
2094 UINT_32 numSamples
, ///< [in] number of samples
2095 ADDR_TILEINFO
* pTileInfo
, ///< [in] tile info
2096 UINT_32 mipLevel
, ///< [in] mip level
2097 UINT_32
* pPitch
, ///< [in,out] pitch in pixels
2098 UINT_32
* pPitchAlign
, ///< [in,out] pitch alignment
2099 UINT_32 height
, ///< [in] height in pixels
2100 UINT_32 heightAlign
///< [in] height alignment
2103 if ((m_settings
.isVolcanicIslands
== TRUE
) &&
2104 (flags
.dccCompatible
== TRUE
) &&
2107 (IsMacroTiled(tileMode
) == TRUE
))
2109 UINT_32 tileSizePerSample
= BITS_TO_BYTES(bpp
* MicroTileWidth
* MicroTileHeight
);
2110 UINT_32 samplesPerSplit
= pTileInfo
->tileSplitBytes
/ tileSizePerSample
;
2112 if (samplesPerSplit
< numSamples
)
2114 UINT_32 dccFastClearByteAlign
= HwlGetPipes(pTileInfo
) * m_pipeInterleaveBytes
* 256;
2115 UINT_32 bytesPerSplit
= BITS_TO_BYTES((*pPitch
) * height
* bpp
* samplesPerSplit
);
2117 ADDR_ASSERT(IsPow2(dccFastClearByteAlign
));
2119 if (0 != (bytesPerSplit
& (dccFastClearByteAlign
- 1)))
2121 UINT_32 dccFastClearPixelAlign
= dccFastClearByteAlign
/
2122 BITS_TO_BYTES(bpp
) /
2124 UINT_32 macroTilePixelAlign
= (*pPitchAlign
) * heightAlign
;
2126 if ((dccFastClearPixelAlign
>= macroTilePixelAlign
) &&
2127 ((dccFastClearPixelAlign
% macroTilePixelAlign
) == 0))
2129 UINT_32 dccFastClearPitchAlignInMacroTile
=
2130 dccFastClearPixelAlign
/ macroTilePixelAlign
;
2131 UINT_32 heightInMacroTile
= height
/ heightAlign
;
2133 while ((heightInMacroTile
> 1) &&
2134 ((heightInMacroTile
% 2) == 0) &&
2135 (dccFastClearPitchAlignInMacroTile
> 1) &&
2136 ((dccFastClearPitchAlignInMacroTile
% 2) == 0))
2138 heightInMacroTile
>>= 1;
2139 dccFastClearPitchAlignInMacroTile
>>= 1;
2142 UINT_32 dccFastClearPitchAlignInPixels
=
2143 (*pPitchAlign
) * dccFastClearPitchAlignInMacroTile
;
2145 if (IsPow2(dccFastClearPitchAlignInPixels
))
2147 *pPitch
= PowTwoAlign((*pPitch
), dccFastClearPitchAlignInPixels
);
2151 *pPitch
+= (dccFastClearPitchAlignInPixels
- 1);
2152 *pPitch
/= dccFastClearPitchAlignInPixels
;
2153 *pPitch
*= dccFastClearPitchAlignInPixels
;
2156 *pPitchAlign
= dccFastClearPitchAlignInPixels
;
2164 ****************************************************************************************************
2165 * CiLib::HwlComputeMaxBaseAlignments
2168 * Gets maximum alignments
2170 * maximum alignments
2171 ****************************************************************************************************
2173 UINT_32
CiLib::HwlComputeMaxBaseAlignments() const
2175 const UINT_32 pipes
= HwlGetPipes(&m_tileTable
[0].info
);
2177 // Initial size is 64 KiB for PRT.
2178 UINT_32 maxBaseAlign
= 64 * 1024;
2180 for (UINT_32 i
= 0; i
< m_noOfMacroEntries
; i
++)
2182 // The maximum tile size is 16 byte-per-pixel and either 8-sample or 8-slice.
2183 UINT_32 tileSize
= m_macroTileTable
[i
].tileSplitBytes
;
2185 UINT_32 baseAlign
= tileSize
* pipes
* m_macroTileTable
[i
].banks
*
2186 m_macroTileTable
[i
].bankWidth
* m_macroTileTable
[i
].bankHeight
;
2188 if (baseAlign
> maxBaseAlign
)
2190 maxBaseAlign
= baseAlign
;
2194 return maxBaseAlign
;
2198 ****************************************************************************************************
2199 * CiLib::HwlComputeMaxMetaBaseAlignments
2202 * Gets maximum alignments for metadata
2204 * maximum alignments for metadata
2205 ****************************************************************************************************
2207 UINT_32
CiLib::HwlComputeMaxMetaBaseAlignments() const
2209 UINT_32 maxBank
= 1;
2211 for (UINT_32 i
= 0; i
< m_noOfMacroEntries
; i
++)
2213 if ((m_settings
.isVolcanicIslands
) && IsMacroTiled(m_tileTable
[i
].mode
))
2215 maxBank
= Max(maxBank
, m_macroTileTable
[i
].banks
);
2219 return SiLib::HwlComputeMaxMetaBaseAlignments() * maxBank
;
2223 ****************************************************************************************************
2224 * CiLib::DepthStencilTileCfgMatch
2227 * Try to find a tile index for stencil which makes its tile config parameters matches to depth
2229 * TRUE if such tile index for stencil can be found
2230 ****************************************************************************************************
2232 BOOL_32
CiLib::DepthStencilTileCfgMatch(
2233 const ADDR_COMPUTE_SURFACE_INFO_INPUT
* pIn
, ///< [in] input structure
2234 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
///< [out] output structure
2237 BOOL_32 depthStencil2DTileConfigMatch
= FALSE
;
2239 for (INT_32 stencilTileIndex
= MinDepth2DThinIndex
;
2240 stencilTileIndex
<= MaxDepth2DThinIndex
;
2243 ADDR_TILEINFO tileInfo
= {0};
2244 INT_32 stencilMacroIndex
= HwlComputeMacroModeIndex(stencilTileIndex
,
2250 if (stencilMacroIndex
!= TileIndexNoMacroIndex
)
2252 if ((m_macroTileTable
[stencilMacroIndex
].banks
==
2253 m_macroTileTable
[pOut
->macroModeIndex
].banks
) &&
2254 (m_macroTileTable
[stencilMacroIndex
].bankWidth
==
2255 m_macroTileTable
[pOut
->macroModeIndex
].bankWidth
) &&
2256 (m_macroTileTable
[stencilMacroIndex
].bankHeight
==
2257 m_macroTileTable
[pOut
->macroModeIndex
].bankHeight
) &&
2258 (m_macroTileTable
[stencilMacroIndex
].macroAspectRatio
==
2259 m_macroTileTable
[pOut
->macroModeIndex
].macroAspectRatio
) &&
2260 (m_macroTileTable
[stencilMacroIndex
].pipeConfig
==
2261 m_macroTileTable
[pOut
->macroModeIndex
].pipeConfig
))
2263 if ((pOut
->tcCompatible
== FALSE
) ||
2264 (tileInfo
.tileSplitBytes
>= MicroTileWidth
* MicroTileHeight
* pIn
->numSamples
))
2266 depthStencil2DTileConfigMatch
= TRUE
;
2267 pOut
->stencilTileIdx
= stencilTileIndex
;
2274 ADDR_ASSERT_ALWAYS();
2278 return depthStencil2DTileConfigMatch
;
2282 ****************************************************************************************************
2283 * CiLib::DepthStencilTileCfgMatch
2286 * Check if tc compatibility is available
2288 * If tc compatibility is not available
2289 ****************************************************************************************************
2291 BOOL_32
CiLib::CheckTcCompatibility(
2292 const ADDR_TILEINFO
* pTileInfo
, ///< [in] input tile info
2293 UINT_32 bpp
, ///< [in] Bits per pixel
2294 AddrTileMode tileMode
, ///< [in] input tile mode
2295 AddrTileType tileType
, ///< [in] input tile type
2296 const ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
///< [in] output surf info
2299 BOOL_32 tcCompatible
= TRUE
;
2301 if (IsMacroTiled(tileMode
))
2303 if (tileType
!= ADDR_DEPTH_SAMPLE_ORDER
)
2305 // Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil
2306 // tileSplit case was handled at tileIndex selecting time.
2307 INT_32 tileIndex
= pOut
->tileIndex
;
2309 if ((tileIndex
== TileIndexInvalid
) && (IsTileInfoAllZero(pTileInfo
) == FALSE
))
2311 tileIndex
= HwlPostCheckTileIndex(pTileInfo
, tileMode
, tileType
, tileIndex
);
2314 if (tileIndex
!= TileIndexInvalid
)
2316 UINT_32 thickness
= Thickness(tileMode
);
2318 ADDR_ASSERT(static_cast<UINT_32
>(tileIndex
) < TileTableSize
);
2319 // Non-depth entries store a split factor
2320 UINT_32 sampleSplit
= m_tileTable
[tileIndex
].info
.tileSplitBytes
;
2321 UINT_32 tileBytes1x
= BITS_TO_BYTES(bpp
* MicroTilePixels
* thickness
);
2322 UINT_32 colorTileSplit
= Max(256u, sampleSplit
* tileBytes1x
);
2324 if (m_rowSize
< colorTileSplit
)
2326 tcCompatible
= FALSE
;
2333 // Client should not enable tc compatible for linear and 1D tile modes.
2334 tcCompatible
= FALSE
;
2337 return tcCompatible
;