2 * Copyright © 2014 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
28 ****************************************************************************************************
30 * @brief Contains the implementation for the SiLib class.
31 ****************************************************************************************************
34 #include "siaddrlib.h"
35 #include "si_gb_reg.h"
37 #include "amdgpu_asic_addr.h"
39 ////////////////////////////////////////////////////////////////////////////////////////////////////
40 ////////////////////////////////////////////////////////////////////////////////////////////////////
45 ****************************************************************************************************
49 * Creates an SiLib object.
52 * Returns an SiLib object pointer.
53 ****************************************************************************************************
55 Lib
* SiHwlInit(const Client
* pClient
)
57 return V1::SiLib::CreateObj(pClient
);
63 // We don't support MSAA for equation
64 const BOOL_32
SiLib::m_EquationSupport
[SiLib::TileTableSize
][SiLib::MaxNumElementBytes
] =
66 {TRUE
, TRUE
, TRUE
, FALSE
, FALSE
}, // 0, non-AA compressed depth or any stencil
67 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 1, 2xAA/4xAA compressed depth with or without stencil
68 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 2, 8xAA compressed depth with or without stencil
69 {FALSE
, TRUE
, FALSE
, FALSE
, FALSE
}, // 3, 16 bpp depth PRT (non-MSAA), don't support uncompressed depth
70 {TRUE
, TRUE
, TRUE
, FALSE
, FALSE
}, // 4, 1D depth
71 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 5, 16 bpp depth PRT (4xMSAA)
72 {FALSE
, FALSE
, TRUE
, FALSE
, FALSE
}, // 6, 32 bpp depth PRT (non-MSAA)
73 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 7, 32 bpp depth PRT (4xMSAA)
74 {TRUE
, TRUE
, TRUE
, TRUE
, TRUE
}, // 8, Linear
75 {TRUE
, TRUE
, TRUE
, TRUE
, TRUE
}, // 9, 1D display
76 {TRUE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 10, 8 bpp color (displayable)
77 {FALSE
, TRUE
, FALSE
, FALSE
, FALSE
}, // 11, 16 bpp color (displayable)
78 {FALSE
, FALSE
, TRUE
, TRUE
, FALSE
}, // 12, 32/64 bpp color (displayable)
79 {TRUE
, TRUE
, TRUE
, TRUE
, TRUE
}, // 13, 1D thin
80 {TRUE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 14, 8 bpp color non-displayable
81 {FALSE
, TRUE
, FALSE
, FALSE
, FALSE
}, // 15, 16 bpp color non-displayable
82 {FALSE
, FALSE
, TRUE
, FALSE
, FALSE
}, // 16, 32 bpp color non-displayable
83 {FALSE
, FALSE
, FALSE
, TRUE
, TRUE
}, // 17, 64/128 bpp color non-displayable
84 {TRUE
, TRUE
, TRUE
, TRUE
, TRUE
}, // 18, 1D THICK
85 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 19, 2D XTHICK
86 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 20, 2D THICK
87 {TRUE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 21, 8 bpp 2D PRTs (non-MSAA)
88 {FALSE
, TRUE
, FALSE
, FALSE
, FALSE
}, // 22, 16 bpp 2D PRTs (non-MSAA)
89 {FALSE
, FALSE
, TRUE
, FALSE
, FALSE
}, // 23, 32 bpp 2D PRTs (non-MSAA)
90 {FALSE
, FALSE
, FALSE
, TRUE
, FALSE
}, // 24, 64 bpp 2D PRTs (non-MSAA)
91 {FALSE
, FALSE
, FALSE
, FALSE
, TRUE
}, // 25, 128bpp 2D PRTs (non-MSAA)
92 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 26, none
93 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 27, none
94 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 28, none
95 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 29, none
96 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 30, 64bpp 2D PRTs (4xMSAA)
97 {FALSE
, FALSE
, FALSE
, FALSE
, FALSE
}, // 31, none
101 ****************************************************************************************************
107 ****************************************************************************************************
109 SiLib::SiLib(const Client
* pClient
)
115 m_class
= SI_ADDRLIB
;
116 memset(&m_settings
, 0, sizeof(m_settings
));
120 ****************************************************************************************************
125 ****************************************************************************************************
132 ****************************************************************************************************
139 ****************************************************************************************************
141 UINT_32
SiLib::HwlGetPipes(
142 const ADDR_TILEINFO
* pTileInfo
///< [in] Tile info
149 numPipes
= GetPipePerSurf(pTileInfo
->pipeConfig
);
153 ADDR_ASSERT_ALWAYS();
154 numPipes
= m_pipes
; // Suppose we should still have a global pipes
161 ****************************************************************************************************
162 * SiLib::GetPipePerSurf
164 * get pipe num base on inputing tileinfo->pipeconfig
167 ****************************************************************************************************
169 UINT_32
SiLib::GetPipePerSurf(
170 AddrPipeCfg pipeConfig
///< [in] pipe config
173 UINT_32 numPipes
= 0;
177 case ADDR_PIPECFG_P2
:
180 case ADDR_PIPECFG_P4_8x16
:
181 case ADDR_PIPECFG_P4_16x16
:
182 case ADDR_PIPECFG_P4_16x32
:
183 case ADDR_PIPECFG_P4_32x32
:
186 case ADDR_PIPECFG_P8_16x16_8x16
:
187 case ADDR_PIPECFG_P8_16x32_8x16
:
188 case ADDR_PIPECFG_P8_32x32_8x16
:
189 case ADDR_PIPECFG_P8_16x32_16x16
:
190 case ADDR_PIPECFG_P8_32x32_16x16
:
191 case ADDR_PIPECFG_P8_32x32_16x32
:
192 case ADDR_PIPECFG_P8_32x64_32x32
:
195 case ADDR_PIPECFG_P16_32x32_8x16
:
196 case ADDR_PIPECFG_P16_32x32_16x16
:
200 ADDR_ASSERT(!"Invalid pipe config");
207 ****************************************************************************************************
208 * SiLib::ComputeBankEquation
211 * Compute bank equation
214 * If equation can be computed
215 ****************************************************************************************************
217 ADDR_E_RETURNCODE
SiLib::ComputeBankEquation(
218 UINT_32 log2BytesPP
, ///< [in] log2 of bytes per pixel
219 UINT_32 threshX
, ///< [in] threshold for x channel
220 UINT_32 threshY
, ///< [in] threshold for y channel
221 ADDR_TILEINFO
* pTileInfo
, ///< [in] tile info
222 ADDR_EQUATION
* pEquation
///< [out] bank equation
225 ADDR_E_RETURNCODE retCode
= ADDR_OK
;
227 UINT_32 pipes
= HwlGetPipes(pTileInfo
);
228 UINT_32 bankXStart
= 3 + Log2(pipes
) + Log2(pTileInfo
->bankWidth
);
229 UINT_32 bankYStart
= 3 + Log2(pTileInfo
->bankHeight
);
231 ADDR_CHANNEL_SETTING x3
= InitChannel(1, 0, log2BytesPP
+ bankXStart
);
232 ADDR_CHANNEL_SETTING x4
= InitChannel(1, 0, log2BytesPP
+ bankXStart
+ 1);
233 ADDR_CHANNEL_SETTING x5
= InitChannel(1, 0, log2BytesPP
+ bankXStart
+ 2);
234 ADDR_CHANNEL_SETTING x6
= InitChannel(1, 0, log2BytesPP
+ bankXStart
+ 3);
235 ADDR_CHANNEL_SETTING y3
= InitChannel(1, 1, bankYStart
);
236 ADDR_CHANNEL_SETTING y4
= InitChannel(1, 1, bankYStart
+ 1);
237 ADDR_CHANNEL_SETTING y5
= InitChannel(1, 1, bankYStart
+ 2);
238 ADDR_CHANNEL_SETTING y6
= InitChannel(1, 1, bankYStart
+ 3);
240 x3
.value
= (threshX
> bankXStart
) ? x3
.value
: 0;
241 x4
.value
= (threshX
> bankXStart
+ 1) ? x4
.value
: 0;
242 x5
.value
= (threshX
> bankXStart
+ 2) ? x5
.value
: 0;
243 x6
.value
= (threshX
> bankXStart
+ 3) ? x6
.value
: 0;
244 y3
.value
= (threshY
> bankYStart
) ? y3
.value
: 0;
245 y4
.value
= (threshY
> bankYStart
+ 1) ? y4
.value
: 0;
246 y5
.value
= (threshY
> bankYStart
+ 2) ? y5
.value
: 0;
247 y6
.value
= (threshY
> bankYStart
+ 3) ? y6
.value
: 0;
249 switch (pTileInfo
->banks
)
252 if (pTileInfo
->macroAspectRatio
== 1)
254 pEquation
->addr
[0] = y6
;
255 pEquation
->xor1
[0] = x3
;
256 pEquation
->addr
[1] = y5
;
257 pEquation
->xor1
[1] = y6
;
258 pEquation
->xor2
[1] = x4
;
259 pEquation
->addr
[2] = y4
;
260 pEquation
->xor1
[2] = x5
;
261 pEquation
->addr
[3] = y3
;
262 pEquation
->xor1
[3] = x6
;
264 else if (pTileInfo
->macroAspectRatio
== 2)
266 pEquation
->addr
[0] = x3
;
267 pEquation
->xor1
[0] = y6
;
268 pEquation
->addr
[1] = y5
;
269 pEquation
->xor1
[1] = y6
;
270 pEquation
->xor2
[1] = x4
;
271 pEquation
->addr
[2] = y4
;
272 pEquation
->xor1
[2] = x5
;
273 pEquation
->addr
[3] = y3
;
274 pEquation
->xor1
[3] = x6
;
276 else if (pTileInfo
->macroAspectRatio
== 4)
278 pEquation
->addr
[0] = x3
;
279 pEquation
->xor1
[0] = y6
;
280 pEquation
->addr
[1] = x4
;
281 pEquation
->xor1
[1] = y5
;
282 pEquation
->xor2
[1] = y6
;
283 pEquation
->addr
[2] = y4
;
284 pEquation
->xor1
[2] = x5
;
285 pEquation
->addr
[3] = y3
;
286 pEquation
->xor1
[3] = x6
;
288 else if (pTileInfo
->macroAspectRatio
== 8)
290 pEquation
->addr
[0] = x3
;
291 pEquation
->xor1
[0] = y6
;
292 pEquation
->addr
[1] = x4
;
293 pEquation
->xor1
[1] = y5
;
294 pEquation
->xor2
[1] = y6
;
295 pEquation
->addr
[2] = x5
;
296 pEquation
->xor1
[2] = y4
;
297 pEquation
->addr
[3] = y3
;
298 pEquation
->xor1
[3] = x6
;
302 ADDR_ASSERT_ALWAYS();
304 pEquation
->numBits
= 4;
307 if (pTileInfo
->macroAspectRatio
== 1)
309 pEquation
->addr
[0] = y5
;
310 pEquation
->xor1
[0] = x3
;
311 pEquation
->addr
[1] = y4
;
312 pEquation
->xor1
[1] = y5
;
313 pEquation
->xor2
[1] = x4
;
314 pEquation
->addr
[2] = y3
;
315 pEquation
->xor1
[2] = x5
;
317 else if (pTileInfo
->macroAspectRatio
== 2)
319 pEquation
->addr
[0] = x3
;
320 pEquation
->xor1
[0] = y5
;
321 pEquation
->addr
[1] = y4
;
322 pEquation
->xor1
[1] = y5
;
323 pEquation
->xor2
[1] = x4
;
324 pEquation
->addr
[2] = y3
;
325 pEquation
->xor1
[2] = x5
;
327 else if (pTileInfo
->macroAspectRatio
== 4)
329 pEquation
->addr
[0] = x3
;
330 pEquation
->xor1
[0] = y5
;
331 pEquation
->addr
[1] = x4
;
332 pEquation
->xor1
[1] = y4
;
333 pEquation
->xor2
[1] = y5
;
334 pEquation
->addr
[2] = y3
;
335 pEquation
->xor1
[2] = x5
;
339 ADDR_ASSERT_ALWAYS();
341 pEquation
->numBits
= 3;
344 if (pTileInfo
->macroAspectRatio
== 1)
346 pEquation
->addr
[0] = y4
;
347 pEquation
->xor1
[0] = x3
;
348 pEquation
->addr
[1] = y3
;
349 pEquation
->xor1
[1] = x4
;
351 else if (pTileInfo
->macroAspectRatio
== 2)
353 pEquation
->addr
[0] = x3
;
354 pEquation
->xor1
[0] = y4
;
355 pEquation
->addr
[1] = y3
;
356 pEquation
->xor1
[1] = x4
;
360 pEquation
->addr
[0] = x3
;
361 pEquation
->xor1
[0] = y4
;
362 pEquation
->addr
[1] = x4
;
363 pEquation
->xor1
[1] = y3
;
365 pEquation
->numBits
= 2;
368 if (pTileInfo
->macroAspectRatio
== 1)
370 pEquation
->addr
[0] = y3
;
371 pEquation
->xor1
[0] = x3
;
375 pEquation
->addr
[0] = x3
;
376 pEquation
->xor1
[0] = y3
;
378 pEquation
->numBits
= 1;
381 pEquation
->numBits
= 0;
382 retCode
= ADDR_NOTSUPPORTED
;
383 ADDR_ASSERT_ALWAYS();
387 for (UINT_32 i
= 0; i
< pEquation
->numBits
; i
++)
389 if (pEquation
->addr
[i
].value
== 0)
391 if (pEquation
->xor1
[i
].value
== 0)
394 pEquation
->addr
[i
].value
= pEquation
->xor2
[i
].value
;
395 pEquation
->xor2
[i
].value
= 0;
399 pEquation
->addr
[i
].value
= pEquation
->xor1
[i
].value
;
401 if (pEquation
->xor2
[i
].value
!= 0)
404 pEquation
->xor1
[i
].value
= pEquation
->xor2
[i
].value
;
405 pEquation
->xor2
[i
].value
= 0;
410 pEquation
->xor1
[i
].value
= 0;
414 else if (pEquation
->xor1
[i
].value
== 0)
416 if (pEquation
->xor2
[i
].value
!= 0)
419 pEquation
->xor1
[i
].value
= pEquation
->xor2
[i
].value
;
420 pEquation
->xor2
[i
].value
= 0;
425 if ((pTileInfo
->bankWidth
== 1) &&
426 ((pTileInfo
->pipeConfig
== ADDR_PIPECFG_P4_32x32
) ||
427 (pTileInfo
->pipeConfig
== ADDR_PIPECFG_P8_32x64_32x32
)))
429 retCode
= ADDR_NOTSUPPORTED
;
436 ****************************************************************************************************
437 * SiLib::ComputePipeEquation
440 * Compute pipe equation
443 * If equation can be computed
444 ****************************************************************************************************
446 ADDR_E_RETURNCODE
SiLib::ComputePipeEquation(
447 UINT_32 log2BytesPP
, ///< [in] Log2 of bytes per pixel
448 UINT_32 threshX
, ///< [in] Threshold for X channel
449 UINT_32 threshY
, ///< [in] Threshold for Y channel
450 ADDR_TILEINFO
* pTileInfo
, ///< [in] Tile info
451 ADDR_EQUATION
* pEquation
///< [out] Pipe configure
454 ADDR_E_RETURNCODE retCode
= ADDR_OK
;
456 ADDR_CHANNEL_SETTING
* pAddr
= pEquation
->addr
;
457 ADDR_CHANNEL_SETTING
* pXor1
= pEquation
->xor1
;
458 ADDR_CHANNEL_SETTING
* pXor2
= pEquation
->xor2
;
460 ADDR_CHANNEL_SETTING x3
= InitChannel(1, 0, 3 + log2BytesPP
);
461 ADDR_CHANNEL_SETTING x4
= InitChannel(1, 0, 4 + log2BytesPP
);
462 ADDR_CHANNEL_SETTING x5
= InitChannel(1, 0, 5 + log2BytesPP
);
463 ADDR_CHANNEL_SETTING x6
= InitChannel(1, 0, 6 + log2BytesPP
);
464 ADDR_CHANNEL_SETTING y3
= InitChannel(1, 1, 3);
465 ADDR_CHANNEL_SETTING y4
= InitChannel(1, 1, 4);
466 ADDR_CHANNEL_SETTING y5
= InitChannel(1, 1, 5);
467 ADDR_CHANNEL_SETTING y6
= InitChannel(1, 1, 6);
469 x3
.value
= (threshX
> 3) ? x3
.value
: 0;
470 x4
.value
= (threshX
> 4) ? x4
.value
: 0;
471 x5
.value
= (threshX
> 5) ? x5
.value
: 0;
472 x6
.value
= (threshX
> 6) ? x6
.value
: 0;
473 y3
.value
= (threshY
> 3) ? y3
.value
: 0;
474 y4
.value
= (threshY
> 4) ? y4
.value
: 0;
475 y5
.value
= (threshY
> 5) ? y5
.value
: 0;
476 y6
.value
= (threshY
> 6) ? y6
.value
: 0;
478 switch (pTileInfo
->pipeConfig
)
480 case ADDR_PIPECFG_P2
:
483 pEquation
->numBits
= 1;
485 case ADDR_PIPECFG_P4_8x16
:
490 pEquation
->numBits
= 2;
492 case ADDR_PIPECFG_P4_16x16
:
498 pEquation
->numBits
= 2;
500 case ADDR_PIPECFG_P4_16x32
:
506 pEquation
->numBits
= 2;
508 case ADDR_PIPECFG_P4_32x32
:
514 pEquation
->numBits
= 2;
516 case ADDR_PIPECFG_P8_16x16_8x16
:
522 pEquation
->numBits
= 3;
524 case ADDR_PIPECFG_P8_16x32_8x16
:
532 pEquation
->numBits
= 3;
534 case ADDR_PIPECFG_P8_16x32_16x16
:
542 pEquation
->numBits
= 3;
544 case ADDR_PIPECFG_P8_32x32_8x16
:
552 pEquation
->numBits
= 3;
554 case ADDR_PIPECFG_P8_32x32_16x16
:
562 pEquation
->numBits
= 3;
564 case ADDR_PIPECFG_P8_32x32_16x32
:
572 pEquation
->numBits
= 3;
574 case ADDR_PIPECFG_P8_32x64_32x32
:
582 pEquation
->numBits
= 3;
584 case ADDR_PIPECFG_P16_32x32_8x16
:
593 pEquation
->numBits
= 4;
595 case ADDR_PIPECFG_P16_32x32_16x16
:
605 pEquation
->numBits
= 4;
608 ADDR_UNHANDLED_CASE();
609 pEquation
->numBits
= 0;
610 retCode
= ADDR_NOTSUPPORTED
;
614 for (UINT_32 i
= 0; i
< pEquation
->numBits
; i
++)
616 if (pAddr
[i
].value
== 0)
618 if (pXor1
[i
].value
== 0)
620 pAddr
[i
].value
= pXor2
[i
].value
;
624 pAddr
[i
].value
= pXor1
[i
].value
;
634 ****************************************************************************************************
635 * SiLib::ComputePipeFromCoord
638 * Compute pipe number from coordinates
641 ****************************************************************************************************
643 UINT_32
SiLib::ComputePipeFromCoord(
644 UINT_32 x
, ///< [in] x coordinate
645 UINT_32 y
, ///< [in] y coordinate
646 UINT_32 slice
, ///< [in] slice index
647 AddrTileMode tileMode
, ///< [in] tile mode
648 UINT_32 pipeSwizzle
, ///< [in] pipe swizzle
649 BOOL_32 ignoreSE
, ///< [in] TRUE if shader engines are ignored
650 ADDR_TILEINFO
* pTileInfo
///< [in] Tile info
654 UINT_32 pipeBit0
= 0;
655 UINT_32 pipeBit1
= 0;
656 UINT_32 pipeBit2
= 0;
657 UINT_32 pipeBit3
= 0;
658 UINT_32 sliceRotation
;
659 UINT_32 numPipes
= 0;
661 UINT_32 tx
= x
/ MicroTileWidth
;
662 UINT_32 ty
= y
/ MicroTileHeight
;
663 UINT_32 x3
= _BIT(tx
,0);
664 UINT_32 x4
= _BIT(tx
,1);
665 UINT_32 x5
= _BIT(tx
,2);
666 UINT_32 x6
= _BIT(tx
,3);
667 UINT_32 y3
= _BIT(ty
,0);
668 UINT_32 y4
= _BIT(ty
,1);
669 UINT_32 y5
= _BIT(ty
,2);
670 UINT_32 y6
= _BIT(ty
,3);
672 switch (pTileInfo
->pipeConfig
)
674 case ADDR_PIPECFG_P2
:
678 case ADDR_PIPECFG_P4_8x16
:
683 case ADDR_PIPECFG_P4_16x16
:
684 pipeBit0
= x3
^ y3
^ x4
;
688 case ADDR_PIPECFG_P4_16x32
:
689 pipeBit0
= x3
^ y3
^ x4
;
693 case ADDR_PIPECFG_P4_32x32
:
694 pipeBit0
= x3
^ y3
^ x5
;
698 case ADDR_PIPECFG_P8_16x16_8x16
:
699 pipeBit0
= x4
^ y3
^ x5
;
703 case ADDR_PIPECFG_P8_16x32_8x16
:
704 pipeBit0
= x4
^ y3
^ x5
;
709 case ADDR_PIPECFG_P8_16x32_16x16
:
710 pipeBit0
= x3
^ y3
^ x4
;
715 case ADDR_PIPECFG_P8_32x32_8x16
:
716 pipeBit0
= x4
^ y3
^ x5
;
721 case ADDR_PIPECFG_P8_32x32_16x16
:
722 pipeBit0
= x3
^ y3
^ x4
;
727 case ADDR_PIPECFG_P8_32x32_16x32
:
728 pipeBit0
= x3
^ y3
^ x4
;
733 case ADDR_PIPECFG_P8_32x64_32x32
:
734 pipeBit0
= x3
^ y3
^ x5
;
739 case ADDR_PIPECFG_P16_32x32_8x16
:
746 case ADDR_PIPECFG_P16_32x32_16x16
:
747 pipeBit0
= x3
^ y3
^ x4
;
754 ADDR_UNHANDLED_CASE();
757 pipe
= pipeBit0
| (pipeBit1
<< 1) | (pipeBit2
<< 2) | (pipeBit3
<< 3);
759 UINT_32 microTileThickness
= Thickness(tileMode
);
762 // Apply pipe rotation for the slice.
766 case ADDR_TM_3D_TILED_THIN1
: //fall through thin
767 case ADDR_TM_3D_TILED_THICK
: //fall through thick
768 case ADDR_TM_3D_TILED_XTHICK
:
770 Max(1, static_cast<INT_32
>(numPipes
/ 2) - 1) * (slice
/ microTileThickness
);
776 pipeSwizzle
+= sliceRotation
;
777 pipeSwizzle
&= (numPipes
- 1);
779 pipe
= pipe
^ pipeSwizzle
;
785 ****************************************************************************************************
786 * SiLib::ComputeTileCoordFromPipeAndElemIdx
789 * Compute (x,y) of a tile within a macro tile from address
792 ****************************************************************************************************
794 VOID
SiLib::ComputeTileCoordFromPipeAndElemIdx(
795 UINT_32 elemIdx
, ///< [in] per pipe element index within a macro tile
796 UINT_32 pipe
, ///< [in] pipe index
797 AddrPipeCfg pipeCfg
, ///< [in] pipe config
798 UINT_32 pitchInMacroTile
, ///< [in] surface pitch in macro tile
799 UINT_32 x
, ///< [in] x coordinate of the (0,0) tile in a macro tile
800 UINT_32 y
, ///< [in] y coordinate of the (0,0) tile in a macro tile
801 UINT_32
* pX
, ///< [out] x coordinate
802 UINT_32
* pY
///< [out] y coordinate
805 UINT_32 pipebit0
= _BIT(pipe
,0);
806 UINT_32 pipebit1
= _BIT(pipe
,1);
807 UINT_32 pipebit2
= _BIT(pipe
,2);
808 UINT_32 pipebit3
= _BIT(pipe
,3);
809 UINT_32 elemIdx0
= _BIT(elemIdx
,0);
810 UINT_32 elemIdx1
= _BIT(elemIdx
,1);
811 UINT_32 elemIdx2
= _BIT(elemIdx
,2);
823 case ADDR_PIPECFG_P2
:
828 *pY
= Bits2Number(2, y4
, y3
);
829 *pX
= Bits2Number(2, x4
, x3
);
831 case ADDR_PIPECFG_P4_8x16
:
836 *pY
= Bits2Number(2, y4
, y3
);
837 *pX
= Bits2Number(2, x4
, x3
);
839 case ADDR_PIPECFG_P4_16x16
:
843 x3
= pipebit0
^ y3
^ x4
;
844 *pY
= Bits2Number(2, y4
, y3
);
845 *pX
= Bits2Number(2, x4
, x3
);
847 case ADDR_PIPECFG_P4_16x32
:
848 x3
= elemIdx0
^ pipebit0
;
851 y3
= pipebit0
^ x3
^ x4
;
853 *pY
= Bits2Number(2, y4
, y3
);
854 *pX
= Bits2Number(2, x4
, x3
);
856 case ADDR_PIPECFG_P4_32x32
:
860 if((pitchInMacroTile
% 2) == 0)
864 x3
= pipebit0
^ y3
^ x5
;
865 *pY
= Bits2Number(2, y4
, y3
);
866 *pX
= Bits2Number(3, x5
, x4
, x3
);
871 x3
= pipebit0
^ y3
^ x5
;
872 *pY
= Bits2Number(2, y4
, y3
);
873 *pX
= Bits2Number(2, x4
, x3
);
876 case ADDR_PIPECFG_P8_16x16_8x16
:
882 y3
= pipebit0
^ x5
^ x4
;
883 *pY
= Bits2Number(2, y4
, y3
);
884 *pX
= Bits2Number(2, x4
, x3
);
886 case ADDR_PIPECFG_P8_16x32_8x16
:
892 y3
= pipebit0
^ x4
^ x5
;
893 *pY
= Bits2Number(2, y4
, y3
);
894 *pX
= Bits2Number(2, x4
, x3
);
896 case ADDR_PIPECFG_P8_32x32_8x16
:
900 if((pitchInMacroTile
% 2) == 0)
905 y3
= pipebit0
^ x4
^ x5
;
906 *pY
= Bits2Number(2, y4
, y3
);
907 *pX
= Bits2Number(3, x5
, x4
, x3
);
912 y3
= pipebit0
^ x4
^ x5
;
913 *pY
= Bits2Number(2, y4
, y3
);
914 *pX
= Bits2Number(2, x4
, x3
);
917 case ADDR_PIPECFG_P8_16x32_16x16
:
923 y3
= pipebit0
^ x3
^ x4
;
924 *pY
= Bits2Number(2, y4
, y3
);
925 *pX
= Bits2Number(2, x4
, x3
);
927 case ADDR_PIPECFG_P8_32x32_16x16
:
932 if((pitchInMacroTile
% 2) == 0)
936 *pY
= Bits2Number(2, y4
, y3
);
937 *pX
= Bits2Number(3, x5
, x4
, x3
);
941 *pY
= Bits2Number(2, y4
, y3
);
942 *pX
= Bits2Number(2, x4
, x3
);
945 case ADDR_PIPECFG_P8_32x32_16x32
:
946 if((pitchInMacroTile
% 2) == 0)
953 x3
= pipebit0
^ y3
^ x4
;
955 *pY
= Bits2Number(2, y4
, y3
);
956 *pX
= Bits2Number(3, x5
, x4
, x3
);
964 x3
= pipebit0
^ y3
^ x4
;
965 *pY
= Bits2Number(2, y4
, y3
);
966 *pX
= Bits2Number(2, x4
, x3
);
969 case ADDR_PIPECFG_P8_32x64_32x32
:
973 if((pitchInMacroTile
% 4) == 0)
979 x3
= pipebit0
^ y3
^ x5
;
980 *pY
= Bits2Number(2, y4
, y3
);
981 *pX
= Bits2Number(4, x6
, x5
, x4
, x3
);
987 x3
= pipebit0
^ y3
^ x5
;
988 *pY
= Bits2Number(2, y4
, y3
);
989 *pX
= Bits2Number(3, x5
, x4
, x3
);
992 case ADDR_PIPECFG_P16_32x32_8x16
:
997 if((pitchInMacroTile
% 4) == 0)
1003 *pY
= Bits2Number(2, y4
, y3
);
1004 *pX
= Bits2Number(4, x6
, x5
,x4
, x3
);
1010 *pY
= Bits2Number(2, y4
, y3
);
1011 *pX
= Bits2Number(3, x5
, x4
, x3
);
1014 case ADDR_PIPECFG_P16_32x32_16x16
:
1018 x3
= pipebit0
^ y3
^ x4
;
1019 if((pitchInMacroTile
% 4) == 0)
1025 *pY
= Bits2Number(2, y4
, y3
);
1026 *pX
= Bits2Number(4, x6
, x5
, x4
, x3
);
1032 *pY
= Bits2Number(2, y4
, y3
);
1033 *pX
= Bits2Number(3, x5
, x4
, x3
);
1037 ADDR_UNHANDLED_CASE();
1042 ****************************************************************************************************
1043 * SiLib::TileCoordToMaskElementIndex
1046 * Compute element index from coordinates in tiles
1049 ****************************************************************************************************
1051 UINT_32
SiLib::TileCoordToMaskElementIndex(
1052 UINT_32 tx
, ///< [in] x coord, in Tiles
1053 UINT_32 ty
, ///< [in] y coord, in Tiles
1054 AddrPipeCfg pipeConfig
, ///< [in] pipe config
1055 UINT_32
* macroShift
, ///< [out] macro shift
1056 UINT_32
* elemIdxBits
///< [out] tile offset bits
1059 UINT_32 elemIdx
= 0;
1060 UINT_32 elemIdx0
, elemIdx1
, elemIdx2
;
1071 case ADDR_PIPECFG_P2
:
1075 elemIdx1
= tx1
^ ty1
;
1076 elemIdx0
= tx1
^ ty0
;
1077 elemIdx
= Bits2Number(3,elemIdx2
,elemIdx1
,elemIdx0
);
1079 case ADDR_PIPECFG_P4_8x16
:
1083 elemIdx0
= tx1
^ ty1
;
1084 elemIdx
= Bits2Number(2,elemIdx1
,elemIdx0
);
1086 case ADDR_PIPECFG_P4_16x16
:
1091 elemIdx
= Bits2Number(2, elemIdx1
, elemIdx0
);
1093 case ADDR_PIPECFG_P4_16x32
:
1098 elemIdx
= Bits2Number(2, elemIdx1
, elemIdx0
);
1100 case ADDR_PIPECFG_P4_32x32
:
1106 elemIdx
= Bits2Number(3, elemIdx2
, elemIdx1
, elemIdx0
);
1108 case ADDR_PIPECFG_P8_16x16_8x16
:
1114 case ADDR_PIPECFG_P8_16x32_8x16
:
1120 case ADDR_PIPECFG_P8_32x32_8x16
:
1125 elemIdx
= Bits2Number(2, elemIdx1
, elemIdx0
);
1127 case ADDR_PIPECFG_P8_16x32_16x16
:
1133 case ADDR_PIPECFG_P8_32x32_16x16
:
1138 elemIdx
= Bits2Number(2, elemIdx1
, elemIdx0
);
1140 case ADDR_PIPECFG_P8_32x32_16x32
:
1145 elemIdx
= Bits2Number(2, elemIdx1
, elemIdx0
);
1147 case ADDR_PIPECFG_P8_32x64_32x32
:
1153 elemIdx
= Bits2Number(3, elemIdx2
, elemIdx1
, elemIdx0
);
1155 case ADDR_PIPECFG_P16_32x32_8x16
:
1160 elemIdx
= Bits2Number(2, elemIdx1
, elemIdx0
);
1162 case ADDR_PIPECFG_P16_32x32_16x16
:
1167 elemIdx
= Bits2Number(2, elemIdx1
, elemIdx0
);
1170 ADDR_UNHANDLED_CASE();
1178 ****************************************************************************************************
1179 * SiLib::HwlComputeTileDataWidthAndHeightLinear
1182 * Compute the squared cache shape for per-tile data (CMASK and HTILE) for linear layout
1188 * MacroWidth and macroHeight are measured in pixels
1189 ****************************************************************************************************
1191 VOID
SiLib::HwlComputeTileDataWidthAndHeightLinear(
1192 UINT_32
* pMacroWidth
, ///< [out] macro tile width
1193 UINT_32
* pMacroHeight
, ///< [out] macro tile height
1194 UINT_32 bpp
, ///< [in] bits per pixel
1195 ADDR_TILEINFO
* pTileInfo
///< [in] tile info
1198 ADDR_ASSERT(pTileInfo
!= NULL
);
1200 UINT_32 macroHeight
;
1202 /// In linear mode, the htile or cmask buffer must be padded out to 4 tiles
1203 /// but for P8_32x64_32x32, it must be padded out to 8 tiles
1204 /// Actually there are more pipe configs which need 8-tile padding but SI family
1205 /// has a bug which is fixed in CI family
1206 if ((pTileInfo
->pipeConfig
== ADDR_PIPECFG_P8_32x64_32x32
) ||
1207 (pTileInfo
->pipeConfig
== ADDR_PIPECFG_P16_32x32_8x16
) ||
1208 (pTileInfo
->pipeConfig
== ADDR_PIPECFG_P8_32x32_16x16
))
1210 macroWidth
= 8*MicroTileWidth
;
1211 macroHeight
= 8*MicroTileHeight
;
1215 macroWidth
= 4*MicroTileWidth
;
1216 macroHeight
= 4*MicroTileHeight
;
1219 *pMacroWidth
= macroWidth
;
1220 *pMacroHeight
= macroHeight
;
1224 ****************************************************************************************************
1225 * SiLib::HwlComputeHtileBytes
1228 * Compute htile size in bytes
1231 * Htile size in bytes
1232 ****************************************************************************************************
1234 UINT_64
SiLib::HwlComputeHtileBytes(
1235 UINT_32 pitch
, ///< [in] pitch
1236 UINT_32 height
, ///< [in] height
1237 UINT_32 bpp
, ///< [in] bits per pixel
1238 BOOL_32 isLinear
, ///< [in] if it is linear mode
1239 UINT_32 numSlices
, ///< [in] number of slices
1240 UINT_64
* pSliceBytes
, ///< [out] bytes per slice
1241 UINT_32 baseAlign
///< [in] base alignments
1244 return ComputeHtileBytes(pitch
, height
, bpp
, isLinear
, numSlices
, pSliceBytes
, baseAlign
);
1248 ****************************************************************************************************
1249 * SiLib::HwlComputeXmaskAddrFromCoord
1252 * Compute address from coordinates for htile/cmask
1255 ****************************************************************************************************
1257 UINT_64
SiLib::HwlComputeXmaskAddrFromCoord(
1258 UINT_32 pitch
, ///< [in] pitch
1259 UINT_32 height
, ///< [in] height
1260 UINT_32 x
, ///< [in] x coord
1261 UINT_32 y
, ///< [in] y coord
1262 UINT_32 slice
, ///< [in] slice/depth index
1263 UINT_32 numSlices
, ///< [in] number of slices
1264 UINT_32 factor
, ///< [in] factor that indicates cmask(2) or htile(1)
1265 BOOL_32 isLinear
, ///< [in] linear or tiled HTILE layout
1266 BOOL_32 isWidth8
, ///< [in] TRUE if width is 8, FALSE means 4. It's register value
1267 BOOL_32 isHeight8
, ///< [in] TRUE if width is 8, FALSE means 4. It's register value
1268 ADDR_TILEINFO
* pTileInfo
, ///< [in] Tile info
1269 UINT_32
* pBitPosition
///< [out] bit position inside a byte
1272 UINT_32 tx
= x
/ MicroTileWidth
;
1273 UINT_32 ty
= y
/ MicroTileHeight
;
1278 UINT_32 macroHeight
;
1279 UINT_64 pSliceBytes
;
1281 UINT_32 tileNumPerPipe
;
1284 if (factor
== 2) //CMASK
1286 ADDR_CMASK_FLAGS flags
= {{0}};
1288 tileNumPerPipe
= 256;
1290 ComputeCmaskInfo(flags
,
1301 elemBits
= CmaskElemBits
;
1305 ADDR_HTILE_FLAGS flags
= {{0}};
1307 tileNumPerPipe
= 512;
1309 ComputeHtileInfo(flags
,
1327 const UINT_32 pitchInTile
= newPitch
/ MicroTileWidth
;
1328 const UINT_32 heightInTile
= newHeight
/ MicroTileWidth
;
1329 UINT_64 macroOffset
; // Per pipe starting offset of the macro tile in which this tile lies.
1330 UINT_64 microNumber
; // Per pipe starting offset of the macro tile in which this tile lies.
1333 UINT_64 microOffset
;
1335 UINT_64 totalOffset
;
1336 UINT_32 elemIdxBits
;
1338 TileCoordToMaskElementIndex(tx
, ty
, pTileInfo
->pipeConfig
, µShift
, &elemIdxBits
);
1340 UINT_32 numPipes
= HwlGetPipes(pTileInfo
);
1343 { //linear addressing
1344 // Linear addressing is extremelly wasting memory if slice > 1, since each pipe has the full
1345 // slice memory foot print instead of divided by numPipes.
1346 microX
= tx
/ 4; // Macro Tile is 4x4
1348 microNumber
= static_cast<UINT_64
>(microX
+ microY
* (pitchInTile
/ 4)) << microShift
;
1350 UINT_32 sliceBits
= pitchInTile
* heightInTile
;
1352 // do htile single slice alignment if the flag is true
1353 if (m_configFlags
.useHtileSliceAlign
&& (factor
== 1)) //Htile
1355 sliceBits
= PowTwoAlign(sliceBits
, BITS_TO_BYTES(HtileCacheBits
) * numPipes
/ elemBits
);
1357 macroOffset
= slice
* (sliceBits
/ numPipes
) * elemBits
;
1360 { //tiled addressing
1361 const UINT_32 macroWidthInTile
= macroWidth
/ MicroTileWidth
; // Now in unit of Tiles
1362 const UINT_32 macroHeightInTile
= macroHeight
/ MicroTileHeight
;
1363 const UINT_32 pitchInCL
= pitchInTile
/ macroWidthInTile
;
1364 const UINT_32 heightInCL
= heightInTile
/ macroHeightInTile
;
1366 const UINT_32 macroX
= x
/ macroWidth
;
1367 const UINT_32 macroY
= y
/ macroHeight
;
1368 const UINT_32 macroNumber
= macroX
+ macroY
* pitchInCL
+ slice
* pitchInCL
* heightInCL
;
1370 // Per pipe starting offset of the cache line in which this tile lies.
1371 microX
= (x
% macroWidth
) / MicroTileWidth
/ 4; // Macro Tile is 4x4
1372 microY
= (y
% macroHeight
) / MicroTileHeight
/ 4 ;
1373 microNumber
= static_cast<UINT_64
>(microX
+ microY
* (macroWidth
/ MicroTileWidth
/ 4)) << microShift
;
1375 macroOffset
= macroNumber
* tileNumPerPipe
* elemBits
;
1378 if(elemIdxBits
== microShift
)
1380 microNumber
+= elemIdx
;
1384 microNumber
>>= elemIdxBits
;
1385 microNumber
<<= elemIdxBits
;
1386 microNumber
+= elemIdx
;
1389 microOffset
= elemBits
* microNumber
;
1390 totalOffset
= microOffset
+ macroOffset
;
1392 UINT_32 pipe
= ComputePipeFromCoord(x
, y
, 0, ADDR_TM_2D_TILED_THIN1
, 0, FALSE
, pTileInfo
);
1393 UINT_64 addrInBits
= totalOffset
% (m_pipeInterleaveBytes
* 8) +
1394 pipe
* (m_pipeInterleaveBytes
* 8) +
1395 totalOffset
/ (m_pipeInterleaveBytes
* 8) * (m_pipeInterleaveBytes
* 8) * numPipes
;
1396 *pBitPosition
= static_cast<UINT_32
>(addrInBits
) % 8;
1397 UINT_64 addr
= addrInBits
/ 8;
1403 ****************************************************************************************************
1404 * SiLib::HwlComputeXmaskCoordFromAddr
1407 * Compute the coord from an address of a cmask/htile
1413 * This method is reused by htile, so rename to Xmask
1414 ****************************************************************************************************
1416 VOID
SiLib::HwlComputeXmaskCoordFromAddr(
1417 UINT_64 addr
, ///< [in] address
1418 UINT_32 bitPosition
, ///< [in] bitPosition in a byte
1419 UINT_32 pitch
, ///< [in] pitch
1420 UINT_32 height
, ///< [in] height
1421 UINT_32 numSlices
, ///< [in] number of slices
1422 UINT_32 factor
, ///< [in] factor that indicates cmask or htile
1423 BOOL_32 isLinear
, ///< [in] linear or tiled HTILE layout
1424 BOOL_32 isWidth8
, ///< [in] Not used by SI
1425 BOOL_32 isHeight8
, ///< [in] Not used by SI
1426 ADDR_TILEINFO
* pTileInfo
, ///< [in] Tile info
1427 UINT_32
* pX
, ///< [out] x coord
1428 UINT_32
* pY
, ///< [out] y coord
1429 UINT_32
* pSlice
///< [out] slice index
1437 UINT_32 tileNumPerPipe
;
1444 if (factor
== 2) //CMASK
1446 ADDR_CMASK_FLAGS flags
= {{0}};
1448 tileNumPerPipe
= 256;
1450 ComputeCmaskInfo(flags
,
1464 ADDR_HTILE_FLAGS flags
= {{0}};
1466 tileNumPerPipe
= 512;
1468 ComputeHtileInfo(flags
,
1484 const UINT_32 pitchInTile
= newPitch
/ MicroTileWidth
;
1485 const UINT_32 heightInTile
= newHeight
/ MicroTileWidth
;
1486 const UINT_32 pitchInMacroTile
= pitchInTile
/ 4;
1488 UINT_32 elemIdxBits
;
1489 // get macroShift and elemIdxBits
1490 TileCoordToMaskElementIndex(0, 0, pTileInfo
->pipeConfig
, ¯oShift
, &elemIdxBits
);
1492 const UINT_32 numPipes
= HwlGetPipes(pTileInfo
);
1493 const UINT_32 pipe
= (UINT_32
)((addr
/ m_pipeInterleaveBytes
) % numPipes
);
1495 UINT_64 localOffset
= (addr
% m_pipeInterleaveBytes
) +
1496 (addr
/ m_pipeInterleaveBytes
/ numPipes
)* m_pipeInterleaveBytes
;
1499 if (factor
== 2) //CMASK
1501 tileIndex
= (UINT_32
)(localOffset
* 2 + (bitPosition
!= 0));
1505 tileIndex
= (UINT_32
)(localOffset
/ 4);
1508 UINT_32 macroOffset
;
1511 UINT_32 sliceSizeInTile
= pitchInTile
* heightInTile
;
1513 // do htile single slice alignment if the flag is true
1514 if (m_configFlags
.useHtileSliceAlign
&& (factor
== 1)) //Htile
1516 sliceSizeInTile
= PowTwoAlign(sliceSizeInTile
, static_cast<UINT_32
>(sliceBytes
) / 64);
1518 *pSlice
= tileIndex
/ (sliceSizeInTile
/ numPipes
);
1519 macroOffset
= tileIndex
% (sliceSizeInTile
/ numPipes
);
1523 const UINT_32 clWidthInTile
= clWidth
/ MicroTileWidth
; // Now in unit of Tiles
1524 const UINT_32 clHeightInTile
= clHeight
/ MicroTileHeight
;
1525 const UINT_32 pitchInCL
= pitchInTile
/ clWidthInTile
;
1526 const UINT_32 heightInCL
= heightInTile
/ clHeightInTile
;
1527 const UINT_32 clIndex
= tileIndex
/ tileNumPerPipe
;
1529 UINT_32 clX
= clIndex
% pitchInCL
;
1530 UINT_32 clY
= (clIndex
% (heightInCL
* pitchInCL
)) / pitchInCL
;
1532 *pX
= clX
* clWidthInTile
* MicroTileWidth
;
1533 *pY
= clY
* clHeightInTile
* MicroTileHeight
;
1534 *pSlice
= clIndex
/ (heightInCL
* pitchInCL
);
1536 macroOffset
= tileIndex
% tileNumPerPipe
;
1539 UINT_32 elemIdx
= macroOffset
& 7;
1540 macroOffset
>>= elemIdxBits
;
1542 if (elemIdxBits
!= macroShift
)
1544 macroOffset
<<= (elemIdxBits
- macroShift
);
1546 UINT_32 pipebit1
= _BIT(pipe
,1);
1547 UINT_32 pipebit2
= _BIT(pipe
,2);
1548 UINT_32 pipebit3
= _BIT(pipe
,3);
1549 if (pitchInMacroTile
% 2)
1551 switch (pTileInfo
->pipeConfig
)
1553 case ADDR_PIPECFG_P4_32x32
:
1554 macroOffset
|= pipebit1
;
1556 case ADDR_PIPECFG_P8_32x32_8x16
:
1557 case ADDR_PIPECFG_P8_32x32_16x16
:
1558 case ADDR_PIPECFG_P8_32x32_16x32
:
1559 macroOffset
|= pipebit2
;
1567 if (pitchInMacroTile
% 4)
1569 if (pTileInfo
->pipeConfig
== ADDR_PIPECFG_P8_32x64_32x32
)
1571 macroOffset
|= (pipebit1
<<1);
1573 if((pTileInfo
->pipeConfig
== ADDR_PIPECFG_P16_32x32_8x16
) ||
1574 (pTileInfo
->pipeConfig
== ADDR_PIPECFG_P16_32x32_16x16
))
1576 macroOffset
|= (pipebit3
<<1);
1586 macroX
= macroOffset
% pitchInMacroTile
;
1587 macroY
= macroOffset
/ pitchInMacroTile
;
1591 const UINT_32 clWidthInMacroTile
= clWidth
/ (MicroTileWidth
* 4);
1592 macroX
= macroOffset
% clWidthInMacroTile
;
1593 macroY
= macroOffset
/ clWidthInMacroTile
;
1596 *pX
+= macroX
* 4 * MicroTileWidth
;
1597 *pY
+= macroY
* 4 * MicroTileHeight
;
1601 ComputeTileCoordFromPipeAndElemIdx(elemIdx
, pipe
, pTileInfo
->pipeConfig
, pitchInMacroTile
,
1602 *pX
, *pY
, µX
, µY
);
1604 *pX
+= microX
* MicroTileWidth
;
1605 *pY
+= microY
* MicroTileWidth
;
1609 ****************************************************************************************************
1610 * SiLib::HwlGetPitchAlignmentLinear
1612 * Get pitch alignment
1615 ****************************************************************************************************
1617 UINT_32
SiLib::HwlGetPitchAlignmentLinear(
1618 UINT_32 bpp
, ///< [in] bits per pixel
1619 ADDR_SURFACE_FLAGS flags
///< [in] surface flags
1624 // Interleaved access requires a 256B aligned pitch, so fall back to pre-SI alignment
1625 if (flags
.interleaved
)
1627 pitchAlign
= Max(64u, m_pipeInterleaveBytes
/ BITS_TO_BYTES(bpp
));
1632 pitchAlign
= Max(8u, 64 / BITS_TO_BYTES(bpp
));
1639 ****************************************************************************************************
1640 * SiLib::HwlGetSizeAdjustmentLinear
1643 * Adjust linear surface pitch and slice size
1646 * Logical slice size in bytes
1647 ****************************************************************************************************
1649 UINT_64
SiLib::HwlGetSizeAdjustmentLinear(
1650 AddrTileMode tileMode
, ///< [in] tile mode
1651 UINT_32 bpp
, ///< [in] bits per pixel
1652 UINT_32 numSamples
, ///< [in] number of samples
1653 UINT_32 baseAlign
, ///< [in] base alignment
1654 UINT_32 pitchAlign
, ///< [in] pitch alignment
1655 UINT_32
* pPitch
, ///< [in,out] pointer to pitch
1656 UINT_32
* pHeight
, ///< [in,out] pointer to height
1657 UINT_32
* pHeightAlign
///< [in,out] pointer to height align
1661 if (tileMode
== ADDR_TM_LINEAR_GENERAL
)
1663 sliceSize
= BITS_TO_BYTES(static_cast<UINT_64
>(*pPitch
) * (*pHeight
) * bpp
* numSamples
);
1667 UINT_32 pitch
= *pPitch
;
1668 UINT_32 height
= *pHeight
;
1670 UINT_32 pixelsPerPipeInterleave
= m_pipeInterleaveBytes
/ BITS_TO_BYTES(bpp
);
1671 UINT_32 sliceAlignInPixel
= pixelsPerPipeInterleave
< 64 ? 64 : pixelsPerPipeInterleave
;
1673 // numSamples should be 1 in real cases (no MSAA for linear but TGL may pass non 1 value)
1674 UINT_64 pixelPerSlice
= static_cast<UINT_64
>(pitch
) * height
* numSamples
;
1676 while (pixelPerSlice
% sliceAlignInPixel
)
1678 pitch
+= pitchAlign
;
1679 pixelPerSlice
= static_cast<UINT_64
>(pitch
) * height
* numSamples
;
1684 UINT_32 heightAlign
= 1;
1686 while ((pitch
* heightAlign
) % sliceAlignInPixel
)
1691 *pHeightAlign
= heightAlign
;
1693 sliceSize
= BITS_TO_BYTES(pixelPerSlice
* bpp
);
1700 ****************************************************************************************************
1701 * SiLib::HwlPreHandleBaseLvl3xPitch
1704 * Pre-handler of 3x pitch (96 bit) adjustment
1708 ****************************************************************************************************
1710 UINT_32
SiLib::HwlPreHandleBaseLvl3xPitch(
1711 const ADDR_COMPUTE_SURFACE_INFO_INPUT
* pIn
, ///< [in] input
1712 UINT_32 expPitch
///< [in] pitch
1715 ADDR_ASSERT(pIn
->width
== expPitch
);
1717 // From SI, if pow2Pad is 1 the pitch is expanded 3x first, then padded to pow2, so nothing to
1719 if (pIn
->flags
.pow2Pad
== FALSE
)
1721 Addr::V1::Lib::HwlPreHandleBaseLvl3xPitch(pIn
, expPitch
);
1725 ADDR_ASSERT(IsPow2(expPitch
));
1732 ****************************************************************************************************
1733 * SiLib::HwlPostHandleBaseLvl3xPitch
1736 * Post-handler of 3x pitch adjustment
1740 ****************************************************************************************************
1742 UINT_32
SiLib::HwlPostHandleBaseLvl3xPitch(
1743 const ADDR_COMPUTE_SURFACE_INFO_INPUT
* pIn
, ///< [in] input
1744 UINT_32 expPitch
///< [in] pitch
1748 * @note The pitch will be divided by 3 in the end so the value will look odd but h/w should
1749 * be able to compute a correct pitch from it as h/w address library is doing the job.
1751 // From SI, the pitch is expanded 3x first, then padded to pow2, so no special handler here
1752 if (pIn
->flags
.pow2Pad
== FALSE
)
1754 Addr::V1::Lib::HwlPostHandleBaseLvl3xPitch(pIn
, expPitch
);
1761 ****************************************************************************************************
1762 * SiLib::HwlGetPitchAlignmentMicroTiled
1765 * Compute 1D tiled surface pitch alignment
1769 ****************************************************************************************************
1771 UINT_32
SiLib::HwlGetPitchAlignmentMicroTiled(
1772 AddrTileMode tileMode
, ///< [in] tile mode
1773 UINT_32 bpp
, ///< [in] bits per pixel
1774 ADDR_SURFACE_FLAGS flags
, ///< [in] surface flags
1775 UINT_32 numSamples
///< [in] number of samples
1782 pitchAlign
= EgBasedLib::HwlGetPitchAlignmentMicroTiled(tileMode
,bpp
,flags
,numSamples
);
1793 ****************************************************************************************************
1794 * SiLib::HwlGetSizeAdjustmentMicroTiled
1797 * Adjust 1D tiled surface pitch and slice size
1800 * Logical slice size in bytes
1801 ****************************************************************************************************
1803 UINT_64
SiLib::HwlGetSizeAdjustmentMicroTiled(
1804 UINT_32 thickness
, ///< [in] thickness
1805 UINT_32 bpp
, ///< [in] bits per pixel
1806 ADDR_SURFACE_FLAGS flags
, ///< [in] surface flags
1807 UINT_32 numSamples
, ///< [in] number of samples
1808 UINT_32 baseAlign
, ///< [in] base alignment
1809 UINT_32 pitchAlign
, ///< [in] pitch alignment
1810 UINT_32
* pPitch
, ///< [in,out] pointer to pitch
1811 UINT_32
* pHeight
///< [in,out] pointer to height
1814 UINT_64 logicalSliceSize
;
1815 UINT_64 physicalSliceSize
;
1817 UINT_32 pitch
= *pPitch
;
1818 UINT_32 height
= *pHeight
;
1820 // Logical slice: pitch * height * bpp * numSamples (no 1D MSAA so actually numSamples == 1)
1821 logicalSliceSize
= BITS_TO_BYTES(static_cast<UINT_64
>(pitch
) * height
* bpp
* numSamples
);
1823 // Physical slice: multiplied by thickness
1824 physicalSliceSize
= logicalSliceSize
* thickness
;
1826 // Pitch alignment is always 8, so if slice size is not padded to base alignment
1827 // (pipe_interleave_size), we need to increase pitch
1828 while ((physicalSliceSize
% baseAlign
) != 0)
1830 pitch
+= pitchAlign
;
1832 logicalSliceSize
= BITS_TO_BYTES(static_cast<UINT_64
>(pitch
) * height
* bpp
* numSamples
);
1834 physicalSliceSize
= logicalSliceSize
* thickness
;
1839 // Special workaround for depth/stencil buffer, use 8 bpp to align depth buffer again since
1840 // the stencil plane may have larger pitch if the slice size is smaller than base alignment.
1842 // Note: this actually does not work for mipmap but mipmap depth texture is not really
1843 // sampled with mipmap.
1845 if (flags
.depth
&& (flags
.noStencil
== FALSE
))
1847 ADDR_ASSERT(numSamples
== 1);
1849 UINT_64 logicalSiceSizeStencil
= static_cast<UINT_64
>(pitch
) * height
; // 1 byte stencil
1851 while ((logicalSiceSizeStencil
% baseAlign
) != 0)
1853 pitch
+= pitchAlign
; // Stencil plane's pitch alignment is the same as depth plane's
1855 logicalSiceSizeStencil
= static_cast<UINT_64
>(pitch
) * height
;
1858 if (pitch
!= *pPitch
)
1860 // If this is a mipmap, this padded one cannot be sampled as a whole mipmap!
1861 logicalSliceSize
= logicalSiceSizeStencil
* BITS_TO_BYTES(bpp
);
1867 // No adjust for pHeight
1869 return logicalSliceSize
;
1873 ****************************************************************************************************
1874 * SiLib::HwlConvertChipFamily
1877 * Convert familyID defined in atiid.h to ChipFamily and set m_chipFamily/m_chipRevision
1880 ****************************************************************************************************
1882 ChipFamily
SiLib::HwlConvertChipFamily(
1883 UINT_32 uChipFamily
, ///< [in] chip family defined in atiih.h
1884 UINT_32 uChipRevision
) ///< [in] chip revision defined in "asic_family"_id.h
1886 ChipFamily family
= ADDR_CHIP_FAMILY_SI
;
1888 switch (uChipFamily
)
1891 m_settings
.isSouthernIsland
= 1;
1892 m_settings
.isTahiti
= ASICREV_IS_TAHITI_P(uChipRevision
);
1893 m_settings
.isPitCairn
= ASICREV_IS_PITCAIRN_PM(uChipRevision
);
1894 m_settings
.isCapeVerde
= ASICREV_IS_CAPEVERDE_M(uChipRevision
);
1895 m_settings
.isOland
= ASICREV_IS_OLAND_M(uChipRevision
);
1896 m_settings
.isHainan
= ASICREV_IS_HAINAN_V(uChipRevision
);
1899 ADDR_ASSERT(!"This should be a Fusion");
1907 ****************************************************************************************************
1908 * SiLib::HwlSetupTileInfo
1911 * Setup default value of tile info for SI
1912 ****************************************************************************************************
1914 VOID
SiLib::HwlSetupTileInfo(
1915 AddrTileMode tileMode
, ///< [in] Tile mode
1916 ADDR_SURFACE_FLAGS flags
, ///< [in] Surface type flags
1917 UINT_32 bpp
, ///< [in] Bits per pixel
1918 UINT_32 pitch
, ///< [in] Pitch in pixels
1919 UINT_32 height
, ///< [in] Height in pixels
1920 UINT_32 numSamples
, ///< [in] Number of samples
1921 ADDR_TILEINFO
* pTileInfoIn
, ///< [in] Tile info input: NULL for default
1922 ADDR_TILEINFO
* pTileInfoOut
, ///< [out] Tile info output
1923 AddrTileType inTileType
, ///< [in] Tile type
1924 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
///< [out] Output
1927 UINT_32 thickness
= Thickness(tileMode
);
1928 ADDR_TILEINFO
* pTileInfo
= pTileInfoOut
;
1929 INT index
= TileIndexInvalid
;
1932 if (IsLinear(tileMode
) == FALSE
)
1934 // 128 bpp/thick tiling must be non-displayable.
1935 // Fmask reuse color buffer's entry but bank-height field can be from another entry
1936 // To simplify the logic, fmask entry should be picked from non-displayable ones
1937 if (bpp
== 128 || thickness
> 1 || flags
.fmask
|| flags
.prt
)
1939 inTileType
= ADDR_NON_DISPLAYABLE
;
1942 if (flags
.depth
|| flags
.stencil
)
1944 inTileType
= ADDR_DEPTH_SAMPLE_ORDER
;
1948 // Partial valid fields are not allowed for SI.
1949 if (IsTileInfoAllZero(pTileInfo
))
1951 if (IsMacroTiled(tileMode
))
1955 if (numSamples
== 1)
1968 ADDR_ASSERT_ALWAYS();
1997 ADDR_ASSERT(bpp
!= 128);
2004 ADDR_ASSERT(numSamples
== 4);
2017 ADDR_ASSERT_ALWAYS();
2038 ADDR_ASSERT_ALWAYS();
2044 // See table entries 0-7
2045 else if (flags
.depth
|| flags
.stencil
)
2047 if (flags
.compressZ
)
2055 // optimal tile index for compressed depth/stencil.
2078 else //non PRT & non Depth & non Stencil
2080 // See table entries 9-12
2081 if (inTileType
== ADDR_DISPLAYABLE
)
2103 // See table entries 13-17
2108 UINT_32 fmaskPixelSize
= bpp
* numSamples
;
2110 switch (fmaskPixelSize
)
2125 ADDR_ASSERT_ALWAYS();
2152 else // thick tiling - entries 18-20
2171 if (tileMode
== ADDR_TM_LINEAR_ALIGNED
)
2175 else if (tileMode
== ADDR_TM_LINEAR_GENERAL
)
2177 index
= TileIndexLinearGeneral
;
2181 if (flags
.depth
|| flags
.stencil
)
2185 else if (inTileType
== ADDR_DISPLAYABLE
)
2189 else if (thickness
== 1)
2200 if (index
>= 0 && index
<= 31)
2202 *pTileInfo
= m_tileTable
[index
].info
;
2203 pOut
->tileType
= m_tileTable
[index
].type
;
2206 if (index
== TileIndexLinearGeneral
)
2208 *pTileInfo
= m_tileTable
[8].info
;
2209 pOut
->tileType
= m_tileTable
[8].type
;
2216 if (flags
.stencil
&& pTileInfoIn
->tileSplitBytes
== 0)
2218 // Stencil always uses index 0
2219 *pTileInfo
= m_tileTable
[0].info
;
2222 // Pass through tile type
2223 pOut
->tileType
= inTileType
;
2226 pOut
->tileIndex
= index
;
2227 pOut
->prtTileIndex
= flags
.prt
;
2231 ****************************************************************************************************
2232 * SiLib::DecodeGbRegs
2235 * Decodes GB_ADDR_CONFIG and noOfBanks/noOfRanks
2238 * TRUE if all settings are valid
2240 ****************************************************************************************************
2242 BOOL_32
SiLib::DecodeGbRegs(
2243 const ADDR_REGISTER_VALUE
* pRegValue
) ///< [in] create input
2246 BOOL_32 valid
= TRUE
;
2248 reg
.val
= pRegValue
->gbAddrConfig
;
2250 switch (reg
.f
.pipe_interleave_size
)
2252 case ADDR_CONFIG_PIPE_INTERLEAVE_256B
:
2253 m_pipeInterleaveBytes
= ADDR_PIPEINTERLEAVE_256B
;
2255 case ADDR_CONFIG_PIPE_INTERLEAVE_512B
:
2256 m_pipeInterleaveBytes
= ADDR_PIPEINTERLEAVE_512B
;
2260 ADDR_UNHANDLED_CASE();
2264 switch (reg
.f
.row_size
)
2266 case ADDR_CONFIG_1KB_ROW
:
2267 m_rowSize
= ADDR_ROWSIZE_1KB
;
2269 case ADDR_CONFIG_2KB_ROW
:
2270 m_rowSize
= ADDR_ROWSIZE_2KB
;
2272 case ADDR_CONFIG_4KB_ROW
:
2273 m_rowSize
= ADDR_ROWSIZE_4KB
;
2277 ADDR_UNHANDLED_CASE();
2281 switch (pRegValue
->noOfBanks
)
2294 ADDR_UNHANDLED_CASE();
2298 switch (pRegValue
->noOfRanks
)
2308 ADDR_UNHANDLED_CASE();
2312 m_logicalBanks
= m_banks
* m_ranks
;
2314 ADDR_ASSERT(m_logicalBanks
<= 16);
2320 ****************************************************************************************************
2321 * SiLib::HwlInitGlobalParams
2324 * Initializes global parameters
2327 * TRUE if all settings are valid
2329 ****************************************************************************************************
2331 BOOL_32
SiLib::HwlInitGlobalParams(
2332 const ADDR_CREATE_INPUT
* pCreateIn
) ///< [in] create input
2334 BOOL_32 valid
= TRUE
;
2335 const ADDR_REGISTER_VALUE
* pRegValue
= &pCreateIn
->regValue
;
2337 valid
= DecodeGbRegs(pRegValue
);
2341 if (m_settings
.isTahiti
|| m_settings
.isPitCairn
)
2345 else if (m_settings
.isCapeVerde
|| m_settings
.isOland
)
2351 // Hainan is 2-pipe (m_settings.isHainan == 1)
2355 valid
= InitTileSettingTable(pRegValue
->pTileConfig
, pRegValue
->noOfEntries
);
2359 InitEquationTable();
2369 ****************************************************************************************************
2370 * SiLib::HwlConvertTileInfoToHW
2372 * Entry of si's ConvertTileInfoToHW
2375 ****************************************************************************************************
2377 ADDR_E_RETURNCODE
SiLib::HwlConvertTileInfoToHW(
2378 const ADDR_CONVERT_TILEINFOTOHW_INPUT
* pIn
, ///< [in] input structure
2379 ADDR_CONVERT_TILEINFOTOHW_OUTPUT
* pOut
///< [out] output structure
2382 ADDR_E_RETURNCODE retCode
= ADDR_OK
;
2384 retCode
= EgBasedLib::HwlConvertTileInfoToHW(pIn
, pOut
);
2386 if (retCode
== ADDR_OK
)
2388 if (pIn
->reverse
== FALSE
)
2390 if (pIn
->pTileInfo
->pipeConfig
== ADDR_PIPECFG_INVALID
)
2392 retCode
= ADDR_INVALIDPARAMS
;
2396 pOut
->pTileInfo
->pipeConfig
=
2397 static_cast<AddrPipeCfg
>(pIn
->pTileInfo
->pipeConfig
- 1);
2402 pOut
->pTileInfo
->pipeConfig
=
2403 static_cast<AddrPipeCfg
>(pIn
->pTileInfo
->pipeConfig
+ 1);
2411 ****************************************************************************************************
2412 * SiLib::HwlComputeXmaskCoordYFrom8Pipe
2415 * Compute the Y coord which will be added to Xmask Y
2419 ****************************************************************************************************
2421 UINT_32
SiLib::HwlComputeXmaskCoordYFrom8Pipe(
2422 UINT_32 pipe
, ///< [in] pipe id
2423 UINT_32 x
///< [in] tile coord x, which is original x coord / 8
2426 // This function should never be called since it is 6xx/8xx specfic.
2427 // Keep this empty implementation to avoid any mis-use.
2428 ADDR_ASSERT_ALWAYS();
2434 ****************************************************************************************************
2435 * SiLib::HwlComputeSurfaceCoord2DFromBankPipe
2438 * Compute surface x,y coordinates from bank/pipe info
2441 ****************************************************************************************************
2443 VOID
SiLib::HwlComputeSurfaceCoord2DFromBankPipe(
2444 AddrTileMode tileMode
, ///< [in] tile mode
2445 UINT_32
* pX
, ///< [in,out] x coordinate
2446 UINT_32
* pY
, ///< [in,out] y coordinate
2447 UINT_32 slice
, ///< [in] slice index
2448 UINT_32 bank
, ///< [in] bank number
2449 UINT_32 pipe
, ///< [in] pipe number
2450 UINT_32 bankSwizzle
,///< [in] bank swizzle
2451 UINT_32 pipeSwizzle
,///< [in] pipe swizzle
2452 UINT_32 tileSlices
, ///< [in] slices in a micro tile
2453 BOOL_32 ignoreSE
, ///< [in] TRUE if shader engines are ignored
2454 ADDR_TILEINFO
* pTileInfo
///< [in] bank structure. **All fields to be valid on entry**
2468 UINT_32 numPipes
= GetPipePerSurf(pTileInfo
->pipeConfig
);
2470 CoordFromBankPipe xyBits
= {0};
2471 ComputeSurfaceCoord2DFromBankPipe(tileMode
, *pX
, *pY
, slice
, bank
, pipe
,
2472 bankSwizzle
, pipeSwizzle
, tileSlices
, pTileInfo
,
2474 yBit3
= xyBits
.yBit3
;
2475 yBit4
= xyBits
.yBit4
;
2476 yBit5
= xyBits
.yBit5
;
2477 yBit6
= xyBits
.yBit6
;
2479 xBit3
= xyBits
.xBit3
;
2480 xBit4
= xyBits
.xBit4
;
2481 xBit5
= xyBits
.xBit5
;
2483 yBit
= xyBits
.yBits
;
2485 UINT_32 yBitTemp
= 0;
2487 if ((pTileInfo
->pipeConfig
== ADDR_PIPECFG_P4_32x32
) ||
2488 (pTileInfo
->pipeConfig
== ADDR_PIPECFG_P8_32x64_32x32
))
2490 ADDR_ASSERT(pTileInfo
->bankWidth
== 1 && pTileInfo
->macroAspectRatio
> 1);
2491 UINT_32 yBitToCheck
= QLog2(pTileInfo
->banks
) - 1;
2493 ADDR_ASSERT(yBitToCheck
<= 3);
2495 yBitTemp
= _BIT(yBit
, yBitToCheck
);
2500 yBit
= Bits2Number(4, yBit6
, yBit5
, yBit4
, yBit3
);
2501 xBit
= Bits2Number(3, xBit5
, xBit4
, xBit3
);
2503 *pY
+= yBit
* pTileInfo
->bankHeight
* MicroTileHeight
;
2504 *pX
+= xBit
* numPipes
* pTileInfo
->bankWidth
* MicroTileWidth
;
2506 //calculate the bank and pipe bits in x, y
2507 UINT_32 xTile
; //x in micro tile
2514 UINT_32 pipeBit0
= _BIT(pipe
,0);
2515 UINT_32 pipeBit1
= _BIT(pipe
,1);
2516 UINT_32 pipeBit2
= _BIT(pipe
,2);
2518 UINT_32 y3
= _BIT(y
, 3);
2519 UINT_32 y4
= _BIT(y
, 4);
2520 UINT_32 y5
= _BIT(y
, 5);
2521 UINT_32 y6
= _BIT(y
, 6);
2523 // bankbit0 after ^x4^x5
2524 UINT_32 bankBit00
= _BIT(bank
,0);
2525 UINT_32 bankBit0
= 0;
2527 switch (pTileInfo
->pipeConfig
)
2529 case ADDR_PIPECFG_P2
:
2532 case ADDR_PIPECFG_P4_8x16
:
2536 case ADDR_PIPECFG_P4_16x16
:
2538 x3
= pipeBit0
^ y3
^ x4
;
2540 case ADDR_PIPECFG_P4_16x32
:
2542 x3
= pipeBit0
^ y3
^ x4
;
2544 case ADDR_PIPECFG_P4_32x32
:
2546 x3
= pipeBit0
^ y3
^ x5
;
2547 bankBit0
= yBitTemp
^ x5
;
2548 x4
= bankBit00
^ x5
^ bankBit0
;
2549 *pX
+= x5
* 4 * 1 * 8; // x5 * num_pipes * bank_width * 8;
2551 case ADDR_PIPECFG_P8_16x16_8x16
:
2554 x5
= pipeBit0
^ y3
^ x4
;
2556 case ADDR_PIPECFG_P8_16x32_8x16
:
2559 x5
= pipeBit0
^ y3
^ x4
;
2561 case ADDR_PIPECFG_P8_32x32_8x16
:
2564 x4
= pipeBit0
^ y3
^ x5
;
2566 case ADDR_PIPECFG_P8_16x32_16x16
:
2569 x3
= pipeBit0
^ y3
^ x4
;
2571 case ADDR_PIPECFG_P8_32x32_16x16
:
2574 x3
= pipeBit0
^ y3
^ x4
;
2576 case ADDR_PIPECFG_P8_32x32_16x32
:
2579 x3
= pipeBit0
^ y3
^ x4
;
2581 case ADDR_PIPECFG_P8_32x64_32x32
:
2584 x3
= pipeBit0
^ y3
^ x5
;
2585 bankBit0
= yBitTemp
^ x6
;
2586 x4
= bankBit00
^ x5
^ bankBit0
;
2587 *pX
+= x6
* 8 * 1 * 8; // x6 * num_pipes * bank_width * 8;
2590 ADDR_ASSERT_ALWAYS();
2593 xTile
= Bits2Number(3, x5
, x4
, x3
);
2599 ****************************************************************************************************
2600 * SiLib::HwlPreAdjustBank
2603 * Adjust bank before calculating address acoording to bank/pipe
2606 ****************************************************************************************************
2608 UINT_32
SiLib::HwlPreAdjustBank(
2609 UINT_32 tileX
, ///< [in] x coordinate in unit of tile
2610 UINT_32 bank
, ///< [in] bank
2611 ADDR_TILEINFO
* pTileInfo
///< [in] tile info
2614 if (((pTileInfo
->pipeConfig
== ADDR_PIPECFG_P4_32x32
) ||
2615 (pTileInfo
->pipeConfig
== ADDR_PIPECFG_P8_32x64_32x32
)) && (pTileInfo
->bankWidth
== 1))
2617 UINT_32 bankBit0
= _BIT(bank
, 0);
2618 UINT_32 x4
= _BIT(tileX
, 1);
2619 UINT_32 x5
= _BIT(tileX
, 2);
2621 bankBit0
= bankBit0
^ x4
^ x5
;
2624 ADDR_ASSERT(pTileInfo
->macroAspectRatio
> 1);
2631 ****************************************************************************************************
2632 * SiLib::HwlComputeSurfaceInfo
2635 * Entry of si's ComputeSurfaceInfo
2638 ****************************************************************************************************
2640 ADDR_E_RETURNCODE
SiLib::HwlComputeSurfaceInfo(
2641 const ADDR_COMPUTE_SURFACE_INFO_INPUT
* pIn
, ///< [in] input structure
2642 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
///< [out] output structure
2645 pOut
->tileIndex
= pIn
->tileIndex
;
2647 ADDR_E_RETURNCODE retCode
= EgBasedLib::HwlComputeSurfaceInfo(pIn
, pOut
);
2649 UINT_32 tileIndex
= static_cast<UINT_32
>(pOut
->tileIndex
);
2651 if (((pIn
->flags
.needEquation
== TRUE
) ||
2652 (pIn
->flags
.preferEquation
== TRUE
)) &&
2653 (pIn
->numSamples
<= 1) &&
2654 (tileIndex
< TileTableSize
))
2656 static const UINT_32 SiUncompressDepthTileIndex
= 3;
2658 if ((pIn
->numSlices
> 1) &&
2659 (IsMacroTiled(pOut
->tileMode
) == TRUE
) &&
2660 ((m_chipFamily
== ADDR_CHIP_FAMILY_SI
) ||
2661 (IsPrtTileMode(pOut
->tileMode
) == FALSE
)))
2663 pOut
->equationIndex
= ADDR_INVALID_EQUATION_INDEX
;
2665 else if ((pIn
->flags
.prt
== FALSE
) &&
2666 (m_uncompressDepthEqIndex
!= 0) &&
2667 (tileIndex
== SiUncompressDepthTileIndex
))
2669 pOut
->equationIndex
= m_uncompressDepthEqIndex
+ Log2(pIn
->bpp
>> 3);
2674 pOut
->equationIndex
= m_equationLookupTable
[Log2(pIn
->bpp
>> 3)][tileIndex
];
2677 if (pOut
->equationIndex
!= ADDR_INVALID_EQUATION_INDEX
)
2679 pOut
->blockWidth
= m_blockWidth
[pOut
->equationIndex
];
2681 pOut
->blockHeight
= m_blockHeight
[pOut
->equationIndex
];
2683 pOut
->blockSlices
= m_blockSlices
[pOut
->equationIndex
];
2688 pOut
->equationIndex
= ADDR_INVALID_EQUATION_INDEX
;
2695 ****************************************************************************************************
2696 * SiLib::HwlComputeMipLevel
2698 * Compute MipLevel info (including level 0)
2700 * TRUE if HWL's handled
2701 ****************************************************************************************************
2703 BOOL_32
SiLib::HwlComputeMipLevel(
2704 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pIn
///< [in,out] Input structure
2707 // basePitch is calculated from level 0 so we only check this for mipLevel > 0
2708 if (pIn
->mipLevel
> 0)
2710 // Note: Don't check expand 3x formats(96 bit) as the basePitch is not pow2 even if
2711 // we explicity set pow2Pad flag. The 3x base pitch is padded to pow2 but after being
2712 // divided by expandX factor (3) - to program texture pitch, the basePitch is never pow2.
2713 if (ElemLib::IsExpand3x(pIn
->format
) == FALSE
)
2715 // Sublevel pitches are generated from base level pitch instead of width on SI
2716 // If pow2Pad is 0, we don't assert - as this is not really used for a mip chain
2717 ADDR_ASSERT((pIn
->flags
.pow2Pad
== FALSE
) ||
2718 ((pIn
->basePitch
!= 0) && IsPow2(pIn
->basePitch
)));
2721 if (pIn
->basePitch
!= 0)
2723 pIn
->width
= Max(1u, pIn
->basePitch
>> pIn
->mipLevel
);
2727 // pow2Pad is done in PostComputeMipLevel
2733 ****************************************************************************************************
2734 * SiLib::HwlCheckLastMacroTiledLvl
2737 * Sets pOut->last2DLevel to TRUE if it is
2740 ****************************************************************************************************
2742 VOID
SiLib::HwlCheckLastMacroTiledLvl(
2743 const ADDR_COMPUTE_SURFACE_INFO_INPUT
* pIn
, ///< [in] Input structure
2744 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
///< [in,out] Output structure (used as input, too)
2747 // pow2Pad covers all mipmap cases
2748 if (pIn
->flags
.pow2Pad
)
2750 ADDR_ASSERT(IsMacroTiled(pIn
->tileMode
));
2756 AddrTileMode nextTileMode
;
2758 if (pIn
->mipLevel
== 0 || pIn
->basePitch
== 0)
2760 // Base level or fail-safe case (basePitch == 0)
2761 nextPitch
= pOut
->pitch
>> 1;
2766 nextPitch
= pIn
->basePitch
>> (pIn
->mipLevel
+ 1);
2769 // nextHeight must be shifted from this level's original height rather than a pow2 padded
2770 // one but this requires original height stored somewhere (pOut->height)
2771 ADDR_ASSERT(pOut
->height
!= 0);
2773 // next level's height is just current level's >> 1 in pixels
2774 nextHeight
= pOut
->height
>> 1;
2775 // Special format such as FMT_1 and FMT_32_32_32 can be linear only so we consider block
2776 // compressed foramts
2777 if (ElemLib::IsBlockCompressed(pIn
->format
))
2779 nextHeight
= (nextHeight
+ 3) / 4;
2781 nextHeight
= NextPow2(nextHeight
);
2783 // nextSlices may be 0 if this level's is 1
2784 if (pIn
->flags
.volume
)
2786 nextSlices
= Max(1u, pIn
->numSlices
>> 1);
2790 nextSlices
= pIn
->numSlices
;
2793 nextTileMode
= ComputeSurfaceMipLevelTileMode(pIn
->tileMode
,
2803 pOut
->last2DLevel
= IsMicroTiled(nextTileMode
);
2808 ****************************************************************************************************
2809 * SiLib::HwlDegradeThickTileMode
2812 * Degrades valid tile mode for thick modes if needed
2815 * Suitable tile mode
2816 ****************************************************************************************************
2818 AddrTileMode
SiLib::HwlDegradeThickTileMode(
2819 AddrTileMode baseTileMode
, ///< base tile mode
2820 UINT_32 numSlices
, ///< current number of slices
2821 UINT_32
* pBytesPerTile
///< [in,out] pointer to bytes per slice
2824 return EgBasedLib::HwlDegradeThickTileMode(baseTileMode
, numSlices
, pBytesPerTile
);
2828 ****************************************************************************************************
2829 * SiLib::HwlTileInfoEqual
2832 * Return TRUE if all field are equal
2834 * Only takes care of current HWL's data
2835 ****************************************************************************************************
2837 BOOL_32
SiLib::HwlTileInfoEqual(
2838 const ADDR_TILEINFO
* pLeft
, ///<[in] Left compare operand
2839 const ADDR_TILEINFO
* pRight
///<[in] Right compare operand
2842 BOOL_32 equal
= FALSE
;
2844 if (pLeft
->pipeConfig
== pRight
->pipeConfig
)
2846 equal
= EgBasedLib::HwlTileInfoEqual(pLeft
, pRight
);
2853 ****************************************************************************************************
2854 * SiLib::GetTileSettings
2857 * Get tile setting infos by index.
2859 * Tile setting info.
2860 ****************************************************************************************************
2862 const TileConfig
* SiLib::GetTileSetting(
2863 UINT_32 index
///< [in] Tile index
2866 ADDR_ASSERT(index
< m_noOfEntries
);
2867 return &m_tileTable
[index
];
2871 ****************************************************************************************************
2872 * SiLib::HwlPostCheckTileIndex
2875 * Map a tile setting to index if curIndex is invalid, otherwise check if curIndex matches
2876 * tile mode/type/info and change the index if needed
2879 ****************************************************************************************************
2881 INT_32
SiLib::HwlPostCheckTileIndex(
2882 const ADDR_TILEINFO
* pInfo
, ///< [in] Tile Info
2883 AddrTileMode mode
, ///< [in] Tile mode
2884 AddrTileType type
, ///< [in] Tile type
2885 INT curIndex
///< [in] Current index assigned in HwlSetupTileInfo
2888 INT_32 index
= curIndex
;
2890 if (mode
== ADDR_TM_LINEAR_GENERAL
)
2892 index
= TileIndexLinearGeneral
;
2896 BOOL_32 macroTiled
= IsMacroTiled(mode
);
2898 // We need to find a new index if either of them is true
2899 // 1. curIndex is invalid
2900 // 2. tile mode is changed
2901 // 3. tile info does not match for macro tiled
2902 if ((index
== TileIndexInvalid
||
2903 (mode
!= m_tileTable
[index
].mode
) ||
2904 (macroTiled
&& (HwlTileInfoEqual(pInfo
, &m_tileTable
[index
].info
) == FALSE
))))
2906 for (index
= 0; index
< static_cast<INT_32
>(m_noOfEntries
); index
++)
2910 // macro tile modes need all to match
2911 if (HwlTileInfoEqual(pInfo
, &m_tileTable
[index
].info
) &&
2912 (mode
== m_tileTable
[index
].mode
) &&
2913 (type
== m_tileTable
[index
].type
))
2918 else if (mode
== ADDR_TM_LINEAR_ALIGNED
)
2920 // linear mode only needs tile mode to match
2921 if (mode
== m_tileTable
[index
].mode
)
2928 // micro tile modes only need tile mode and tile type to match
2929 if (mode
== m_tileTable
[index
].mode
&&
2930 type
== m_tileTable
[index
].type
)
2939 ADDR_ASSERT(index
< static_cast<INT_32
>(m_noOfEntries
));
2941 if (index
>= static_cast<INT_32
>(m_noOfEntries
))
2943 index
= TileIndexInvalid
;
2950 ****************************************************************************************************
2951 * SiLib::HwlSetupTileCfg
2954 * Map tile index to tile setting.
2957 ****************************************************************************************************
2959 ADDR_E_RETURNCODE
SiLib::HwlSetupTileCfg(
2960 UINT_32 bpp
, ///< Bits per pixel
2961 INT_32 index
, ///< Tile index
2962 INT_32 macroModeIndex
, ///< Index in macro tile mode table(CI)
2963 ADDR_TILEINFO
* pInfo
, ///< [out] Tile Info
2964 AddrTileMode
* pMode
, ///< [out] Tile mode
2965 AddrTileType
* pType
///< [out] Tile type
2968 ADDR_E_RETURNCODE returnCode
= ADDR_OK
;
2970 // Global flag to control usage of tileIndex
2971 if (UseTileIndex(index
))
2973 if (index
== TileIndexLinearGeneral
)
2977 *pMode
= ADDR_TM_LINEAR_GENERAL
;
2982 *pType
= ADDR_DISPLAYABLE
;
2988 pInfo
->bankWidth
= 1;
2989 pInfo
->bankHeight
= 1;
2990 pInfo
->macroAspectRatio
= 1;
2991 pInfo
->tileSplitBytes
= 64;
2992 pInfo
->pipeConfig
= ADDR_PIPECFG_P2
;
2995 else if (static_cast<UINT_32
>(index
) >= m_noOfEntries
)
2997 returnCode
= ADDR_INVALIDPARAMS
;
3001 const TileConfig
* pCfgTable
= GetTileSetting(index
);
3005 *pInfo
= pCfgTable
->info
;
3009 if (IsMacroTiled(pCfgTable
->mode
))
3011 returnCode
= ADDR_INVALIDPARAMS
;
3017 *pMode
= pCfgTable
->mode
;
3022 *pType
= pCfgTable
->type
;
3031 ****************************************************************************************************
3032 * SiLib::ReadGbTileMode
3035 * Convert GB_TILE_MODE HW value to TileConfig.
3038 ****************************************************************************************************
3040 VOID
SiLib::ReadGbTileMode(
3041 UINT_32 regValue
, ///< [in] GB_TILE_MODE register
3042 TileConfig
* pCfg
///< [out] output structure
3045 GB_TILE_MODE gbTileMode
;
3046 gbTileMode
.val
= regValue
;
3048 pCfg
->type
= static_cast<AddrTileType
>(gbTileMode
.f
.micro_tile_mode
);
3049 pCfg
->info
.bankHeight
= 1 << gbTileMode
.f
.bank_height
;
3050 pCfg
->info
.bankWidth
= 1 << gbTileMode
.f
.bank_width
;
3051 pCfg
->info
.banks
= 1 << (gbTileMode
.f
.num_banks
+ 1);
3052 pCfg
->info
.macroAspectRatio
= 1 << gbTileMode
.f
.macro_tile_aspect
;
3053 pCfg
->info
.tileSplitBytes
= 64 << gbTileMode
.f
.tile_split
;
3054 pCfg
->info
.pipeConfig
= static_cast<AddrPipeCfg
>(gbTileMode
.f
.pipe_config
+ 1);
3056 UINT_32 regArrayMode
= gbTileMode
.f
.array_mode
;
3058 pCfg
->mode
= static_cast<AddrTileMode
>(regArrayMode
);
3060 if (regArrayMode
== 8) //ARRAY_2D_TILED_XTHICK
3062 pCfg
->mode
= ADDR_TM_2D_TILED_XTHICK
;
3064 else if (regArrayMode
>= 14) //ARRAY_3D_TILED_XTHICK
3066 pCfg
->mode
= static_cast<AddrTileMode
>(pCfg
->mode
+ 3);
3071 ****************************************************************************************************
3072 * SiLib::InitTileSettingTable
3075 * Initialize the ADDR_TILE_CONFIG table.
3077 * TRUE if tile table is correctly initialized
3078 ****************************************************************************************************
3080 BOOL_32
SiLib::InitTileSettingTable(
3081 const UINT_32
* pCfg
, ///< [in] Pointer to table of tile configs
3082 UINT_32 noOfEntries
///< [in] Numbe of entries in the table above
3085 BOOL_32 initOk
= TRUE
;
3087 ADDR_ASSERT(noOfEntries
<= TileTableSize
);
3089 memset(m_tileTable
, 0, sizeof(m_tileTable
));
3091 if (noOfEntries
!= 0)
3093 m_noOfEntries
= noOfEntries
;
3097 m_noOfEntries
= TileTableSize
;
3100 if (pCfg
) // From Client
3102 for (UINT_32 i
= 0; i
< m_noOfEntries
; i
++)
3104 ReadGbTileMode(*(pCfg
+ i
), &m_tileTable
[i
]);
3109 ADDR_ASSERT_ALWAYS();
3115 ADDR_ASSERT(m_tileTable
[TILEINDEX_LINEAR_ALIGNED
].mode
== ADDR_TM_LINEAR_ALIGNED
);
3122 ****************************************************************************************************
3123 * SiLib::HwlGetTileIndex
3126 * Return the virtual/real index for given mode/type/info
3128 * ADDR_OK if successful.
3129 ****************************************************************************************************
3131 ADDR_E_RETURNCODE
SiLib::HwlGetTileIndex(
3132 const ADDR_GET_TILEINDEX_INPUT
* pIn
,
3133 ADDR_GET_TILEINDEX_OUTPUT
* pOut
) const
3135 ADDR_E_RETURNCODE returnCode
= ADDR_OK
;
3137 pOut
->index
= HwlPostCheckTileIndex(pIn
->pTileInfo
, pIn
->tileMode
, pIn
->tileType
);
3143 ****************************************************************************************************
3144 * SiLib::HwlFmaskPreThunkSurfInfo
3147 * Some preparation before thunking a ComputeSurfaceInfo call for Fmask
3150 ****************************************************************************************************
3152 VOID
SiLib::HwlFmaskPreThunkSurfInfo(
3153 const ADDR_COMPUTE_FMASK_INFO_INPUT
* pFmaskIn
, ///< [in] Input of fmask info
3154 const ADDR_COMPUTE_FMASK_INFO_OUTPUT
* pFmaskOut
, ///< [in] Output of fmask info
3155 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pSurfIn
, ///< [out] Input of thunked surface info
3156 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pSurfOut
///< [out] Output of thunked surface info
3159 pSurfIn
->tileIndex
= pFmaskIn
->tileIndex
;
3163 ****************************************************************************************************
3164 * SiLib::HwlFmaskPostThunkSurfInfo
3167 * Copy hwl extra field after calling thunked ComputeSurfaceInfo
3170 ****************************************************************************************************
3172 VOID
SiLib::HwlFmaskPostThunkSurfInfo(
3173 const ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pSurfOut
, ///< [in] Output of surface info
3174 ADDR_COMPUTE_FMASK_INFO_OUTPUT
* pFmaskOut
///< [out] Output of fmask info
3177 pFmaskOut
->macroModeIndex
= TileIndexInvalid
;
3178 pFmaskOut
->tileIndex
= pSurfOut
->tileIndex
;
3182 ****************************************************************************************************
3183 * SiLib::HwlComputeFmaskBits
3185 * Computes fmask bits
3188 ****************************************************************************************************
3190 UINT_32
SiLib::HwlComputeFmaskBits(
3191 const ADDR_COMPUTE_FMASK_INFO_INPUT
* pIn
,
3192 UINT_32
* pNumSamples
3195 UINT_32 numSamples
= pIn
->numSamples
;
3196 UINT_32 numFrags
= GetNumFragments(numSamples
, pIn
->numFrags
);
3199 if (numFrags
!= numSamples
) // EQAA
3201 ADDR_ASSERT(numFrags
<= 8);
3203 if (pIn
->resolved
== FALSE
)
3208 numSamples
= numSamples
== 16 ? 16 : 8;
3210 else if (numFrags
== 2)
3212 ADDR_ASSERT(numSamples
>= 4);
3215 numSamples
= numSamples
;
3217 else if (numFrags
== 4)
3219 ADDR_ASSERT(numSamples
>= 4);
3222 numSamples
= numSamples
;
3224 else // numFrags == 8
3226 ADDR_ASSERT(numSamples
== 16);
3229 numSamples
= numSamples
;
3236 bpp
= (numSamples
== 16) ? 16 : 8;
3239 else if (numFrags
== 2)
3241 ADDR_ASSERT(numSamples
>= 4);
3246 else if (numFrags
== 4)
3248 ADDR_ASSERT(numSamples
>= 4);
3253 else // numFrags == 8
3255 ADDR_ASSERT(numSamples
>= 16);
3264 if (pIn
->resolved
== FALSE
)
3266 bpp
= ComputeFmaskNumPlanesFromNumSamples(numSamples
);
3267 numSamples
= numSamples
== 2 ? 8 : numSamples
;
3272 bpp
= ComputeFmaskResolvedBppFromNumSamples(numSamples
);
3273 numSamples
= 1; // 1x sample
3277 SafeAssign(pNumSamples
, numSamples
);
3283 ****************************************************************************************************
3284 * SiLib::HwlOptimizeTileMode
3287 * Optimize tile mode on SI
3292 ****************************************************************************************************
3294 VOID
SiLib::HwlOptimizeTileMode(
3295 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pInOut
///< [in,out] input output structure
3298 AddrTileMode tileMode
= pInOut
->tileMode
;
3300 if ((pInOut
->flags
.needEquation
== TRUE
) &&
3301 (IsMacroTiled(tileMode
) == TRUE
) &&
3302 (pInOut
->numSamples
<= 1))
3304 UINT_32 thickness
= Thickness(tileMode
);
3308 tileMode
= ADDR_TM_1D_TILED_THICK
;
3310 else if (pInOut
->numSlices
> 1)
3312 tileMode
= ADDR_TM_1D_TILED_THIN1
;
3316 tileMode
= ADDR_TM_2D_TILED_THIN1
;
3320 if (tileMode
!= pInOut
->tileMode
)
3322 pInOut
->tileMode
= tileMode
;
3327 ****************************************************************************************************
3328 * SiLib::HwlOverrideTileMode
3331 * Override tile modes (for PRT only, avoid client passes in an invalid PRT mode for SI.
3336 ****************************************************************************************************
3338 VOID
SiLib::HwlOverrideTileMode(
3339 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pInOut
///< [in,out] input output structure
3342 AddrTileMode tileMode
= pInOut
->tileMode
;
3346 case ADDR_TM_PRT_TILED_THIN1
:
3347 tileMode
= ADDR_TM_2D_TILED_THIN1
;
3350 case ADDR_TM_PRT_TILED_THICK
:
3351 tileMode
= ADDR_TM_2D_TILED_THICK
;
3354 case ADDR_TM_PRT_2D_TILED_THICK
:
3355 tileMode
= ADDR_TM_2D_TILED_THICK
;
3358 case ADDR_TM_PRT_3D_TILED_THICK
:
3359 tileMode
= ADDR_TM_3D_TILED_THICK
;
3366 if (tileMode
!= pInOut
->tileMode
)
3368 pInOut
->tileMode
= tileMode
;
3369 // Only PRT tile modes are overridden for now. Revisit this once new modes are added above.
3370 pInOut
->flags
.prt
= TRUE
;
3375 ****************************************************************************************************
3376 * SiLib::HwlSetPrtTileMode
3379 * Set prt tile modes.
3384 ****************************************************************************************************
3386 VOID
SiLib::HwlSetPrtTileMode(
3387 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pInOut
///< [in,out] input output structure
3390 pInOut
->tileMode
= ADDR_TM_2D_TILED_THIN1
;
3391 pInOut
->tileType
= (pInOut
->tileType
== ADDR_DEPTH_SAMPLE_ORDER
) ?
3392 ADDR_DEPTH_SAMPLE_ORDER
: ADDR_NON_DISPLAYABLE
;
3393 pInOut
->flags
.prt
= TRUE
;
3397 ****************************************************************************************************
3398 * SiLib::HwlSelectTileMode
3401 * Select tile modes.
3406 ****************************************************************************************************
3408 VOID
SiLib::HwlSelectTileMode(
3409 ADDR_COMPUTE_SURFACE_INFO_INPUT
* pInOut
///< [in,out] input output structure
3412 AddrTileMode tileMode
;
3413 AddrTileType tileType
;
3415 if (pInOut
->flags
.volume
)
3417 if (pInOut
->numSlices
>= 8)
3419 tileMode
= ADDR_TM_2D_TILED_XTHICK
;
3421 else if (pInOut
->numSlices
>= 4)
3423 tileMode
= ADDR_TM_2D_TILED_THICK
;
3427 tileMode
= ADDR_TM_2D_TILED_THIN1
;
3429 tileType
= ADDR_NON_DISPLAYABLE
;
3433 tileMode
= ADDR_TM_2D_TILED_THIN1
;
3435 if (pInOut
->flags
.depth
|| pInOut
->flags
.stencil
)
3437 tileType
= ADDR_DEPTH_SAMPLE_ORDER
;
3439 else if ((pInOut
->bpp
<= 32) ||
3440 (pInOut
->flags
.display
== TRUE
) ||
3441 (pInOut
->flags
.overlay
== TRUE
))
3443 tileType
= ADDR_DISPLAYABLE
;
3447 tileType
= ADDR_NON_DISPLAYABLE
;
3451 if (pInOut
->flags
.prt
)
3453 tileMode
= ADDR_TM_2D_TILED_THIN1
;
3454 tileType
= (tileType
== ADDR_DISPLAYABLE
) ? ADDR_NON_DISPLAYABLE
: tileType
;
3457 pInOut
->tileMode
= tileMode
;
3458 pInOut
->tileType
= tileType
;
3460 // Optimize tile mode if possible
3461 pInOut
->flags
.opt4Space
= TRUE
;
3463 // Optimize tile mode if possible
3464 OptimizeTileMode(pInOut
);
3466 HwlOverrideTileMode(pInOut
);
3470 ****************************************************************************************************
3471 * SiLib::HwlGetMaxAlignments
3474 * Gets maximum alignments
3477 ****************************************************************************************************
3479 ADDR_E_RETURNCODE
SiLib::HwlGetMaxAlignments(
3480 ADDR_GET_MAX_ALIGNMENTS_OUTPUT
* pOut
///< [out] output structure
3483 const UINT_32 pipes
= HwlGetPipes(&m_tileTable
[0].info
);
3485 // Initial size is 64 KiB for PRT.
3486 UINT_64 maxBaseAlign
= 64 * 1024;
3488 for (UINT_32 i
= 0; i
< m_noOfEntries
; i
++)
3490 if ((IsMacroTiled(m_tileTable
[i
].mode
) == TRUE
) &&
3491 (IsPrtTileMode(m_tileTable
[i
].mode
) == FALSE
))
3493 // The maximum tile size is 16 byte-per-pixel and either 8-sample or 8-slice.
3494 UINT_32 tileSize
= Min(m_tileTable
[i
].info
.tileSplitBytes
,
3495 MicroTilePixels
* 8 * 16);
3497 UINT_64 baseAlign
= tileSize
* pipes
* m_tileTable
[i
].info
.banks
*
3498 m_tileTable
[i
].info
.bankWidth
* m_tileTable
[i
].info
.bankHeight
;
3500 if (baseAlign
> maxBaseAlign
)
3502 maxBaseAlign
= baseAlign
;
3509 pOut
->baseAlign
= maxBaseAlign
;
3516 ****************************************************************************************************
3517 * SiLib::HwlComputeSurfaceAlignmentsMacroTiled
3520 * Hardware layer function to compute alignment request for macro tile mode
3525 ****************************************************************************************************
3527 VOID
SiLib::HwlComputeSurfaceAlignmentsMacroTiled(
3528 AddrTileMode tileMode
, ///< [in] tile mode
3529 UINT_32 bpp
, ///< [in] bits per pixel
3530 ADDR_SURFACE_FLAGS flags
, ///< [in] surface flags
3531 UINT_32 mipLevel
, ///< [in] mip level
3532 UINT_32 numSamples
, ///< [in] number of samples
3533 ADDR_COMPUTE_SURFACE_INFO_OUTPUT
* pOut
///< [in,out] Surface output
3536 if ((mipLevel
== 0) && (flags
.prt
))
3538 UINT_32 macroTileSize
= pOut
->blockWidth
* pOut
->blockHeight
* numSamples
* bpp
/ 8;
3540 if (macroTileSize
< PrtTileSize
)
3542 UINT_32 numMacroTiles
= PrtTileSize
/ macroTileSize
;
3544 ADDR_ASSERT((PrtTileSize
% macroTileSize
) == 0);
3546 pOut
->pitchAlign
*= numMacroTiles
;
3547 pOut
->baseAlign
*= numMacroTiles
;
3553 ****************************************************************************************************
3554 * SiLib::InitEquationTable
3557 * Initialize Equation table.
3561 ****************************************************************************************************
3563 VOID
SiLib::InitEquationTable()
3565 ADDR_EQUATION_KEY equationKeyTable
[EquationTableSize
];
3566 memset(equationKeyTable
, 0, sizeof(equationKeyTable
));
3568 memset(m_equationTable
, 0, sizeof(m_equationTable
));
3570 memset(m_blockWidth
, 0, sizeof(m_blockWidth
));
3572 memset(m_blockHeight
, 0, sizeof(m_blockHeight
));
3574 memset(m_blockSlices
, 0, sizeof(m_blockSlices
));
3576 // Loop all possible bpp
3577 for (UINT_32 log2ElementBytes
= 0; log2ElementBytes
< MaxNumElementBytes
; log2ElementBytes
++)
3579 // Get bits per pixel
3580 UINT_32 bpp
= 1 << (log2ElementBytes
+ 3);
3582 // Loop all possible tile index
3583 for (INT_32 tileIndex
= 0; tileIndex
< static_cast<INT_32
>(m_noOfEntries
); tileIndex
++)
3585 UINT_32 equationIndex
= ADDR_INVALID_EQUATION_INDEX
;
3587 TileConfig tileConfig
= m_tileTable
[tileIndex
];
3589 ADDR_SURFACE_FLAGS flags
= {{0}};
3591 // Compute tile info, hardcode numSamples to 1 because MSAA is not supported
3592 // in swizzle pattern equation
3593 HwlComputeMacroModeIndex(tileIndex
, flags
, bpp
, 1, &tileConfig
.info
, NULL
, NULL
);
3595 // Check if the input is supported
3596 if (IsEquationSupported(bpp
, tileConfig
, tileIndex
, log2ElementBytes
) == TRUE
)
3598 ADDR_EQUATION_KEY key
= {{0}};
3600 // Generate swizzle equation key from bpp and tile config
3601 key
.fields
.log2ElementBytes
= log2ElementBytes
;
3602 key
.fields
.tileMode
= tileConfig
.mode
;
3603 // Treat depth micro tile type and non-display micro tile type as the same key
3604 // because they have the same equation actually
3605 key
.fields
.microTileType
= (tileConfig
.type
== ADDR_DEPTH_SAMPLE_ORDER
) ?
3606 ADDR_NON_DISPLAYABLE
: tileConfig
.type
;
3607 key
.fields
.pipeConfig
= tileConfig
.info
.pipeConfig
;
3608 key
.fields
.numBanksLog2
= Log2(tileConfig
.info
.banks
);
3609 key
.fields
.bankWidth
= tileConfig
.info
.bankWidth
;
3610 key
.fields
.bankHeight
= tileConfig
.info
.bankHeight
;
3611 key
.fields
.macroAspectRatio
= tileConfig
.info
.macroAspectRatio
;
3612 key
.fields
.prt
= ((m_chipFamily
== ADDR_CHIP_FAMILY_SI
) &&
3613 ((1 << tileIndex
) & SiPrtTileIndexMask
)) ? 1 : 0;
3615 // Find in the table if the equation has been built based on the key
3616 for (UINT_32 i
= 0; i
< m_numEquations
; i
++)
3618 if (key
.value
== equationKeyTable
[i
].value
)
3625 // If found, just fill the index into the lookup table and no need
3626 // to generate the equation again. Otherwise, generate the equation.
3627 if (equationIndex
== ADDR_INVALID_EQUATION_INDEX
)
3629 ADDR_EQUATION equation
;
3630 ADDR_E_RETURNCODE retCode
;
3632 memset(&equation
, 0, sizeof(ADDR_EQUATION
));
3634 // Generate the equation
3635 if (IsMicroTiled(tileConfig
.mode
))
3637 retCode
= ComputeMicroTileEquation(log2ElementBytes
,
3644 retCode
= ComputeMacroTileEquation(log2ElementBytes
,
3650 // Only fill the equation into the table if the return code is ADDR_OK,
3651 // otherwise if the return code is not ADDR_OK, it indicates this is not
3652 // a valid input, we do nothing but just fill invalid equation index
3653 // into the lookup table.
3654 if (retCode
== ADDR_OK
)
3656 equationIndex
= m_numEquations
;
3657 ADDR_ASSERT(equationIndex
< EquationTableSize
);
3659 m_blockSlices
[equationIndex
] = Thickness(tileConfig
.mode
);
3661 if (IsMicroTiled(tileConfig
.mode
))
3663 m_blockWidth
[equationIndex
] = MicroTileWidth
;
3664 m_blockHeight
[equationIndex
] = MicroTileHeight
;
3668 const ADDR_TILEINFO
* pTileInfo
= &tileConfig
.info
;
3670 m_blockWidth
[equationIndex
] =
3671 HwlGetPipes(pTileInfo
) * MicroTileWidth
* pTileInfo
->bankWidth
*
3672 pTileInfo
->macroAspectRatio
;
3673 m_blockHeight
[equationIndex
] =
3674 MicroTileHeight
* pTileInfo
->bankHeight
* pTileInfo
->banks
/
3675 pTileInfo
->macroAspectRatio
;
3679 UINT_32 macroTileSize
=
3680 m_blockWidth
[equationIndex
] * m_blockHeight
[equationIndex
] *
3683 if (macroTileSize
< PrtTileSize
)
3685 UINT_32 numMacroTiles
= PrtTileSize
/ macroTileSize
;
3687 ADDR_ASSERT(macroTileSize
== (1u << equation
.numBits
));
3688 ADDR_ASSERT((PrtTileSize
% macroTileSize
) == 0);
3690 UINT_32 numBits
= Log2(numMacroTiles
);
3692 UINT_32 xStart
= Log2(m_blockWidth
[equationIndex
]) +
3695 m_blockWidth
[equationIndex
] *= numMacroTiles
;
3697 for (UINT_32 i
= 0; i
< numBits
; i
++)
3699 equation
.addr
[equation
.numBits
+ i
].valid
= 1;
3700 equation
.addr
[equation
.numBits
+ i
].index
= xStart
+ i
;
3703 equation
.numBits
+= numBits
;
3708 equationKeyTable
[equationIndex
] = key
;
3709 m_equationTable
[equationIndex
] = equation
;
3716 // Fill the index into the lookup table, if the combination is not supported
3717 // fill the invalid equation index
3718 m_equationLookupTable
[log2ElementBytes
][tileIndex
] = equationIndex
;
3721 if (m_chipFamily
== ADDR_CHIP_FAMILY_SI
)
3723 // For tile index 3 which is shared between PRT depth and uncompressed depth
3724 m_uncompressDepthEqIndex
= m_numEquations
;
3726 for (UINT_32 log2ElemBytes
= 0; log2ElemBytes
< MaxNumElementBytes
; log2ElemBytes
++)
3728 TileConfig tileConfig
= m_tileTable
[3];
3729 ADDR_EQUATION equation
;
3730 ADDR_E_RETURNCODE retCode
;
3732 memset(&equation
, 0, sizeof(ADDR_EQUATION
));
3734 retCode
= ComputeMacroTileEquation(log2ElemBytes
,
3740 if (retCode
== ADDR_OK
)
3742 UINT_32 equationIndex
= m_numEquations
;
3743 ADDR_ASSERT(equationIndex
< EquationTableSize
);
3745 m_blockSlices
[equationIndex
] = 1;
3747 const ADDR_TILEINFO
* pTileInfo
= &tileConfig
.info
;
3749 m_blockWidth
[equationIndex
] =
3750 HwlGetPipes(pTileInfo
) * MicroTileWidth
* pTileInfo
->bankWidth
*
3751 pTileInfo
->macroAspectRatio
;
3752 m_blockHeight
[equationIndex
] =
3753 MicroTileHeight
* pTileInfo
->bankHeight
* pTileInfo
->banks
/
3754 pTileInfo
->macroAspectRatio
;
3756 m_equationTable
[equationIndex
] = equation
;
3766 ****************************************************************************************************
3767 * SiLib::IsEquationSupported
3770 * Check if it is supported for given bpp and tile config to generate a equation.
3774 ****************************************************************************************************
3776 BOOL_32
SiLib::IsEquationSupported(
3777 UINT_32 bpp
, ///< Bits per pixel
3778 TileConfig tileConfig
, ///< Tile config
3779 INT_32 tileIndex
, ///< Tile index
3780 UINT_32 elementBytesLog2
///< Log2 of element bytes
3783 BOOL_32 supported
= TRUE
;
3785 // Linear tile mode is not supported in swizzle pattern equation
3786 if (IsLinear(tileConfig
.mode
))
3790 // These tile modes are for Tex2DArray and Tex3D which has depth (num_slice > 1) use,
3791 // which is not supported in swizzle pattern equation due to slice rotation
3792 else if ((tileConfig
.mode
== ADDR_TM_2D_TILED_THICK
) ||
3793 (tileConfig
.mode
== ADDR_TM_2D_TILED_XTHICK
) ||
3794 (tileConfig
.mode
== ADDR_TM_3D_TILED_THIN1
) ||
3795 (tileConfig
.mode
== ADDR_TM_3D_TILED_THICK
) ||
3796 (tileConfig
.mode
== ADDR_TM_3D_TILED_XTHICK
))
3800 // Only 8bpp(stencil), 16bpp and 32bpp is supported for depth
3801 else if ((tileConfig
.type
== ADDR_DEPTH_SAMPLE_ORDER
) && (bpp
> 32))
3805 // Tile split is not supported in swizzle pattern equation
3806 else if (IsMacroTiled(tileConfig
.mode
))
3808 UINT_32 thickness
= Thickness(tileConfig
.mode
);
3809 if (((bpp
>> 3) * MicroTilePixels
* thickness
) > tileConfig
.info
.tileSplitBytes
)
3814 if ((supported
== TRUE
) && (m_chipFamily
== ADDR_CHIP_FAMILY_SI
))
3816 supported
= m_EquationSupport
[tileIndex
][elementBytesLog2
];