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amd/addrlib: update Mesa's copy of addrlib
[mesa.git] / src / amd / addrlib / src / r800 / siaddrlib.cpp
1 /*
2 * Copyright © 2007-2018 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26
27 /**
28 ****************************************************************************************************
29 * @file siaddrlib.cpp
30 * @brief Contains the implementation for the SiLib class.
31 ****************************************************************************************************
32 */
33
34 #include "siaddrlib.h"
35 #include "si_gb_reg.h"
36
37 #include "amdgpu_asic_addr.h"
38
39 ////////////////////////////////////////////////////////////////////////////////////////////////////
40 ////////////////////////////////////////////////////////////////////////////////////////////////////
41 namespace Addr
42 {
43
44 /**
45 ****************************************************************************************************
46 * SiHwlInit
47 *
48 * @brief
49 * Creates an SiLib object.
50 *
51 * @return
52 * Returns an SiLib object pointer.
53 ****************************************************************************************************
54 */
55 Lib* SiHwlInit(const Client* pClient)
56 {
57 return V1::SiLib::CreateObj(pClient);
58 }
59
60 namespace V1
61 {
62
63 // We don't support MSAA for equation
64 const BOOL_32 SiLib::m_EquationSupport[SiLib::TileTableSize][SiLib::MaxNumElementBytes] =
65 {
66 {TRUE, TRUE, TRUE, FALSE, FALSE}, // 0, non-AA compressed depth or any stencil
67 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 1, 2xAA/4xAA compressed depth with or without stencil
68 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 2, 8xAA compressed depth with or without stencil
69 {FALSE, TRUE, FALSE, FALSE, FALSE}, // 3, 16 bpp depth PRT (non-MSAA), don't support uncompressed depth
70 {TRUE, TRUE, TRUE, FALSE, FALSE}, // 4, 1D depth
71 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 5, 16 bpp depth PRT (4xMSAA)
72 {FALSE, FALSE, TRUE, FALSE, FALSE}, // 6, 32 bpp depth PRT (non-MSAA)
73 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 7, 32 bpp depth PRT (4xMSAA)
74 {TRUE, TRUE, TRUE, TRUE, TRUE }, // 8, Linear
75 {TRUE, TRUE, TRUE, TRUE, TRUE }, // 9, 1D display
76 {TRUE, FALSE, FALSE, FALSE, FALSE}, // 10, 8 bpp color (displayable)
77 {FALSE, TRUE, FALSE, FALSE, FALSE}, // 11, 16 bpp color (displayable)
78 {FALSE, FALSE, TRUE, TRUE, FALSE}, // 12, 32/64 bpp color (displayable)
79 {TRUE, TRUE, TRUE, TRUE, TRUE }, // 13, 1D thin
80 {TRUE, FALSE, FALSE, FALSE, FALSE}, // 14, 8 bpp color non-displayable
81 {FALSE, TRUE, FALSE, FALSE, FALSE}, // 15, 16 bpp color non-displayable
82 {FALSE, FALSE, TRUE, FALSE, FALSE}, // 16, 32 bpp color non-displayable
83 {FALSE, FALSE, FALSE, TRUE, TRUE }, // 17, 64/128 bpp color non-displayable
84 {TRUE, TRUE, TRUE, TRUE, TRUE }, // 18, 1D THICK
85 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 19, 2D XTHICK
86 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 20, 2D THICK
87 {TRUE, FALSE, FALSE, FALSE, FALSE}, // 21, 8 bpp 2D PRTs (non-MSAA)
88 {FALSE, TRUE, FALSE, FALSE, FALSE}, // 22, 16 bpp 2D PRTs (non-MSAA)
89 {FALSE, FALSE, TRUE, FALSE, FALSE}, // 23, 32 bpp 2D PRTs (non-MSAA)
90 {FALSE, FALSE, FALSE, TRUE, FALSE}, // 24, 64 bpp 2D PRTs (non-MSAA)
91 {FALSE, FALSE, FALSE, FALSE, TRUE }, // 25, 128bpp 2D PRTs (non-MSAA)
92 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 26, none
93 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 27, none
94 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 28, none
95 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 29, none
96 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 30, 64bpp 2D PRTs (4xMSAA)
97 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 31, none
98 };
99
100 /**
101 ****************************************************************************************************
102 * SiLib::SiLib
103 *
104 * @brief
105 * Constructor
106 *
107 ****************************************************************************************************
108 */
109 SiLib::SiLib(const Client* pClient)
110 :
111 EgBasedLib(pClient),
112 m_noOfEntries(0),
113 m_numEquations(0)
114 {
115 m_class = SI_ADDRLIB;
116 memset(&m_settings, 0, sizeof(m_settings));
117 }
118
119 /**
120 ****************************************************************************************************
121 * SiLib::~SiLib
122 *
123 * @brief
124 * Destructor
125 ****************************************************************************************************
126 */
127 SiLib::~SiLib()
128 {
129 }
130
131 /**
132 ****************************************************************************************************
133 * SiLib::HwlGetPipes
134 *
135 * @brief
136 * Get number pipes
137 * @return
138 * num pipes
139 ****************************************************************************************************
140 */
141 UINT_32 SiLib::HwlGetPipes(
142 const ADDR_TILEINFO* pTileInfo ///< [in] Tile info
143 ) const
144 {
145 UINT_32 numPipes;
146
147 if (pTileInfo)
148 {
149 numPipes = GetPipePerSurf(pTileInfo->pipeConfig);
150 }
151 else
152 {
153 ADDR_ASSERT_ALWAYS();
154 numPipes = m_pipes; // Suppose we should still have a global pipes
155 }
156
157 return numPipes;
158 }
159
160 /**
161 ****************************************************************************************************
162 * SiLib::GetPipePerSurf
163 * @brief
164 * get pipe num base on inputing tileinfo->pipeconfig
165 * @return
166 * pipe number
167 ****************************************************************************************************
168 */
169 UINT_32 SiLib::GetPipePerSurf(
170 AddrPipeCfg pipeConfig ///< [in] pipe config
171 ) const
172 {
173 UINT_32 numPipes = 0;
174
175 switch (pipeConfig)
176 {
177 case ADDR_PIPECFG_P2:
178 numPipes = 2;
179 break;
180 case ADDR_PIPECFG_P4_8x16:
181 case ADDR_PIPECFG_P4_16x16:
182 case ADDR_PIPECFG_P4_16x32:
183 case ADDR_PIPECFG_P4_32x32:
184 numPipes = 4;
185 break;
186 case ADDR_PIPECFG_P8_16x16_8x16:
187 case ADDR_PIPECFG_P8_16x32_8x16:
188 case ADDR_PIPECFG_P8_32x32_8x16:
189 case ADDR_PIPECFG_P8_16x32_16x16:
190 case ADDR_PIPECFG_P8_32x32_16x16:
191 case ADDR_PIPECFG_P8_32x32_16x32:
192 case ADDR_PIPECFG_P8_32x64_32x32:
193 numPipes = 8;
194 break;
195 case ADDR_PIPECFG_P16_32x32_8x16:
196 case ADDR_PIPECFG_P16_32x32_16x16:
197 numPipes = 16;
198 break;
199 default:
200 ADDR_ASSERT(!"Invalid pipe config");
201 numPipes = m_pipes;
202 }
203 return numPipes;
204 }
205
206 /**
207 ****************************************************************************************************
208 * SiLib::ComputeBankEquation
209 *
210 * @brief
211 * Compute bank equation
212 *
213 * @return
214 * If equation can be computed
215 ****************************************************************************************************
216 */
217 ADDR_E_RETURNCODE SiLib::ComputeBankEquation(
218 UINT_32 log2BytesPP, ///< [in] log2 of bytes per pixel
219 UINT_32 threshX, ///< [in] threshold for x channel
220 UINT_32 threshY, ///< [in] threshold for y channel
221 ADDR_TILEINFO* pTileInfo, ///< [in] tile info
222 ADDR_EQUATION* pEquation ///< [out] bank equation
223 ) const
224 {
225 ADDR_E_RETURNCODE retCode = ADDR_OK;
226
227 UINT_32 pipes = HwlGetPipes(pTileInfo);
228 UINT_32 bankXStart = 3 + Log2(pipes) + Log2(pTileInfo->bankWidth);
229 UINT_32 bankYStart = 3 + Log2(pTileInfo->bankHeight);
230
231 ADDR_CHANNEL_SETTING x3 = InitChannel(1, 0, log2BytesPP + bankXStart);
232 ADDR_CHANNEL_SETTING x4 = InitChannel(1, 0, log2BytesPP + bankXStart + 1);
233 ADDR_CHANNEL_SETTING x5 = InitChannel(1, 0, log2BytesPP + bankXStart + 2);
234 ADDR_CHANNEL_SETTING x6 = InitChannel(1, 0, log2BytesPP + bankXStart + 3);
235 ADDR_CHANNEL_SETTING y3 = InitChannel(1, 1, bankYStart);
236 ADDR_CHANNEL_SETTING y4 = InitChannel(1, 1, bankYStart + 1);
237 ADDR_CHANNEL_SETTING y5 = InitChannel(1, 1, bankYStart + 2);
238 ADDR_CHANNEL_SETTING y6 = InitChannel(1, 1, bankYStart + 3);
239
240 x3.value = (threshX > bankXStart) ? x3.value : 0;
241 x4.value = (threshX > bankXStart + 1) ? x4.value : 0;
242 x5.value = (threshX > bankXStart + 2) ? x5.value : 0;
243 x6.value = (threshX > bankXStart + 3) ? x6.value : 0;
244 y3.value = (threshY > bankYStart) ? y3.value : 0;
245 y4.value = (threshY > bankYStart + 1) ? y4.value : 0;
246 y5.value = (threshY > bankYStart + 2) ? y5.value : 0;
247 y6.value = (threshY > bankYStart + 3) ? y6.value : 0;
248
249 switch (pTileInfo->banks)
250 {
251 case 16:
252 if (pTileInfo->macroAspectRatio == 1)
253 {
254 pEquation->addr[0] = y6;
255 pEquation->xor1[0] = x3;
256 pEquation->addr[1] = y5;
257 pEquation->xor1[1] = y6;
258 pEquation->xor2[1] = x4;
259 pEquation->addr[2] = y4;
260 pEquation->xor1[2] = x5;
261 pEquation->addr[3] = y3;
262 pEquation->xor1[3] = x6;
263 }
264 else if (pTileInfo->macroAspectRatio == 2)
265 {
266 pEquation->addr[0] = x3;
267 pEquation->xor1[0] = y6;
268 pEquation->addr[1] = y5;
269 pEquation->xor1[1] = y6;
270 pEquation->xor2[1] = x4;
271 pEquation->addr[2] = y4;
272 pEquation->xor1[2] = x5;
273 pEquation->addr[3] = y3;
274 pEquation->xor1[3] = x6;
275 }
276 else if (pTileInfo->macroAspectRatio == 4)
277 {
278 pEquation->addr[0] = x3;
279 pEquation->xor1[0] = y6;
280 pEquation->addr[1] = x4;
281 pEquation->xor1[1] = y5;
282 pEquation->xor2[1] = y6;
283 pEquation->addr[2] = y4;
284 pEquation->xor1[2] = x5;
285 pEquation->addr[3] = y3;
286 pEquation->xor1[3] = x6;
287 }
288 else if (pTileInfo->macroAspectRatio == 8)
289 {
290 pEquation->addr[0] = x3;
291 pEquation->xor1[0] = y6;
292 pEquation->addr[1] = x4;
293 pEquation->xor1[1] = y5;
294 pEquation->xor2[1] = y6;
295 pEquation->addr[2] = x5;
296 pEquation->xor1[2] = y4;
297 pEquation->addr[3] = y3;
298 pEquation->xor1[3] = x6;
299 }
300 else
301 {
302 ADDR_ASSERT_ALWAYS();
303 }
304 pEquation->numBits = 4;
305 break;
306 case 8:
307 if (pTileInfo->macroAspectRatio == 1)
308 {
309 pEquation->addr[0] = y5;
310 pEquation->xor1[0] = x3;
311 pEquation->addr[1] = y4;
312 pEquation->xor1[1] = y5;
313 pEquation->xor2[1] = x4;
314 pEquation->addr[2] = y3;
315 pEquation->xor1[2] = x5;
316 }
317 else if (pTileInfo->macroAspectRatio == 2)
318 {
319 pEquation->addr[0] = x3;
320 pEquation->xor1[0] = y5;
321 pEquation->addr[1] = y4;
322 pEquation->xor1[1] = y5;
323 pEquation->xor2[1] = x4;
324 pEquation->addr[2] = y3;
325 pEquation->xor1[2] = x5;
326 }
327 else if (pTileInfo->macroAspectRatio == 4)
328 {
329 pEquation->addr[0] = x3;
330 pEquation->xor1[0] = y5;
331 pEquation->addr[1] = x4;
332 pEquation->xor1[1] = y4;
333 pEquation->xor2[1] = y5;
334 pEquation->addr[2] = y3;
335 pEquation->xor1[2] = x5;
336 }
337 else
338 {
339 ADDR_ASSERT_ALWAYS();
340 }
341 pEquation->numBits = 3;
342 break;
343 case 4:
344 if (pTileInfo->macroAspectRatio == 1)
345 {
346 pEquation->addr[0] = y4;
347 pEquation->xor1[0] = x3;
348 pEquation->addr[1] = y3;
349 pEquation->xor1[1] = x4;
350 }
351 else if (pTileInfo->macroAspectRatio == 2)
352 {
353 pEquation->addr[0] = x3;
354 pEquation->xor1[0] = y4;
355 pEquation->addr[1] = y3;
356 pEquation->xor1[1] = x4;
357 }
358 else
359 {
360 pEquation->addr[0] = x3;
361 pEquation->xor1[0] = y4;
362 pEquation->addr[1] = x4;
363 pEquation->xor1[1] = y3;
364 }
365 pEquation->numBits = 2;
366 break;
367 case 2:
368 if (pTileInfo->macroAspectRatio == 1)
369 {
370 pEquation->addr[0] = y3;
371 pEquation->xor1[0] = x3;
372 }
373 else
374 {
375 pEquation->addr[0] = x3;
376 pEquation->xor1[0] = y3;
377 }
378 pEquation->numBits = 1;
379 break;
380 default:
381 pEquation->numBits = 0;
382 retCode = ADDR_NOTSUPPORTED;
383 ADDR_ASSERT_ALWAYS();
384 break;
385 }
386
387 for (UINT_32 i = 0; i < pEquation->numBits; i++)
388 {
389 if (pEquation->addr[i].value == 0)
390 {
391 if (pEquation->xor1[i].value == 0)
392 {
393 // 00X -> X00
394 pEquation->addr[i].value = pEquation->xor2[i].value;
395 pEquation->xor2[i].value = 0;
396 }
397 else
398 {
399 pEquation->addr[i].value = pEquation->xor1[i].value;
400
401 if (pEquation->xor2[i].value != 0)
402 {
403 // 0XY -> XY0
404 pEquation->xor1[i].value = pEquation->xor2[i].value;
405 pEquation->xor2[i].value = 0;
406 }
407 else
408 {
409 // 0X0 -> X00
410 pEquation->xor1[i].value = 0;
411 }
412 }
413 }
414 else if (pEquation->xor1[i].value == 0)
415 {
416 if (pEquation->xor2[i].value != 0)
417 {
418 // X0Y -> XY0
419 pEquation->xor1[i].value = pEquation->xor2[i].value;
420 pEquation->xor2[i].value = 0;
421 }
422 }
423 }
424
425 if ((pTileInfo->bankWidth == 1) &&
426 ((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) ||
427 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)))
428 {
429 retCode = ADDR_NOTSUPPORTED;
430 }
431
432 return retCode;
433 }
434
435 /**
436 ****************************************************************************************************
437 * SiLib::ComputePipeEquation
438 *
439 * @brief
440 * Compute pipe equation
441 *
442 * @return
443 * If equation can be computed
444 ****************************************************************************************************
445 */
446 ADDR_E_RETURNCODE SiLib::ComputePipeEquation(
447 UINT_32 log2BytesPP, ///< [in] Log2 of bytes per pixel
448 UINT_32 threshX, ///< [in] Threshold for X channel
449 UINT_32 threshY, ///< [in] Threshold for Y channel
450 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info
451 ADDR_EQUATION* pEquation ///< [out] Pipe configure
452 ) const
453 {
454 ADDR_E_RETURNCODE retCode = ADDR_OK;
455
456 ADDR_CHANNEL_SETTING* pAddr = pEquation->addr;
457 ADDR_CHANNEL_SETTING* pXor1 = pEquation->xor1;
458 ADDR_CHANNEL_SETTING* pXor2 = pEquation->xor2;
459
460 ADDR_CHANNEL_SETTING x3 = InitChannel(1, 0, 3 + log2BytesPP);
461 ADDR_CHANNEL_SETTING x4 = InitChannel(1, 0, 4 + log2BytesPP);
462 ADDR_CHANNEL_SETTING x5 = InitChannel(1, 0, 5 + log2BytesPP);
463 ADDR_CHANNEL_SETTING x6 = InitChannel(1, 0, 6 + log2BytesPP);
464 ADDR_CHANNEL_SETTING y3 = InitChannel(1, 1, 3);
465 ADDR_CHANNEL_SETTING y4 = InitChannel(1, 1, 4);
466 ADDR_CHANNEL_SETTING y5 = InitChannel(1, 1, 5);
467 ADDR_CHANNEL_SETTING y6 = InitChannel(1, 1, 6);
468
469 x3.value = (threshX > 3) ? x3.value : 0;
470 x4.value = (threshX > 4) ? x4.value : 0;
471 x5.value = (threshX > 5) ? x5.value : 0;
472 x6.value = (threshX > 6) ? x6.value : 0;
473 y3.value = (threshY > 3) ? y3.value : 0;
474 y4.value = (threshY > 4) ? y4.value : 0;
475 y5.value = (threshY > 5) ? y5.value : 0;
476 y6.value = (threshY > 6) ? y6.value : 0;
477
478 switch (pTileInfo->pipeConfig)
479 {
480 case ADDR_PIPECFG_P2:
481 pAddr[0] = x3;
482 pXor1[0] = y3;
483 pEquation->numBits = 1;
484 break;
485 case ADDR_PIPECFG_P4_8x16:
486 pAddr[0] = x4;
487 pXor1[0] = y3;
488 pAddr[1] = x3;
489 pXor1[1] = y4;
490 pEquation->numBits = 2;
491 break;
492 case ADDR_PIPECFG_P4_16x16:
493 pAddr[0] = x3;
494 pXor1[0] = y3;
495 pXor2[0] = x4;
496 pAddr[1] = x4;
497 pXor1[1] = y4;
498 pEquation->numBits = 2;
499 break;
500 case ADDR_PIPECFG_P4_16x32:
501 pAddr[0] = x3;
502 pXor1[0] = y3;
503 pXor2[0] = x4;
504 pAddr[1] = x4;
505 pXor1[1] = y5;
506 pEquation->numBits = 2;
507 break;
508 case ADDR_PIPECFG_P4_32x32:
509 pAddr[0] = x3;
510 pXor1[0] = y3;
511 pXor2[0] = x5;
512 pAddr[1] = x5;
513 pXor1[1] = y5;
514 pEquation->numBits = 2;
515 break;
516 case ADDR_PIPECFG_P8_16x16_8x16:
517 pAddr[0] = x4;
518 pXor1[0] = y3;
519 pXor2[0] = x5;
520 pAddr[1] = x3;
521 pXor1[1] = y5;
522 pEquation->numBits = 3;
523 break;
524 case ADDR_PIPECFG_P8_16x32_8x16:
525 pAddr[0] = x4;
526 pXor1[0] = y3;
527 pXor2[0] = x5;
528 pAddr[1] = x3;
529 pXor1[1] = y4;
530 pAddr[2] = x4;
531 pXor1[2] = y5;
532 pEquation->numBits = 3;
533 break;
534 case ADDR_PIPECFG_P8_16x32_16x16:
535 pAddr[0] = x3;
536 pXor1[0] = y3;
537 pXor2[0] = x4;
538 pAddr[1] = x5;
539 pXor1[1] = y4;
540 pAddr[2] = x4;
541 pXor1[2] = y5;
542 pEquation->numBits = 3;
543 break;
544 case ADDR_PIPECFG_P8_32x32_8x16:
545 pAddr[0] = x4;
546 pXor1[0] = y3;
547 pXor2[0] = x5;
548 pAddr[1] = x3;
549 pXor1[1] = y4;
550 pAddr[2] = x5;
551 pXor1[2] = y5;
552 pEquation->numBits = 3;
553 break;
554 case ADDR_PIPECFG_P8_32x32_16x16:
555 pAddr[0] = x3;
556 pXor1[0] = y3;
557 pXor2[0] = x4;
558 pAddr[1] = x4;
559 pXor1[1] = y4;
560 pAddr[2] = x5;
561 pXor1[2] = y5;
562 pEquation->numBits = 3;
563 break;
564 case ADDR_PIPECFG_P8_32x32_16x32:
565 pAddr[0] = x3;
566 pXor1[0] = y3;
567 pXor2[0] = x4;
568 pAddr[1] = x4;
569 pXor1[1] = y6;
570 pAddr[2] = x5;
571 pXor1[2] = y5;
572 pEquation->numBits = 3;
573 break;
574 case ADDR_PIPECFG_P8_32x64_32x32:
575 pAddr[0] = x3;
576 pXor1[0] = y3;
577 pXor2[0] = x5;
578 pAddr[1] = x6;
579 pXor1[1] = y5;
580 pAddr[2] = x5;
581 pXor1[2] = y6;
582 pEquation->numBits = 3;
583 break;
584 case ADDR_PIPECFG_P16_32x32_8x16:
585 pAddr[0] = x4;
586 pXor1[0] = y3;
587 pAddr[1] = x3;
588 pXor1[1] = y4;
589 pAddr[2] = x5;
590 pXor1[2] = y6;
591 pAddr[3] = x6;
592 pXor1[3] = y5;
593 pEquation->numBits = 4;
594 break;
595 case ADDR_PIPECFG_P16_32x32_16x16:
596 pAddr[0] = x3;
597 pXor1[0] = y3;
598 pXor2[0] = x4;
599 pAddr[1] = x4;
600 pXor1[1] = y4;
601 pAddr[2] = x5;
602 pXor1[2] = y6;
603 pAddr[3] = x6;
604 pXor1[3] = y5;
605 pEquation->numBits = 4;
606 break;
607 default:
608 ADDR_UNHANDLED_CASE();
609 pEquation->numBits = 0;
610 retCode = ADDR_NOTSUPPORTED;
611 break;
612 }
613
614 if (m_settings.isVegaM && (pEquation->numBits == 4))
615 {
616 ADDR_CHANNEL_SETTING addeMsb = pAddr[0];
617 ADDR_CHANNEL_SETTING xor1Msb = pXor1[0];
618 ADDR_CHANNEL_SETTING xor2Msb = pXor2[0];
619
620 pAddr[0] = pAddr[1];
621 pXor1[0] = pXor1[1];
622 pXor2[0] = pXor2[1];
623
624 pAddr[1] = pAddr[2];
625 pXor1[1] = pXor1[2];
626 pXor2[1] = pXor2[2];
627
628 pAddr[2] = pAddr[3];
629 pXor1[2] = pXor1[3];
630 pXor2[2] = pXor2[3];
631
632 pAddr[3] = addeMsb;
633 pXor1[3] = xor1Msb;
634 pXor2[3] = xor2Msb;
635 }
636
637 for (UINT_32 i = 0; i < pEquation->numBits; i++)
638 {
639 if (pAddr[i].value == 0)
640 {
641 if (pXor1[i].value == 0)
642 {
643 pAddr[i].value = pXor2[i].value;
644 }
645 else
646 {
647 pAddr[i].value = pXor1[i].value;
648 pXor1[i].value = 0;
649 }
650 }
651 }
652
653 return retCode;
654 }
655
656 /**
657 ****************************************************************************************************
658 * SiLib::ComputePipeFromCoord
659 *
660 * @brief
661 * Compute pipe number from coordinates
662 * @return
663 * Pipe number
664 ****************************************************************************************************
665 */
666 UINT_32 SiLib::ComputePipeFromCoord(
667 UINT_32 x, ///< [in] x coordinate
668 UINT_32 y, ///< [in] y coordinate
669 UINT_32 slice, ///< [in] slice index
670 AddrTileMode tileMode, ///< [in] tile mode
671 UINT_32 pipeSwizzle, ///< [in] pipe swizzle
672 BOOL_32 ignoreSE, ///< [in] TRUE if shader engines are ignored
673 ADDR_TILEINFO* pTileInfo ///< [in] Tile info
674 ) const
675 {
676 UINT_32 pipe;
677 UINT_32 pipeBit0 = 0;
678 UINT_32 pipeBit1 = 0;
679 UINT_32 pipeBit2 = 0;
680 UINT_32 pipeBit3 = 0;
681 UINT_32 sliceRotation;
682 UINT_32 numPipes = 0;
683
684 UINT_32 tx = x / MicroTileWidth;
685 UINT_32 ty = y / MicroTileHeight;
686 UINT_32 x3 = _BIT(tx,0);
687 UINT_32 x4 = _BIT(tx,1);
688 UINT_32 x5 = _BIT(tx,2);
689 UINT_32 x6 = _BIT(tx,3);
690 UINT_32 y3 = _BIT(ty,0);
691 UINT_32 y4 = _BIT(ty,1);
692 UINT_32 y5 = _BIT(ty,2);
693 UINT_32 y6 = _BIT(ty,3);
694
695 switch (pTileInfo->pipeConfig)
696 {
697 case ADDR_PIPECFG_P2:
698 pipeBit0 = x3 ^ y3;
699 numPipes = 2;
700 break;
701 case ADDR_PIPECFG_P4_8x16:
702 pipeBit0 = x4 ^ y3;
703 pipeBit1 = x3 ^ y4;
704 numPipes = 4;
705 break;
706 case ADDR_PIPECFG_P4_16x16:
707 pipeBit0 = x3 ^ y3 ^ x4;
708 pipeBit1 = x4 ^ y4;
709 numPipes = 4;
710 break;
711 case ADDR_PIPECFG_P4_16x32:
712 pipeBit0 = x3 ^ y3 ^ x4;
713 pipeBit1 = x4 ^ y5;
714 numPipes = 4;
715 break;
716 case ADDR_PIPECFG_P4_32x32:
717 pipeBit0 = x3 ^ y3 ^ x5;
718 pipeBit1 = x5 ^ y5;
719 numPipes = 4;
720 break;
721 case ADDR_PIPECFG_P8_16x16_8x16:
722 pipeBit0 = x4 ^ y3 ^ x5;
723 pipeBit1 = x3 ^ y5;
724 numPipes = 8;
725 break;
726 case ADDR_PIPECFG_P8_16x32_8x16:
727 pipeBit0 = x4 ^ y3 ^ x5;
728 pipeBit1 = x3 ^ y4;
729 pipeBit2 = x4 ^ y5;
730 numPipes = 8;
731 break;
732 case ADDR_PIPECFG_P8_16x32_16x16:
733 pipeBit0 = x3 ^ y3 ^ x4;
734 pipeBit1 = x5 ^ y4;
735 pipeBit2 = x4 ^ y5;
736 numPipes = 8;
737 break;
738 case ADDR_PIPECFG_P8_32x32_8x16:
739 pipeBit0 = x4 ^ y3 ^ x5;
740 pipeBit1 = x3 ^ y4;
741 pipeBit2 = x5 ^ y5;
742 numPipes = 8;
743 break;
744 case ADDR_PIPECFG_P8_32x32_16x16:
745 pipeBit0 = x3 ^ y3 ^ x4;
746 pipeBit1 = x4 ^ y4;
747 pipeBit2 = x5 ^ y5;
748 numPipes = 8;
749 break;
750 case ADDR_PIPECFG_P8_32x32_16x32:
751 pipeBit0 = x3 ^ y3 ^ x4;
752 pipeBit1 = x4 ^ y6;
753 pipeBit2 = x5 ^ y5;
754 numPipes = 8;
755 break;
756 case ADDR_PIPECFG_P8_32x64_32x32:
757 pipeBit0 = x3 ^ y3 ^ x5;
758 pipeBit1 = x6 ^ y5;
759 pipeBit2 = x5 ^ y6;
760 numPipes = 8;
761 break;
762 case ADDR_PIPECFG_P16_32x32_8x16:
763 pipeBit0 = x4 ^ y3;
764 pipeBit1 = x3 ^ y4;
765 pipeBit2 = x5 ^ y6;
766 pipeBit3 = x6 ^ y5;
767 numPipes = 16;
768 break;
769 case ADDR_PIPECFG_P16_32x32_16x16:
770 pipeBit0 = x3 ^ y3 ^ x4;
771 pipeBit1 = x4 ^ y4;
772 pipeBit2 = x5 ^ y6;
773 pipeBit3 = x6 ^ y5;
774 numPipes = 16;
775 break;
776 default:
777 ADDR_UNHANDLED_CASE();
778 break;
779 }
780
781 if (m_settings.isVegaM && (numPipes == 16))
782 {
783 UINT_32 pipeMsb = pipeBit0;
784 pipeBit0 = pipeBit1;
785 pipeBit1 = pipeBit2;
786 pipeBit2 = pipeBit3;
787 pipeBit3 = pipeMsb;
788 }
789
790 pipe = pipeBit0 | (pipeBit1 << 1) | (pipeBit2 << 2) | (pipeBit3 << 3);
791
792 UINT_32 microTileThickness = Thickness(tileMode);
793
794 //
795 // Apply pipe rotation for the slice.
796 //
797 switch (tileMode)
798 {
799 case ADDR_TM_3D_TILED_THIN1: //fall through thin
800 case ADDR_TM_3D_TILED_THICK: //fall through thick
801 case ADDR_TM_3D_TILED_XTHICK:
802 sliceRotation =
803 Max(1, static_cast<INT_32>(numPipes / 2) - 1) * (slice / microTileThickness);
804 break;
805 default:
806 sliceRotation = 0;
807 break;
808 }
809 pipeSwizzle += sliceRotation;
810 pipeSwizzle &= (numPipes - 1);
811
812 pipe = pipe ^ pipeSwizzle;
813
814 return pipe;
815 }
816
817 /**
818 ****************************************************************************************************
819 * SiLib::ComputeTileCoordFromPipeAndElemIdx
820 *
821 * @brief
822 * Compute (x,y) of a tile within a macro tile from address
823 * @return
824 * Pipe number
825 ****************************************************************************************************
826 */
827 VOID SiLib::ComputeTileCoordFromPipeAndElemIdx(
828 UINT_32 elemIdx, ///< [in] per pipe element index within a macro tile
829 UINT_32 pipe, ///< [in] pipe index
830 AddrPipeCfg pipeCfg, ///< [in] pipe config
831 UINT_32 pitchInMacroTile, ///< [in] surface pitch in macro tile
832 UINT_32 x, ///< [in] x coordinate of the (0,0) tile in a macro tile
833 UINT_32 y, ///< [in] y coordinate of the (0,0) tile in a macro tile
834 UINT_32* pX, ///< [out] x coordinate
835 UINT_32* pY ///< [out] y coordinate
836 ) const
837 {
838 UINT_32 pipebit0 = _BIT(pipe,0);
839 UINT_32 pipebit1 = _BIT(pipe,1);
840 UINT_32 pipebit2 = _BIT(pipe,2);
841 UINT_32 pipebit3 = _BIT(pipe,3);
842 UINT_32 elemIdx0 = _BIT(elemIdx,0);
843 UINT_32 elemIdx1 = _BIT(elemIdx,1);
844 UINT_32 elemIdx2 = _BIT(elemIdx,2);
845 UINT_32 x3 = 0;
846 UINT_32 x4 = 0;
847 UINT_32 x5 = 0;
848 UINT_32 x6 = 0;
849 UINT_32 y3 = 0;
850 UINT_32 y4 = 0;
851 UINT_32 y5 = 0;
852 UINT_32 y6 = 0;
853
854 switch(pipeCfg)
855 {
856 case ADDR_PIPECFG_P2:
857 x4 = elemIdx2;
858 y4 = elemIdx1 ^ x4;
859 y3 = elemIdx0 ^ x4;
860 x3 = pipebit0 ^ y3;
861 *pY = Bits2Number(2, y4, y3);
862 *pX = Bits2Number(2, x4, x3);
863 break;
864 case ADDR_PIPECFG_P4_8x16:
865 x4 = elemIdx1;
866 y4 = elemIdx0 ^ x4;
867 x3 = pipebit1 ^ y4;
868 y3 = pipebit0 ^ x4;
869 *pY = Bits2Number(2, y4, y3);
870 *pX = Bits2Number(2, x4, x3);
871 break;
872 case ADDR_PIPECFG_P4_16x16:
873 x4 = elemIdx1;
874 y3 = elemIdx0 ^ x4;
875 y4 = pipebit1 ^ x4;
876 x3 = pipebit0 ^ y3 ^ x4;
877 *pY = Bits2Number(2, y4, y3);
878 *pX = Bits2Number(2, x4, x3);
879 break;
880 case ADDR_PIPECFG_P4_16x32:
881 x3 = elemIdx0 ^ pipebit0;
882 y5 = _BIT(y,5);
883 x4 = pipebit1 ^ y5;
884 y3 = pipebit0 ^ x3 ^ x4;
885 y4 = elemIdx1 ^ x4;
886 *pY = Bits2Number(2, y4, y3);
887 *pX = Bits2Number(2, x4, x3);
888 break;
889 case ADDR_PIPECFG_P4_32x32:
890 x4 = elemIdx2;
891 y3 = elemIdx0 ^ x4;
892 y4 = elemIdx1 ^ x4;
893 if((pitchInMacroTile % 2) == 0)
894 { //even
895 y5 = _BIT(y,5);
896 x5 = pipebit1 ^ y5;
897 x3 = pipebit0 ^ y3 ^ x5;
898 *pY = Bits2Number(2, y4, y3);
899 *pX = Bits2Number(3, x5, x4, x3);
900 }
901 else
902 { //odd
903 x5 = _BIT(x,5);
904 x3 = pipebit0 ^ y3 ^ x5;
905 *pY = Bits2Number(2, y4, y3);
906 *pX = Bits2Number(2, x4, x3);
907 }
908 break;
909 case ADDR_PIPECFG_P8_16x16_8x16:
910 x4 = elemIdx0;
911 y5 = _BIT(y,5);
912 x5 = _BIT(x,5);
913 x3 = pipebit1 ^ y5;
914 y4 = pipebit2 ^ x4;
915 y3 = pipebit0 ^ x5 ^ x4;
916 *pY = Bits2Number(2, y4, y3);
917 *pX = Bits2Number(2, x4, x3);
918 break;
919 case ADDR_PIPECFG_P8_16x32_8x16:
920 x3 = elemIdx0;
921 y4 = pipebit1 ^ x3;
922 y5 = _BIT(y,5);
923 x5 = _BIT(x,5);
924 x4 = pipebit2 ^ y5;
925 y3 = pipebit0 ^ x4 ^ x5;
926 *pY = Bits2Number(2, y4, y3);
927 *pX = Bits2Number(2, x4, x3);
928 break;
929 case ADDR_PIPECFG_P8_32x32_8x16:
930 x4 = elemIdx1;
931 y4 = elemIdx0 ^ x4;
932 x3 = pipebit1 ^ y4;
933 if((pitchInMacroTile % 2) == 0)
934 { //even
935 y5 = _BIT(y,5);
936 x5 = _BIT(x,5);
937 x5 = pipebit2 ^ y5;
938 y3 = pipebit0 ^ x4 ^ x5;
939 *pY = Bits2Number(2, y4, y3);
940 *pX = Bits2Number(3, x5, x4, x3);
941 }
942 else
943 { //odd
944 x5 = _BIT(x,5);
945 y3 = pipebit0 ^ x4 ^ x5;
946 *pY = Bits2Number(2, y4, y3);
947 *pX = Bits2Number(2, x4, x3);
948 }
949 break;
950 case ADDR_PIPECFG_P8_16x32_16x16:
951 x3 = elemIdx0;
952 x5 = _BIT(x,5);
953 y5 = _BIT(y,5);
954 x4 = pipebit2 ^ y5;
955 y4 = pipebit1 ^ x5;
956 y3 = pipebit0 ^ x3 ^ x4;
957 *pY = Bits2Number(2, y4, y3);
958 *pX = Bits2Number(2, x4, x3);
959 break;
960 case ADDR_PIPECFG_P8_32x32_16x16:
961 x4 = elemIdx1;
962 y3 = elemIdx0 ^ x4;
963 x3 = y3^x4^pipebit0;
964 y4 = pipebit1 ^ x4;
965 if((pitchInMacroTile % 2) == 0)
966 { //even
967 y5 = _BIT(y,5);
968 x5 = pipebit2 ^ y5;
969 *pY = Bits2Number(2, y4, y3);
970 *pX = Bits2Number(3, x5, x4, x3);
971 }
972 else
973 { //odd
974 *pY = Bits2Number(2, y4, y3);
975 *pX = Bits2Number(2, x4, x3);
976 }
977 break;
978 case ADDR_PIPECFG_P8_32x32_16x32:
979 if((pitchInMacroTile % 2) == 0)
980 { //even
981 y5 = _BIT(y,5);
982 y6 = _BIT(y,6);
983 x4 = pipebit1 ^ y6;
984 y3 = elemIdx0 ^ x4;
985 y4 = elemIdx1 ^ x4;
986 x3 = pipebit0 ^ y3 ^ x4;
987 x5 = pipebit2 ^ y5;
988 *pY = Bits2Number(2, y4, y3);
989 *pX = Bits2Number(3, x5, x4, x3);
990 }
991 else
992 { //odd
993 y6 = _BIT(y,6);
994 x4 = pipebit1 ^ y6;
995 y3 = elemIdx0 ^ x4;
996 y4 = elemIdx1 ^ x4;
997 x3 = pipebit0 ^ y3 ^ x4;
998 *pY = Bits2Number(2, y4, y3);
999 *pX = Bits2Number(2, x4, x3);
1000 }
1001 break;
1002 case ADDR_PIPECFG_P8_32x64_32x32:
1003 x4 = elemIdx2;
1004 y3 = elemIdx0 ^ x4;
1005 y4 = elemIdx1 ^ x4;
1006 if((pitchInMacroTile % 4) == 0)
1007 { //multiple of 4
1008 y5 = _BIT(y,5);
1009 y6 = _BIT(y,6);
1010 x5 = pipebit2 ^ y6;
1011 x6 = pipebit1 ^ y5;
1012 x3 = pipebit0 ^ y3 ^ x5;
1013 *pY = Bits2Number(2, y4, y3);
1014 *pX = Bits2Number(4, x6, x5, x4, x3);
1015 }
1016 else
1017 {
1018 y6 = _BIT(y,6);
1019 x5 = pipebit2 ^ y6;
1020 x3 = pipebit0 ^ y3 ^ x5;
1021 *pY = Bits2Number(2, y4, y3);
1022 *pX = Bits2Number(3, x5, x4, x3);
1023 }
1024 break;
1025 case ADDR_PIPECFG_P16_32x32_8x16:
1026 x4 = elemIdx1;
1027 y4 = elemIdx0 ^ x4;
1028 y3 = pipebit0 ^ x4;
1029 x3 = pipebit1 ^ y4;
1030 if((pitchInMacroTile % 4) == 0)
1031 { //multiple of 4
1032 y5 = _BIT(y,5);
1033 y6 = _BIT(y,6);
1034 x5 = pipebit2 ^ y6;
1035 x6 = pipebit3 ^ y5;
1036 *pY = Bits2Number(2, y4, y3);
1037 *pX = Bits2Number(4, x6, x5,x4, x3);
1038 }
1039 else
1040 {
1041 y6 = _BIT(y,6);
1042 x5 = pipebit2 ^ y6;
1043 *pY = Bits2Number(2, y4, y3);
1044 *pX = Bits2Number(3, x5, x4, x3);
1045 }
1046 break;
1047 case ADDR_PIPECFG_P16_32x32_16x16:
1048 x4 = elemIdx1;
1049 y3 = elemIdx0 ^ x4;
1050 y4 = pipebit1 ^ x4;
1051 x3 = pipebit0 ^ y3 ^ x4;
1052 if((pitchInMacroTile % 4) == 0)
1053 { //multiple of 4
1054 y5 = _BIT(y,5);
1055 y6 = _BIT(y,6);
1056 x5 = pipebit2 ^ y6;
1057 x6 = pipebit3 ^ y5;
1058 *pY = Bits2Number(2, y4, y3);
1059 *pX = Bits2Number(4, x6, x5, x4, x3);
1060 }
1061 else
1062 {
1063 y6 = _BIT(y,6);
1064 x5 = pipebit2 ^ y6;
1065 *pY = Bits2Number(2, y4, y3);
1066 *pX = Bits2Number(3, x5, x4, x3);
1067 }
1068 break;
1069 default:
1070 ADDR_UNHANDLED_CASE();
1071 }
1072 }
1073
1074 /**
1075 ****************************************************************************************************
1076 * SiLib::TileCoordToMaskElementIndex
1077 *
1078 * @brief
1079 * Compute element index from coordinates in tiles
1080 * @return
1081 * Element index
1082 ****************************************************************************************************
1083 */
1084 UINT_32 SiLib::TileCoordToMaskElementIndex(
1085 UINT_32 tx, ///< [in] x coord, in Tiles
1086 UINT_32 ty, ///< [in] y coord, in Tiles
1087 AddrPipeCfg pipeConfig, ///< [in] pipe config
1088 UINT_32* macroShift, ///< [out] macro shift
1089 UINT_32* elemIdxBits ///< [out] tile offset bits
1090 ) const
1091 {
1092 UINT_32 elemIdx = 0;
1093 UINT_32 elemIdx0, elemIdx1, elemIdx2;
1094 UINT_32 tx0, tx1;
1095 UINT_32 ty0, ty1;
1096
1097 tx0 = _BIT(tx,0);
1098 tx1 = _BIT(tx,1);
1099 ty0 = _BIT(ty,0);
1100 ty1 = _BIT(ty,1);
1101
1102 switch(pipeConfig)
1103 {
1104 case ADDR_PIPECFG_P2:
1105 *macroShift = 3;
1106 *elemIdxBits =3;
1107 elemIdx2 = tx1;
1108 elemIdx1 = tx1 ^ ty1;
1109 elemIdx0 = tx1 ^ ty0;
1110 elemIdx = Bits2Number(3,elemIdx2,elemIdx1,elemIdx0);
1111 break;
1112 case ADDR_PIPECFG_P4_8x16:
1113 *macroShift = 2;
1114 *elemIdxBits =2;
1115 elemIdx1 = tx1;
1116 elemIdx0 = tx1 ^ ty1;
1117 elemIdx = Bits2Number(2,elemIdx1,elemIdx0);
1118 break;
1119 case ADDR_PIPECFG_P4_16x16:
1120 *macroShift = 2;
1121 *elemIdxBits =2;
1122 elemIdx0 = tx1^ty0;
1123 elemIdx1 = tx1;
1124 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1125 break;
1126 case ADDR_PIPECFG_P4_16x32:
1127 *macroShift = 2;
1128 *elemIdxBits =2;
1129 elemIdx0 = tx1^ty0;
1130 elemIdx1 = tx1^ty1;
1131 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1132 break;
1133 case ADDR_PIPECFG_P4_32x32:
1134 *macroShift = 2;
1135 *elemIdxBits =3;
1136 elemIdx0 = tx1^ty0;
1137 elemIdx1 = tx1^ty1;
1138 elemIdx2 = tx1;
1139 elemIdx = Bits2Number(3, elemIdx2, elemIdx1, elemIdx0);
1140 break;
1141 case ADDR_PIPECFG_P8_16x16_8x16:
1142 *macroShift = 1;
1143 *elemIdxBits =1;
1144 elemIdx0 = tx1;
1145 elemIdx = elemIdx0;
1146 break;
1147 case ADDR_PIPECFG_P8_16x32_8x16:
1148 *macroShift = 1;
1149 *elemIdxBits =1;
1150 elemIdx0 = tx0;
1151 elemIdx = elemIdx0;
1152 break;
1153 case ADDR_PIPECFG_P8_32x32_8x16:
1154 *macroShift = 1;
1155 *elemIdxBits =2;
1156 elemIdx1 = tx1;
1157 elemIdx0 = tx1^ty1;
1158 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1159 break;
1160 case ADDR_PIPECFG_P8_16x32_16x16:
1161 *macroShift = 1;
1162 *elemIdxBits =1;
1163 elemIdx0 = tx0;
1164 elemIdx = elemIdx0;
1165 break;
1166 case ADDR_PIPECFG_P8_32x32_16x16:
1167 *macroShift = 1;
1168 *elemIdxBits =2;
1169 elemIdx0 = tx1^ty0;
1170 elemIdx1 = tx1;
1171 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1172 break;
1173 case ADDR_PIPECFG_P8_32x32_16x32:
1174 *macroShift = 1;
1175 *elemIdxBits =2;
1176 elemIdx0 = tx1^ty0;
1177 elemIdx1 = tx1^ty1;
1178 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1179 break;
1180 case ADDR_PIPECFG_P8_32x64_32x32:
1181 *macroShift = 1;
1182 *elemIdxBits =3;
1183 elemIdx0 = tx1^ty0;
1184 elemIdx1 = tx1^ty1;
1185 elemIdx2 = tx1;
1186 elemIdx = Bits2Number(3, elemIdx2, elemIdx1, elemIdx0);
1187 break;
1188 case ADDR_PIPECFG_P16_32x32_8x16:
1189 *macroShift = 0;
1190 *elemIdxBits =2;
1191 elemIdx0 = tx1^ty1;
1192 elemIdx1 = tx1;
1193 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1194 break;
1195 case ADDR_PIPECFG_P16_32x32_16x16:
1196 *macroShift = 0;
1197 *elemIdxBits =2;
1198 elemIdx0 = tx1^ty0;
1199 elemIdx1 = tx1;
1200 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1201 break;
1202 default:
1203 ADDR_UNHANDLED_CASE();
1204 break;
1205 }
1206
1207 return elemIdx;
1208 }
1209
1210 /**
1211 ****************************************************************************************************
1212 * SiLib::HwlComputeTileDataWidthAndHeightLinear
1213 *
1214 * @brief
1215 * Compute the squared cache shape for per-tile data (CMASK and HTILE) for linear layout
1216 *
1217 * @return
1218 * N/A
1219 *
1220 * @note
1221 * MacroWidth and macroHeight are measured in pixels
1222 ****************************************************************************************************
1223 */
1224 VOID SiLib::HwlComputeTileDataWidthAndHeightLinear(
1225 UINT_32* pMacroWidth, ///< [out] macro tile width
1226 UINT_32* pMacroHeight, ///< [out] macro tile height
1227 UINT_32 bpp, ///< [in] bits per pixel
1228 ADDR_TILEINFO* pTileInfo ///< [in] tile info
1229 ) const
1230 {
1231 ADDR_ASSERT(pTileInfo != NULL);
1232 UINT_32 macroWidth;
1233 UINT_32 macroHeight;
1234
1235 /// In linear mode, the htile or cmask buffer must be padded out to 4 tiles
1236 /// but for P8_32x64_32x32, it must be padded out to 8 tiles
1237 /// Actually there are more pipe configs which need 8-tile padding but SI family
1238 /// has a bug which is fixed in CI family
1239 if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32) ||
1240 (pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) ||
1241 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x32_16x16))
1242 {
1243 macroWidth = 8*MicroTileWidth;
1244 macroHeight = 8*MicroTileHeight;
1245 }
1246 else
1247 {
1248 macroWidth = 4*MicroTileWidth;
1249 macroHeight = 4*MicroTileHeight;
1250 }
1251
1252 *pMacroWidth = macroWidth;
1253 *pMacroHeight = macroHeight;
1254 }
1255
1256 /**
1257 ****************************************************************************************************
1258 * SiLib::HwlComputeHtileBytes
1259 *
1260 * @brief
1261 * Compute htile size in bytes
1262 *
1263 * @return
1264 * Htile size in bytes
1265 ****************************************************************************************************
1266 */
1267 UINT_64 SiLib::HwlComputeHtileBytes(
1268 UINT_32 pitch, ///< [in] pitch
1269 UINT_32 height, ///< [in] height
1270 UINT_32 bpp, ///< [in] bits per pixel
1271 BOOL_32 isLinear, ///< [in] if it is linear mode
1272 UINT_32 numSlices, ///< [in] number of slices
1273 UINT_64* pSliceBytes, ///< [out] bytes per slice
1274 UINT_32 baseAlign ///< [in] base alignments
1275 ) const
1276 {
1277 return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign);
1278 }
1279
1280 /**
1281 ****************************************************************************************************
1282 * SiLib::HwlComputeXmaskAddrFromCoord
1283 *
1284 * @brief
1285 * Compute address from coordinates for htile/cmask
1286 * @return
1287 * Byte address
1288 ****************************************************************************************************
1289 */
1290 UINT_64 SiLib::HwlComputeXmaskAddrFromCoord(
1291 UINT_32 pitch, ///< [in] pitch
1292 UINT_32 height, ///< [in] height
1293 UINT_32 x, ///< [in] x coord
1294 UINT_32 y, ///< [in] y coord
1295 UINT_32 slice, ///< [in] slice/depth index
1296 UINT_32 numSlices, ///< [in] number of slices
1297 UINT_32 factor, ///< [in] factor that indicates cmask(2) or htile(1)
1298 BOOL_32 isLinear, ///< [in] linear or tiled HTILE layout
1299 BOOL_32 isWidth8, ///< [in] TRUE if width is 8, FALSE means 4. It's register value
1300 BOOL_32 isHeight8, ///< [in] TRUE if width is 8, FALSE means 4. It's register value
1301 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info
1302 UINT_32* pBitPosition ///< [out] bit position inside a byte
1303 ) const
1304 {
1305 UINT_32 tx = x / MicroTileWidth;
1306 UINT_32 ty = y / MicroTileHeight;
1307 UINT_32 newPitch;
1308 UINT_32 newHeight;
1309 UINT_64 totalBytes;
1310 UINT_32 macroWidth;
1311 UINT_32 macroHeight;
1312 UINT_64 pSliceBytes;
1313 UINT_32 pBaseAlign;
1314 UINT_32 tileNumPerPipe;
1315 UINT_32 elemBits;
1316
1317 if (factor == 2) //CMASK
1318 {
1319 ADDR_CMASK_FLAGS flags = {{0}};
1320
1321 tileNumPerPipe = 256;
1322
1323 ComputeCmaskInfo(flags,
1324 pitch,
1325 height,
1326 numSlices,
1327 isLinear,
1328 pTileInfo,
1329 &newPitch,
1330 &newHeight,
1331 &totalBytes,
1332 &macroWidth,
1333 &macroHeight);
1334 elemBits = CmaskElemBits;
1335 }
1336 else //HTile
1337 {
1338 ADDR_HTILE_FLAGS flags = {{0}};
1339
1340 tileNumPerPipe = 512;
1341
1342 ComputeHtileInfo(flags,
1343 pitch,
1344 height,
1345 numSlices,
1346 isLinear,
1347 TRUE,
1348 TRUE,
1349 pTileInfo,
1350 &newPitch,
1351 &newHeight,
1352 &totalBytes,
1353 &macroWidth,
1354 &macroHeight,
1355 &pSliceBytes,
1356 &pBaseAlign);
1357 elemBits = 32;
1358 }
1359
1360 const UINT_32 pitchInTile = newPitch / MicroTileWidth;
1361 const UINT_32 heightInTile = newHeight / MicroTileWidth;
1362 UINT_64 macroOffset; // Per pipe starting offset of the macro tile in which this tile lies.
1363 UINT_64 microNumber; // Per pipe starting offset of the macro tile in which this tile lies.
1364 UINT_32 microX;
1365 UINT_32 microY;
1366 UINT_64 microOffset;
1367 UINT_32 microShift;
1368 UINT_64 totalOffset;
1369 UINT_32 elemIdxBits;
1370 UINT_32 elemIdx =
1371 TileCoordToMaskElementIndex(tx, ty, pTileInfo->pipeConfig, &microShift, &elemIdxBits);
1372
1373 UINT_32 numPipes = HwlGetPipes(pTileInfo);
1374
1375 if (isLinear)
1376 { //linear addressing
1377 // Linear addressing is extremelly wasting memory if slice > 1, since each pipe has the full
1378 // slice memory foot print instead of divided by numPipes.
1379 microX = tx / 4; // Macro Tile is 4x4
1380 microY = ty / 4 ;
1381 microNumber = static_cast<UINT_64>(microX + microY * (pitchInTile / 4)) << microShift;
1382
1383 UINT_32 sliceBits = pitchInTile * heightInTile;
1384
1385 // do htile single slice alignment if the flag is true
1386 if (m_configFlags.useHtileSliceAlign && (factor == 1)) //Htile
1387 {
1388 sliceBits = PowTwoAlign(sliceBits, BITS_TO_BYTES(HtileCacheBits) * numPipes / elemBits);
1389 }
1390 macroOffset = slice * (sliceBits / numPipes) * elemBits ;
1391 }
1392 else
1393 { //tiled addressing
1394 const UINT_32 macroWidthInTile = macroWidth / MicroTileWidth; // Now in unit of Tiles
1395 const UINT_32 macroHeightInTile = macroHeight / MicroTileHeight;
1396 const UINT_32 pitchInCL = pitchInTile / macroWidthInTile;
1397 const UINT_32 heightInCL = heightInTile / macroHeightInTile;
1398
1399 const UINT_32 macroX = x / macroWidth;
1400 const UINT_32 macroY = y / macroHeight;
1401 const UINT_32 macroNumber = macroX + macroY * pitchInCL + slice * pitchInCL * heightInCL;
1402
1403 // Per pipe starting offset of the cache line in which this tile lies.
1404 microX = (x % macroWidth) / MicroTileWidth / 4; // Macro Tile is 4x4
1405 microY = (y % macroHeight) / MicroTileHeight / 4 ;
1406 microNumber = static_cast<UINT_64>(microX + microY * (macroWidth / MicroTileWidth / 4)) << microShift;
1407
1408 macroOffset = macroNumber * tileNumPerPipe * elemBits;
1409 }
1410
1411 if(elemIdxBits == microShift)
1412 {
1413 microNumber += elemIdx;
1414 }
1415 else
1416 {
1417 microNumber >>= elemIdxBits;
1418 microNumber <<= elemIdxBits;
1419 microNumber += elemIdx;
1420 }
1421
1422 microOffset = elemBits * microNumber;
1423 totalOffset = microOffset + macroOffset;
1424
1425 UINT_32 pipe = ComputePipeFromCoord(x, y, 0, ADDR_TM_2D_TILED_THIN1, 0, FALSE, pTileInfo);
1426 UINT_64 addrInBits = totalOffset % (m_pipeInterleaveBytes * 8) +
1427 pipe * (m_pipeInterleaveBytes * 8) +
1428 totalOffset / (m_pipeInterleaveBytes * 8) * (m_pipeInterleaveBytes * 8) * numPipes;
1429 *pBitPosition = static_cast<UINT_32>(addrInBits) % 8;
1430 UINT_64 addr = addrInBits / 8;
1431
1432 return addr;
1433 }
1434
1435 /**
1436 ****************************************************************************************************
1437 * SiLib::HwlComputeXmaskCoordFromAddr
1438 *
1439 * @brief
1440 * Compute the coord from an address of a cmask/htile
1441 *
1442 * @return
1443 * N/A
1444 *
1445 * @note
1446 * This method is reused by htile, so rename to Xmask
1447 ****************************************************************************************************
1448 */
1449 VOID SiLib::HwlComputeXmaskCoordFromAddr(
1450 UINT_64 addr, ///< [in] address
1451 UINT_32 bitPosition, ///< [in] bitPosition in a byte
1452 UINT_32 pitch, ///< [in] pitch
1453 UINT_32 height, ///< [in] height
1454 UINT_32 numSlices, ///< [in] number of slices
1455 UINT_32 factor, ///< [in] factor that indicates cmask or htile
1456 BOOL_32 isLinear, ///< [in] linear or tiled HTILE layout
1457 BOOL_32 isWidth8, ///< [in] Not used by SI
1458 BOOL_32 isHeight8, ///< [in] Not used by SI
1459 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info
1460 UINT_32* pX, ///< [out] x coord
1461 UINT_32* pY, ///< [out] y coord
1462 UINT_32* pSlice ///< [out] slice index
1463 ) const
1464 {
1465 UINT_32 newPitch;
1466 UINT_32 newHeight;
1467 UINT_64 totalBytes;
1468 UINT_32 clWidth;
1469 UINT_32 clHeight;
1470 UINT_32 tileNumPerPipe;
1471 UINT_64 sliceBytes;
1472
1473 *pX = 0;
1474 *pY = 0;
1475 *pSlice = 0;
1476
1477 if (factor == 2) //CMASK
1478 {
1479 ADDR_CMASK_FLAGS flags = {{0}};
1480
1481 tileNumPerPipe = 256;
1482
1483 ComputeCmaskInfo(flags,
1484 pitch,
1485 height,
1486 numSlices,
1487 isLinear,
1488 pTileInfo,
1489 &newPitch,
1490 &newHeight,
1491 &totalBytes,
1492 &clWidth,
1493 &clHeight);
1494 }
1495 else //HTile
1496 {
1497 ADDR_HTILE_FLAGS flags = {{0}};
1498
1499 tileNumPerPipe = 512;
1500
1501 ComputeHtileInfo(flags,
1502 pitch,
1503 height,
1504 numSlices,
1505 isLinear,
1506 TRUE,
1507 TRUE,
1508 pTileInfo,
1509 &newPitch,
1510 &newHeight,
1511 &totalBytes,
1512 &clWidth,
1513 &clHeight,
1514 &sliceBytes);
1515 }
1516
1517 const UINT_32 pitchInTile = newPitch / MicroTileWidth;
1518 const UINT_32 heightInTile = newHeight / MicroTileWidth;
1519 const UINT_32 pitchInMacroTile = pitchInTile / 4;
1520 UINT_32 macroShift;
1521 UINT_32 elemIdxBits;
1522 // get macroShift and elemIdxBits
1523 TileCoordToMaskElementIndex(0, 0, pTileInfo->pipeConfig, &macroShift, &elemIdxBits);
1524
1525 const UINT_32 numPipes = HwlGetPipes(pTileInfo);
1526 const UINT_32 pipe = (UINT_32)((addr / m_pipeInterleaveBytes) % numPipes);
1527 // per pipe
1528 UINT_64 localOffset = (addr % m_pipeInterleaveBytes) +
1529 (addr / m_pipeInterleaveBytes / numPipes)* m_pipeInterleaveBytes;
1530
1531 UINT_32 tileIndex;
1532 if (factor == 2) //CMASK
1533 {
1534 tileIndex = (UINT_32)(localOffset * 2 + (bitPosition != 0));
1535 }
1536 else
1537 {
1538 tileIndex = (UINT_32)(localOffset / 4);
1539 }
1540
1541 UINT_32 macroOffset;
1542 if (isLinear)
1543 {
1544 UINT_32 sliceSizeInTile = pitchInTile * heightInTile;
1545
1546 // do htile single slice alignment if the flag is true
1547 if (m_configFlags.useHtileSliceAlign && (factor == 1)) //Htile
1548 {
1549 sliceSizeInTile = PowTwoAlign(sliceSizeInTile, static_cast<UINT_32>(sliceBytes) / 64);
1550 }
1551 *pSlice = tileIndex / (sliceSizeInTile / numPipes);
1552 macroOffset = tileIndex % (sliceSizeInTile / numPipes);
1553 }
1554 else
1555 {
1556 const UINT_32 clWidthInTile = clWidth / MicroTileWidth; // Now in unit of Tiles
1557 const UINT_32 clHeightInTile = clHeight / MicroTileHeight;
1558 const UINT_32 pitchInCL = pitchInTile / clWidthInTile;
1559 const UINT_32 heightInCL = heightInTile / clHeightInTile;
1560 const UINT_32 clIndex = tileIndex / tileNumPerPipe;
1561
1562 UINT_32 clX = clIndex % pitchInCL;
1563 UINT_32 clY = (clIndex % (heightInCL * pitchInCL)) / pitchInCL;
1564
1565 *pX = clX * clWidthInTile * MicroTileWidth;
1566 *pY = clY * clHeightInTile * MicroTileHeight;
1567 *pSlice = clIndex / (heightInCL * pitchInCL);
1568
1569 macroOffset = tileIndex % tileNumPerPipe;
1570 }
1571
1572 UINT_32 elemIdx = macroOffset & 7;
1573 macroOffset >>= elemIdxBits;
1574
1575 if (elemIdxBits != macroShift)
1576 {
1577 macroOffset <<= (elemIdxBits - macroShift);
1578
1579 UINT_32 pipebit1 = _BIT(pipe,1);
1580 UINT_32 pipebit2 = _BIT(pipe,2);
1581 UINT_32 pipebit3 = _BIT(pipe,3);
1582 if (pitchInMacroTile % 2)
1583 { //odd
1584 switch (pTileInfo->pipeConfig)
1585 {
1586 case ADDR_PIPECFG_P4_32x32:
1587 macroOffset |= pipebit1;
1588 break;
1589 case ADDR_PIPECFG_P8_32x32_8x16:
1590 case ADDR_PIPECFG_P8_32x32_16x16:
1591 case ADDR_PIPECFG_P8_32x32_16x32:
1592 macroOffset |= pipebit2;
1593 break;
1594 default:
1595 break;
1596 }
1597
1598 }
1599
1600 if (pitchInMacroTile % 4)
1601 {
1602 if (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)
1603 {
1604 macroOffset |= (pipebit1<<1);
1605 }
1606 if((pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) ||
1607 (pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_16x16))
1608 {
1609 macroOffset |= (pipebit3<<1);
1610 }
1611 }
1612 }
1613
1614 UINT_32 macroX;
1615 UINT_32 macroY;
1616
1617 if (isLinear)
1618 {
1619 macroX = macroOffset % pitchInMacroTile;
1620 macroY = macroOffset / pitchInMacroTile;
1621 }
1622 else
1623 {
1624 const UINT_32 clWidthInMacroTile = clWidth / (MicroTileWidth * 4);
1625 macroX = macroOffset % clWidthInMacroTile;
1626 macroY = macroOffset / clWidthInMacroTile;
1627 }
1628
1629 *pX += macroX * 4 * MicroTileWidth;
1630 *pY += macroY * 4 * MicroTileHeight;
1631
1632 UINT_32 microX;
1633 UINT_32 microY;
1634 ComputeTileCoordFromPipeAndElemIdx(elemIdx, pipe, pTileInfo->pipeConfig, pitchInMacroTile,
1635 *pX, *pY, &microX, &microY);
1636
1637 *pX += microX * MicroTileWidth;
1638 *pY += microY * MicroTileWidth;
1639 }
1640
1641 /**
1642 ****************************************************************************************************
1643 * SiLib::HwlGetPitchAlignmentLinear
1644 * @brief
1645 * Get pitch alignment
1646 * @return
1647 * pitch alignment
1648 ****************************************************************************************************
1649 */
1650 UINT_32 SiLib::HwlGetPitchAlignmentLinear(
1651 UINT_32 bpp, ///< [in] bits per pixel
1652 ADDR_SURFACE_FLAGS flags ///< [in] surface flags
1653 ) const
1654 {
1655 UINT_32 pitchAlign;
1656
1657 // Interleaved access requires a 256B aligned pitch, so fall back to pre-SI alignment
1658 if (flags.interleaved)
1659 {
1660 pitchAlign = Max(64u, m_pipeInterleaveBytes / BITS_TO_BYTES(bpp));
1661
1662 }
1663 else
1664 {
1665 pitchAlign = Max(8u, 64 / BITS_TO_BYTES(bpp));
1666 }
1667
1668 return pitchAlign;
1669 }
1670
1671 /**
1672 ****************************************************************************************************
1673 * SiLib::HwlGetSizeAdjustmentLinear
1674 *
1675 * @brief
1676 * Adjust linear surface pitch and slice size
1677 *
1678 * @return
1679 * Logical slice size in bytes
1680 ****************************************************************************************************
1681 */
1682 UINT_64 SiLib::HwlGetSizeAdjustmentLinear(
1683 AddrTileMode tileMode, ///< [in] tile mode
1684 UINT_32 bpp, ///< [in] bits per pixel
1685 UINT_32 numSamples, ///< [in] number of samples
1686 UINT_32 baseAlign, ///< [in] base alignment
1687 UINT_32 pitchAlign, ///< [in] pitch alignment
1688 UINT_32* pPitch, ///< [in,out] pointer to pitch
1689 UINT_32* pHeight, ///< [in,out] pointer to height
1690 UINT_32* pHeightAlign ///< [in,out] pointer to height align
1691 ) const
1692 {
1693 UINT_64 sliceSize;
1694 if (tileMode == ADDR_TM_LINEAR_GENERAL)
1695 {
1696 sliceSize = BITS_TO_BYTES(static_cast<UINT_64>(*pPitch) * (*pHeight) * bpp * numSamples);
1697 }
1698 else
1699 {
1700 UINT_32 pitch = *pPitch;
1701 UINT_32 height = *pHeight;
1702
1703 UINT_32 pixelsPerPipeInterleave = m_pipeInterleaveBytes / BITS_TO_BYTES(bpp);
1704 UINT_32 sliceAlignInPixel = pixelsPerPipeInterleave < 64 ? 64 : pixelsPerPipeInterleave;
1705
1706 // numSamples should be 1 in real cases (no MSAA for linear but TGL may pass non 1 value)
1707 UINT_64 pixelPerSlice = static_cast<UINT_64>(pitch) * height * numSamples;
1708
1709 while (pixelPerSlice % sliceAlignInPixel)
1710 {
1711 pitch += pitchAlign;
1712 pixelPerSlice = static_cast<UINT_64>(pitch) * height * numSamples;
1713 }
1714
1715 *pPitch = pitch;
1716
1717 UINT_32 heightAlign = 1;
1718
1719 while ((pitch * heightAlign) % sliceAlignInPixel)
1720 {
1721 heightAlign++;
1722 }
1723
1724 *pHeightAlign = heightAlign;
1725
1726 sliceSize = BITS_TO_BYTES(pixelPerSlice * bpp);
1727 }
1728
1729 return sliceSize;
1730 }
1731
1732 /**
1733 ****************************************************************************************************
1734 * SiLib::HwlPreHandleBaseLvl3xPitch
1735 *
1736 * @brief
1737 * Pre-handler of 3x pitch (96 bit) adjustment
1738 *
1739 * @return
1740 * Expected pitch
1741 ****************************************************************************************************
1742 */
1743 UINT_32 SiLib::HwlPreHandleBaseLvl3xPitch(
1744 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input
1745 UINT_32 expPitch ///< [in] pitch
1746 ) const
1747 {
1748 ADDR_ASSERT(pIn->width == expPitch);
1749
1750 // From SI, if pow2Pad is 1 the pitch is expanded 3x first, then padded to pow2, so nothing to
1751 // do here
1752 if (pIn->flags.pow2Pad == FALSE)
1753 {
1754 Addr::V1::Lib::HwlPreHandleBaseLvl3xPitch(pIn, expPitch);
1755 }
1756 else
1757 {
1758 ADDR_ASSERT(IsPow2(expPitch));
1759 }
1760
1761 return expPitch;
1762 }
1763
1764 /**
1765 ****************************************************************************************************
1766 * SiLib::HwlPostHandleBaseLvl3xPitch
1767 *
1768 * @brief
1769 * Post-handler of 3x pitch adjustment
1770 *
1771 * @return
1772 * Expected pitch
1773 ****************************************************************************************************
1774 */
1775 UINT_32 SiLib::HwlPostHandleBaseLvl3xPitch(
1776 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input
1777 UINT_32 expPitch ///< [in] pitch
1778 ) const
1779 {
1780 /**
1781 * @note The pitch will be divided by 3 in the end so the value will look odd but h/w should
1782 * be able to compute a correct pitch from it as h/w address library is doing the job.
1783 */
1784 // From SI, the pitch is expanded 3x first, then padded to pow2, so no special handler here
1785 if (pIn->flags.pow2Pad == FALSE)
1786 {
1787 Addr::V1::Lib::HwlPostHandleBaseLvl3xPitch(pIn, expPitch);
1788 }
1789
1790 return expPitch;
1791 }
1792
1793 /**
1794 ****************************************************************************************************
1795 * SiLib::HwlGetPitchAlignmentMicroTiled
1796 *
1797 * @brief
1798 * Compute 1D tiled surface pitch alignment
1799 *
1800 * @return
1801 * pitch alignment
1802 ****************************************************************************************************
1803 */
1804 UINT_32 SiLib::HwlGetPitchAlignmentMicroTiled(
1805 AddrTileMode tileMode, ///< [in] tile mode
1806 UINT_32 bpp, ///< [in] bits per pixel
1807 ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
1808 UINT_32 numSamples ///< [in] number of samples
1809 ) const
1810 {
1811 UINT_32 pitchAlign;
1812
1813 if (flags.qbStereo)
1814 {
1815 pitchAlign = EgBasedLib::HwlGetPitchAlignmentMicroTiled(tileMode,bpp,flags,numSamples);
1816 }
1817 else
1818 {
1819 pitchAlign = 8;
1820 }
1821
1822 return pitchAlign;
1823 }
1824
1825 /**
1826 ****************************************************************************************************
1827 * SiLib::HwlGetSizeAdjustmentMicroTiled
1828 *
1829 * @brief
1830 * Adjust 1D tiled surface pitch and slice size
1831 *
1832 * @return
1833 * Logical slice size in bytes
1834 ****************************************************************************************************
1835 */
1836 UINT_64 SiLib::HwlGetSizeAdjustmentMicroTiled(
1837 UINT_32 thickness, ///< [in] thickness
1838 UINT_32 bpp, ///< [in] bits per pixel
1839 ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
1840 UINT_32 numSamples, ///< [in] number of samples
1841 UINT_32 baseAlign, ///< [in] base alignment
1842 UINT_32 pitchAlign, ///< [in] pitch alignment
1843 UINT_32* pPitch, ///< [in,out] pointer to pitch
1844 UINT_32* pHeight ///< [in,out] pointer to height
1845 ) const
1846 {
1847 UINT_64 logicalSliceSize;
1848 UINT_64 physicalSliceSize;
1849
1850 UINT_32 pitch = *pPitch;
1851 UINT_32 height = *pHeight;
1852
1853 // Logical slice: pitch * height * bpp * numSamples (no 1D MSAA so actually numSamples == 1)
1854 logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
1855
1856 // Physical slice: multiplied by thickness
1857 physicalSliceSize = logicalSliceSize * thickness;
1858
1859 // Pitch alignment is always 8, so if slice size is not padded to base alignment
1860 // (pipe_interleave_size), we need to increase pitch
1861 while ((physicalSliceSize % baseAlign) != 0)
1862 {
1863 pitch += pitchAlign;
1864
1865 logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
1866
1867 physicalSliceSize = logicalSliceSize * thickness;
1868 }
1869
1870 #if !ALT_TEST
1871 //
1872 // Special workaround for depth/stencil buffer, use 8 bpp to align depth buffer again since
1873 // the stencil plane may have larger pitch if the slice size is smaller than base alignment.
1874 //
1875 // Note: this actually does not work for mipmap but mipmap depth texture is not really
1876 // sampled with mipmap.
1877 //
1878 if (flags.depth && (flags.noStencil == FALSE))
1879 {
1880 ADDR_ASSERT(numSamples == 1);
1881
1882 UINT_64 logicalSiceSizeStencil = static_cast<UINT_64>(pitch) * height; // 1 byte stencil
1883
1884 while ((logicalSiceSizeStencil % baseAlign) != 0)
1885 {
1886 pitch += pitchAlign; // Stencil plane's pitch alignment is the same as depth plane's
1887
1888 logicalSiceSizeStencil = static_cast<UINT_64>(pitch) * height;
1889 }
1890
1891 if (pitch != *pPitch)
1892 {
1893 // If this is a mipmap, this padded one cannot be sampled as a whole mipmap!
1894 logicalSliceSize = logicalSiceSizeStencil * BITS_TO_BYTES(bpp);
1895 }
1896 }
1897 #endif
1898 *pPitch = pitch;
1899
1900 // No adjust for pHeight
1901
1902 return logicalSliceSize;
1903 }
1904
1905 /**
1906 ****************************************************************************************************
1907 * SiLib::HwlConvertChipFamily
1908 *
1909 * @brief
1910 * Convert familyID defined in atiid.h to ChipFamily and set m_chipFamily/m_chipRevision
1911 * @return
1912 * ChipFamily
1913 ****************************************************************************************************
1914 */
1915 ChipFamily SiLib::HwlConvertChipFamily(
1916 UINT_32 uChipFamily, ///< [in] chip family defined in atiih.h
1917 UINT_32 uChipRevision) ///< [in] chip revision defined in "asic_family"_id.h
1918 {
1919 ChipFamily family = ADDR_CHIP_FAMILY_SI;
1920
1921 switch (uChipFamily)
1922 {
1923 case FAMILY_SI:
1924 m_settings.isSouthernIsland = 1;
1925 m_settings.isTahiti = ASICREV_IS_TAHITI_P(uChipRevision);
1926 m_settings.isPitCairn = ASICREV_IS_PITCAIRN_PM(uChipRevision);
1927 m_settings.isCapeVerde = ASICREV_IS_CAPEVERDE_M(uChipRevision);
1928 m_settings.isOland = ASICREV_IS_OLAND_M(uChipRevision);
1929 m_settings.isHainan = ASICREV_IS_HAINAN_V(uChipRevision);
1930 break;
1931 default:
1932 ADDR_ASSERT(!"This should be a Fusion");
1933 break;
1934 }
1935
1936 return family;
1937 }
1938
1939 /**
1940 ****************************************************************************************************
1941 * SiLib::HwlSetupTileInfo
1942 *
1943 * @brief
1944 * Setup default value of tile info for SI
1945 ****************************************************************************************************
1946 */
1947 VOID SiLib::HwlSetupTileInfo(
1948 AddrTileMode tileMode, ///< [in] Tile mode
1949 ADDR_SURFACE_FLAGS flags, ///< [in] Surface type flags
1950 UINT_32 bpp, ///< [in] Bits per pixel
1951 UINT_32 pitch, ///< [in] Pitch in pixels
1952 UINT_32 height, ///< [in] Height in pixels
1953 UINT_32 numSamples, ///< [in] Number of samples
1954 ADDR_TILEINFO* pTileInfoIn, ///< [in] Tile info input: NULL for default
1955 ADDR_TILEINFO* pTileInfoOut, ///< [out] Tile info output
1956 AddrTileType inTileType, ///< [in] Tile type
1957 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output
1958 ) const
1959 {
1960 UINT_32 thickness = Thickness(tileMode);
1961 ADDR_TILEINFO* pTileInfo = pTileInfoOut;
1962 INT index = TileIndexInvalid;
1963
1964 // Fail-safe code
1965 if (IsLinear(tileMode) == FALSE)
1966 {
1967 // 128 bpp/thick tiling must be non-displayable.
1968 // Fmask reuse color buffer's entry but bank-height field can be from another entry
1969 // To simplify the logic, fmask entry should be picked from non-displayable ones
1970 if (bpp == 128 || thickness > 1 || flags.fmask || flags.prt)
1971 {
1972 inTileType = ADDR_NON_DISPLAYABLE;
1973 }
1974
1975 if (flags.depth || flags.stencil)
1976 {
1977 inTileType = ADDR_DEPTH_SAMPLE_ORDER;
1978 }
1979 }
1980
1981 // Partial valid fields are not allowed for SI.
1982 if (IsTileInfoAllZero(pTileInfo))
1983 {
1984 if (IsMacroTiled(tileMode))
1985 {
1986 if (flags.prt)
1987 {
1988 if (numSamples == 1)
1989 {
1990 if (flags.depth)
1991 {
1992 switch (bpp)
1993 {
1994 case 16:
1995 index = 3;
1996 break;
1997 case 32:
1998 index = 6;
1999 break;
2000 default:
2001 ADDR_ASSERT_ALWAYS();
2002 break;
2003 }
2004 }
2005 else
2006 {
2007 switch (bpp)
2008 {
2009 case 8:
2010 index = 21;
2011 break;
2012 case 16:
2013 index = 22;
2014 break;
2015 case 32:
2016 index = 23;
2017 break;
2018 case 64:
2019 index = 24;
2020 break;
2021 case 128:
2022 index = 25;
2023 break;
2024 default:
2025 break;
2026 }
2027
2028 if (thickness > 1)
2029 {
2030 ADDR_ASSERT(bpp != 128);
2031 index += 5;
2032 }
2033 }
2034 }
2035 else
2036 {
2037 ADDR_ASSERT(numSamples == 4);
2038
2039 if (flags.depth)
2040 {
2041 switch (bpp)
2042 {
2043 case 16:
2044 index = 5;
2045 break;
2046 case 32:
2047 index = 7;
2048 break;
2049 default:
2050 ADDR_ASSERT_ALWAYS();
2051 break;
2052 }
2053 }
2054 else
2055 {
2056 switch (bpp)
2057 {
2058 case 8:
2059 index = 23;
2060 break;
2061 case 16:
2062 index = 24;
2063 break;
2064 case 32:
2065 index = 25;
2066 break;
2067 case 64:
2068 index = 30;
2069 break;
2070 default:
2071 ADDR_ASSERT_ALWAYS();
2072 break;
2073 }
2074 }
2075 }
2076 }//end of PRT part
2077 // See table entries 0-7
2078 else if (flags.depth || flags.stencil)
2079 {
2080 if (flags.compressZ)
2081 {
2082 if (flags.stencil)
2083 {
2084 index = 0;
2085 }
2086 else
2087 {
2088 // optimal tile index for compressed depth/stencil.
2089 switch (numSamples)
2090 {
2091 case 1:
2092 index = 0;
2093 break;
2094 case 2:
2095 case 4:
2096 index = 1;
2097 break;
2098 case 8:
2099 index = 2;
2100 break;
2101 default:
2102 break;
2103 }
2104 }
2105 }
2106 else // unCompressZ
2107 {
2108 index = 3;
2109 }
2110 }
2111 else //non PRT & non Depth & non Stencil
2112 {
2113 // See table entries 9-12
2114 if (inTileType == ADDR_DISPLAYABLE)
2115 {
2116 switch (bpp)
2117 {
2118 case 8:
2119 index = 10;
2120 break;
2121 case 16:
2122 index = 11;
2123 break;
2124 case 32:
2125 index = 12;
2126 break;
2127 case 64:
2128 index = 12;
2129 break;
2130 default:
2131 break;
2132 }
2133 }
2134 else
2135 {
2136 // See table entries 13-17
2137 if (thickness == 1)
2138 {
2139 if (flags.fmask)
2140 {
2141 UINT_32 fmaskPixelSize = bpp * numSamples;
2142
2143 switch (fmaskPixelSize)
2144 {
2145 case 8:
2146 index = 14;
2147 break;
2148 case 16:
2149 index = 15;
2150 break;
2151 case 32:
2152 index = 16;
2153 break;
2154 case 64:
2155 index = 17;
2156 break;
2157 default:
2158 ADDR_ASSERT_ALWAYS();
2159 }
2160 }
2161 else
2162 {
2163 switch (bpp)
2164 {
2165 case 8:
2166 index = 14;
2167 break;
2168 case 16:
2169 index = 15;
2170 break;
2171 case 32:
2172 index = 16;
2173 break;
2174 case 64:
2175 index = 17;
2176 break;
2177 case 128:
2178 index = 17;
2179 break;
2180 default:
2181 break;
2182 }
2183 }
2184 }
2185 else // thick tiling - entries 18-20
2186 {
2187 switch (thickness)
2188 {
2189 case 4:
2190 index = 20;
2191 break;
2192 case 8:
2193 index = 19;
2194 break;
2195 default:
2196 break;
2197 }
2198 }
2199 }
2200 }
2201 }
2202 else
2203 {
2204 if (tileMode == ADDR_TM_LINEAR_ALIGNED)
2205 {
2206 index = 8;
2207 }
2208 else if (tileMode == ADDR_TM_LINEAR_GENERAL)
2209 {
2210 index = TileIndexLinearGeneral;
2211 }
2212 else
2213 {
2214 if (flags.depth || flags.stencil)
2215 {
2216 index = 4;
2217 }
2218 else if (inTileType == ADDR_DISPLAYABLE)
2219 {
2220 index = 9;
2221 }
2222 else if (thickness == 1)
2223 {
2224 index = 13;
2225 }
2226 else
2227 {
2228 index = 18;
2229 }
2230 }
2231 }
2232
2233 if (index >= 0 && index <= 31)
2234 {
2235 *pTileInfo = m_tileTable[index].info;
2236 pOut->tileType = m_tileTable[index].type;
2237 }
2238
2239 if (index == TileIndexLinearGeneral)
2240 {
2241 *pTileInfo = m_tileTable[8].info;
2242 pOut->tileType = m_tileTable[8].type;
2243 }
2244 }
2245 else
2246 {
2247 if (pTileInfoIn)
2248 {
2249 if (flags.stencil && pTileInfoIn->tileSplitBytes == 0)
2250 {
2251 // Stencil always uses index 0
2252 *pTileInfo = m_tileTable[0].info;
2253 }
2254 }
2255 // Pass through tile type
2256 pOut->tileType = inTileType;
2257 }
2258
2259 pOut->tileIndex = index;
2260 pOut->prtTileIndex = flags.prt;
2261 }
2262
2263 /**
2264 ****************************************************************************************************
2265 * SiLib::DecodeGbRegs
2266 *
2267 * @brief
2268 * Decodes GB_ADDR_CONFIG and noOfBanks/noOfRanks
2269 *
2270 * @return
2271 * TRUE if all settings are valid
2272 *
2273 ****************************************************************************************************
2274 */
2275 BOOL_32 SiLib::DecodeGbRegs(
2276 const ADDR_REGISTER_VALUE* pRegValue) ///< [in] create input
2277 {
2278 GB_ADDR_CONFIG reg;
2279 BOOL_32 valid = TRUE;
2280
2281 reg.val = pRegValue->gbAddrConfig;
2282
2283 switch (reg.f.pipe_interleave_size)
2284 {
2285 case ADDR_CONFIG_PIPE_INTERLEAVE_256B:
2286 m_pipeInterleaveBytes = ADDR_PIPEINTERLEAVE_256B;
2287 break;
2288 case ADDR_CONFIG_PIPE_INTERLEAVE_512B:
2289 m_pipeInterleaveBytes = ADDR_PIPEINTERLEAVE_512B;
2290 break;
2291 default:
2292 valid = FALSE;
2293 ADDR_UNHANDLED_CASE();
2294 break;
2295 }
2296
2297 switch (reg.f.row_size)
2298 {
2299 case ADDR_CONFIG_1KB_ROW:
2300 m_rowSize = ADDR_ROWSIZE_1KB;
2301 break;
2302 case ADDR_CONFIG_2KB_ROW:
2303 m_rowSize = ADDR_ROWSIZE_2KB;
2304 break;
2305 case ADDR_CONFIG_4KB_ROW:
2306 m_rowSize = ADDR_ROWSIZE_4KB;
2307 break;
2308 default:
2309 valid = FALSE;
2310 ADDR_UNHANDLED_CASE();
2311 break;
2312 }
2313
2314 switch (pRegValue->noOfBanks)
2315 {
2316 case 0:
2317 m_banks = 4;
2318 break;
2319 case 1:
2320 m_banks = 8;
2321 break;
2322 case 2:
2323 m_banks = 16;
2324 break;
2325 default:
2326 valid = FALSE;
2327 ADDR_UNHANDLED_CASE();
2328 break;
2329 }
2330
2331 switch (pRegValue->noOfRanks)
2332 {
2333 case 0:
2334 m_ranks = 1;
2335 break;
2336 case 1:
2337 m_ranks = 2;
2338 break;
2339 default:
2340 valid = FALSE;
2341 ADDR_UNHANDLED_CASE();
2342 break;
2343 }
2344
2345 m_logicalBanks = m_banks * m_ranks;
2346
2347 ADDR_ASSERT(m_logicalBanks <= 16);
2348
2349 return valid;
2350 }
2351
2352 /**
2353 ****************************************************************************************************
2354 * SiLib::HwlInitGlobalParams
2355 *
2356 * @brief
2357 * Initializes global parameters
2358 *
2359 * @return
2360 * TRUE if all settings are valid
2361 *
2362 ****************************************************************************************************
2363 */
2364 BOOL_32 SiLib::HwlInitGlobalParams(
2365 const ADDR_CREATE_INPUT* pCreateIn) ///< [in] create input
2366 {
2367 BOOL_32 valid = TRUE;
2368 const ADDR_REGISTER_VALUE* pRegValue = &pCreateIn->regValue;
2369
2370 valid = DecodeGbRegs(pRegValue);
2371
2372 if (valid)
2373 {
2374 if (m_settings.isTahiti || m_settings.isPitCairn)
2375 {
2376 m_pipes = 8;
2377 }
2378 else if (m_settings.isCapeVerde || m_settings.isOland)
2379 {
2380 m_pipes = 4;
2381 }
2382 else
2383 {
2384 // Hainan is 2-pipe (m_settings.isHainan == 1)
2385 m_pipes = 2;
2386 }
2387
2388 valid = InitTileSettingTable(pRegValue->pTileConfig, pRegValue->noOfEntries);
2389
2390 if (valid)
2391 {
2392 InitEquationTable();
2393 }
2394
2395 m_maxSamples = 16;
2396 }
2397
2398 return valid;
2399 }
2400
2401 /**
2402 ****************************************************************************************************
2403 * SiLib::HwlConvertTileInfoToHW
2404 * @brief
2405 * Entry of si's ConvertTileInfoToHW
2406 * @return
2407 * ADDR_E_RETURNCODE
2408 ****************************************************************************************************
2409 */
2410 ADDR_E_RETURNCODE SiLib::HwlConvertTileInfoToHW(
2411 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, ///< [in] input structure
2412 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut ///< [out] output structure
2413 ) const
2414 {
2415 ADDR_E_RETURNCODE retCode = ADDR_OK;
2416
2417 retCode = EgBasedLib::HwlConvertTileInfoToHW(pIn, pOut);
2418
2419 if (retCode == ADDR_OK)
2420 {
2421 if (pIn->reverse == FALSE)
2422 {
2423 if (pIn->pTileInfo->pipeConfig == ADDR_PIPECFG_INVALID)
2424 {
2425 retCode = ADDR_INVALIDPARAMS;
2426 }
2427 else
2428 {
2429 pOut->pTileInfo->pipeConfig =
2430 static_cast<AddrPipeCfg>(pIn->pTileInfo->pipeConfig - 1);
2431 }
2432 }
2433 else
2434 {
2435 pOut->pTileInfo->pipeConfig =
2436 static_cast<AddrPipeCfg>(pIn->pTileInfo->pipeConfig + 1);
2437 }
2438 }
2439
2440 return retCode;
2441 }
2442
2443 /**
2444 ****************************************************************************************************
2445 * SiLib::HwlComputeXmaskCoordYFrom8Pipe
2446 *
2447 * @brief
2448 * Compute the Y coord which will be added to Xmask Y
2449 * coord.
2450 * @return
2451 * Y coord
2452 ****************************************************************************************************
2453 */
2454 UINT_32 SiLib::HwlComputeXmaskCoordYFrom8Pipe(
2455 UINT_32 pipe, ///< [in] pipe id
2456 UINT_32 x ///< [in] tile coord x, which is original x coord / 8
2457 ) const
2458 {
2459 // This function should never be called since it is 6xx/8xx specfic.
2460 // Keep this empty implementation to avoid any mis-use.
2461 ADDR_ASSERT_ALWAYS();
2462
2463 return 0;
2464 }
2465
2466 /**
2467 ****************************************************************************************************
2468 * SiLib::HwlComputeSurfaceCoord2DFromBankPipe
2469 *
2470 * @brief
2471 * Compute surface x,y coordinates from bank/pipe info
2472 * @return
2473 * N/A
2474 ****************************************************************************************************
2475 */
2476 VOID SiLib::HwlComputeSurfaceCoord2DFromBankPipe(
2477 AddrTileMode tileMode, ///< [in] tile mode
2478 UINT_32* pX, ///< [in,out] x coordinate
2479 UINT_32* pY, ///< [in,out] y coordinate
2480 UINT_32 slice, ///< [in] slice index
2481 UINT_32 bank, ///< [in] bank number
2482 UINT_32 pipe, ///< [in] pipe number
2483 UINT_32 bankSwizzle,///< [in] bank swizzle
2484 UINT_32 pipeSwizzle,///< [in] pipe swizzle
2485 UINT_32 tileSlices, ///< [in] slices in a micro tile
2486 BOOL_32 ignoreSE, ///< [in] TRUE if shader engines are ignored
2487 ADDR_TILEINFO* pTileInfo ///< [in] bank structure. **All fields to be valid on entry**
2488 ) const
2489 {
2490 UINT_32 xBit;
2491 UINT_32 yBit;
2492 UINT_32 yBit3 = 0;
2493 UINT_32 yBit4 = 0;
2494 UINT_32 yBit5 = 0;
2495 UINT_32 yBit6 = 0;
2496
2497 UINT_32 xBit3 = 0;
2498 UINT_32 xBit4 = 0;
2499 UINT_32 xBit5 = 0;
2500
2501 UINT_32 numPipes = GetPipePerSurf(pTileInfo->pipeConfig);
2502
2503 CoordFromBankPipe xyBits = {0};
2504 ComputeSurfaceCoord2DFromBankPipe(tileMode, *pX, *pY, slice, bank, pipe,
2505 bankSwizzle, pipeSwizzle, tileSlices, pTileInfo,
2506 &xyBits);
2507 yBit3 = xyBits.yBit3;
2508 yBit4 = xyBits.yBit4;
2509 yBit5 = xyBits.yBit5;
2510 yBit6 = xyBits.yBit6;
2511
2512 xBit3 = xyBits.xBit3;
2513 xBit4 = xyBits.xBit4;
2514 xBit5 = xyBits.xBit5;
2515
2516 yBit = xyBits.yBits;
2517
2518 UINT_32 yBitTemp = 0;
2519
2520 if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) ||
2521 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32))
2522 {
2523 ADDR_ASSERT(pTileInfo->bankWidth == 1 && pTileInfo->macroAspectRatio > 1);
2524 UINT_32 yBitToCheck = QLog2(pTileInfo->banks) - 1;
2525
2526 ADDR_ASSERT(yBitToCheck <= 3);
2527
2528 yBitTemp = _BIT(yBit, yBitToCheck);
2529
2530 xBit3 = 0;
2531 }
2532
2533 yBit = Bits2Number(4, yBit6, yBit5, yBit4, yBit3);
2534 xBit = Bits2Number(3, xBit5, xBit4, xBit3);
2535
2536 *pY += yBit * pTileInfo->bankHeight * MicroTileHeight;
2537 *pX += xBit * numPipes * pTileInfo->bankWidth * MicroTileWidth;
2538
2539 //calculate the bank and pipe bits in x, y
2540 UINT_32 xTile; //x in micro tile
2541 UINT_32 x3 = 0;
2542 UINT_32 x4 = 0;
2543 UINT_32 x5 = 0;
2544 UINT_32 x6 = 0;
2545 UINT_32 y = *pY;
2546
2547 UINT_32 pipeBit0 = _BIT(pipe,0);
2548 UINT_32 pipeBit1 = _BIT(pipe,1);
2549 UINT_32 pipeBit2 = _BIT(pipe,2);
2550
2551 UINT_32 y3 = _BIT(y, 3);
2552 UINT_32 y4 = _BIT(y, 4);
2553 UINT_32 y5 = _BIT(y, 5);
2554 UINT_32 y6 = _BIT(y, 6);
2555
2556 // bankbit0 after ^x4^x5
2557 UINT_32 bankBit00 = _BIT(bank,0);
2558 UINT_32 bankBit0 = 0;
2559
2560 switch (pTileInfo->pipeConfig)
2561 {
2562 case ADDR_PIPECFG_P2:
2563 x3 = pipeBit0 ^ y3;
2564 break;
2565 case ADDR_PIPECFG_P4_8x16:
2566 x4 = pipeBit0 ^ y3;
2567 x3 = pipeBit0 ^ y4;
2568 break;
2569 case ADDR_PIPECFG_P4_16x16:
2570 x4 = pipeBit1 ^ y4;
2571 x3 = pipeBit0 ^ y3 ^ x4;
2572 break;
2573 case ADDR_PIPECFG_P4_16x32:
2574 x4 = pipeBit1 ^ y4;
2575 x3 = pipeBit0 ^ y3 ^ x4;
2576 break;
2577 case ADDR_PIPECFG_P4_32x32:
2578 x5 = pipeBit1 ^ y5;
2579 x3 = pipeBit0 ^ y3 ^ x5;
2580 bankBit0 = yBitTemp ^ x5;
2581 x4 = bankBit00 ^ x5 ^ bankBit0;
2582 *pX += x5 * 4 * 1 * 8; // x5 * num_pipes * bank_width * 8;
2583 break;
2584 case ADDR_PIPECFG_P8_16x16_8x16:
2585 x3 = pipeBit1 ^ y5;
2586 x4 = pipeBit2 ^ y4;
2587 x5 = pipeBit0 ^ y3 ^ x4;
2588 break;
2589 case ADDR_PIPECFG_P8_16x32_8x16:
2590 x3 = pipeBit1 ^ y4;
2591 x4 = pipeBit2 ^ y5;
2592 x5 = pipeBit0 ^ y3 ^ x4;
2593 break;
2594 case ADDR_PIPECFG_P8_32x32_8x16:
2595 x3 = pipeBit1 ^ y4;
2596 x5 = pipeBit2 ^ y5;
2597 x4 = pipeBit0 ^ y3 ^ x5;
2598 break;
2599 case ADDR_PIPECFG_P8_16x32_16x16:
2600 x4 = pipeBit2 ^ y5;
2601 x5 = pipeBit1 ^ y4;
2602 x3 = pipeBit0 ^ y3 ^ x4;
2603 break;
2604 case ADDR_PIPECFG_P8_32x32_16x16:
2605 x5 = pipeBit2 ^ y5;
2606 x4 = pipeBit1 ^ y4;
2607 x3 = pipeBit0 ^ y3 ^ x4;
2608 break;
2609 case ADDR_PIPECFG_P8_32x32_16x32:
2610 x5 = pipeBit2 ^ y5;
2611 x4 = pipeBit1 ^ y6;
2612 x3 = pipeBit0 ^ y3 ^ x4;
2613 break;
2614 case ADDR_PIPECFG_P8_32x64_32x32:
2615 x6 = pipeBit1 ^ y5;
2616 x5 = pipeBit2 ^ y6;
2617 x3 = pipeBit0 ^ y3 ^ x5;
2618 bankBit0 = yBitTemp ^ x6;
2619 x4 = bankBit00 ^ x5 ^ bankBit0;
2620 *pX += x6 * 8 * 1 * 8; // x6 * num_pipes * bank_width * 8;
2621 break;
2622 default:
2623 ADDR_ASSERT_ALWAYS();
2624 }
2625
2626 xTile = Bits2Number(3, x5, x4, x3);
2627
2628 *pX += xTile << 3;
2629 }
2630
2631 /**
2632 ****************************************************************************************************
2633 * SiLib::HwlPreAdjustBank
2634 *
2635 * @brief
2636 * Adjust bank before calculating address acoording to bank/pipe
2637 * @return
2638 * Adjusted bank
2639 ****************************************************************************************************
2640 */
2641 UINT_32 SiLib::HwlPreAdjustBank(
2642 UINT_32 tileX, ///< [in] x coordinate in unit of tile
2643 UINT_32 bank, ///< [in] bank
2644 ADDR_TILEINFO* pTileInfo ///< [in] tile info
2645 ) const
2646 {
2647 if (((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) ||
2648 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)) && (pTileInfo->bankWidth == 1))
2649 {
2650 UINT_32 bankBit0 = _BIT(bank, 0);
2651 UINT_32 x4 = _BIT(tileX, 1);
2652 UINT_32 x5 = _BIT(tileX, 2);
2653
2654 bankBit0 = bankBit0 ^ x4 ^ x5;
2655 bank |= bankBit0;
2656
2657 ADDR_ASSERT(pTileInfo->macroAspectRatio > 1);
2658 }
2659
2660 return bank;
2661 }
2662
2663 /**
2664 ****************************************************************************************************
2665 * SiLib::HwlComputeSurfaceInfo
2666 *
2667 * @brief
2668 * Entry of si's ComputeSurfaceInfo
2669 * @return
2670 * ADDR_E_RETURNCODE
2671 ****************************************************************************************************
2672 */
2673 ADDR_E_RETURNCODE SiLib::HwlComputeSurfaceInfo(
2674 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input structure
2675 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] output structure
2676 ) const
2677 {
2678 pOut->tileIndex = pIn->tileIndex;
2679
2680 ADDR_E_RETURNCODE retCode = EgBasedLib::HwlComputeSurfaceInfo(pIn, pOut);
2681
2682 UINT_32 tileIndex = static_cast<UINT_32>(pOut->tileIndex);
2683
2684 if (((pIn->flags.needEquation == TRUE) ||
2685 (pIn->flags.preferEquation == TRUE)) &&
2686 (pIn->numSamples <= 1) &&
2687 (tileIndex < TileTableSize))
2688 {
2689 static const UINT_32 SiUncompressDepthTileIndex = 3;
2690
2691 if ((pIn->numSlices > 1) &&
2692 (IsMacroTiled(pOut->tileMode) == TRUE) &&
2693 ((m_chipFamily == ADDR_CHIP_FAMILY_SI) ||
2694 (IsPrtTileMode(pOut->tileMode) == FALSE)))
2695 {
2696 pOut->equationIndex = ADDR_INVALID_EQUATION_INDEX;
2697 }
2698 else if ((pIn->flags.prt == FALSE) &&
2699 (m_uncompressDepthEqIndex != 0) &&
2700 (tileIndex == SiUncompressDepthTileIndex))
2701 {
2702 pOut->equationIndex = m_uncompressDepthEqIndex + Log2(pIn->bpp >> 3);
2703 }
2704 else
2705 {
2706
2707 pOut->equationIndex = m_equationLookupTable[Log2(pIn->bpp >> 3)][tileIndex];
2708 }
2709
2710 if (pOut->equationIndex != ADDR_INVALID_EQUATION_INDEX)
2711 {
2712 pOut->blockWidth = m_blockWidth[pOut->equationIndex];
2713
2714 pOut->blockHeight = m_blockHeight[pOut->equationIndex];
2715
2716 pOut->blockSlices = m_blockSlices[pOut->equationIndex];
2717 }
2718 }
2719 else
2720 {
2721 pOut->equationIndex = ADDR_INVALID_EQUATION_INDEX;
2722 }
2723
2724 return retCode;
2725 }
2726
2727 /**
2728 ****************************************************************************************************
2729 * SiLib::HwlComputeMipLevel
2730 * @brief
2731 * Compute MipLevel info (including level 0)
2732 * @return
2733 * TRUE if HWL's handled
2734 ****************************************************************************************************
2735 */
2736 BOOL_32 SiLib::HwlComputeMipLevel(
2737 ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in,out] Input structure
2738 ) const
2739 {
2740 // basePitch is calculated from level 0 so we only check this for mipLevel > 0
2741 if (pIn->mipLevel > 0)
2742 {
2743 // Note: Don't check expand 3x formats(96 bit) as the basePitch is not pow2 even if
2744 // we explicity set pow2Pad flag. The 3x base pitch is padded to pow2 but after being
2745 // divided by expandX factor (3) - to program texture pitch, the basePitch is never pow2.
2746 if (ElemLib::IsExpand3x(pIn->format) == FALSE)
2747 {
2748 // Sublevel pitches are generated from base level pitch instead of width on SI
2749 // If pow2Pad is 0, we don't assert - as this is not really used for a mip chain
2750 ADDR_ASSERT((pIn->flags.pow2Pad == FALSE) ||
2751 ((pIn->basePitch != 0) && IsPow2(pIn->basePitch)));
2752 }
2753
2754 if (pIn->basePitch != 0)
2755 {
2756 pIn->width = Max(1u, pIn->basePitch >> pIn->mipLevel);
2757 }
2758 }
2759
2760 // pow2Pad is done in PostComputeMipLevel
2761
2762 return TRUE;
2763 }
2764
2765 /**
2766 ****************************************************************************************************
2767 * SiLib::HwlCheckLastMacroTiledLvl
2768 *
2769 * @brief
2770 * Sets pOut->last2DLevel to TRUE if it is
2771 * @note
2772 *
2773 ****************************************************************************************************
2774 */
2775 VOID SiLib::HwlCheckLastMacroTiledLvl(
2776 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] Input structure
2777 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out] Output structure (used as input, too)
2778 ) const
2779 {
2780 // pow2Pad covers all mipmap cases
2781 if (pIn->flags.pow2Pad)
2782 {
2783 ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
2784
2785 UINT_32 nextPitch;
2786 UINT_32 nextHeight;
2787 UINT_32 nextSlices;
2788
2789 AddrTileMode nextTileMode;
2790
2791 if (pIn->mipLevel == 0 || pIn->basePitch == 0)
2792 {
2793 // Base level or fail-safe case (basePitch == 0)
2794 nextPitch = pOut->pitch >> 1;
2795 }
2796 else
2797 {
2798 // Sub levels
2799 nextPitch = pIn->basePitch >> (pIn->mipLevel + 1);
2800 }
2801
2802 // nextHeight must be shifted from this level's original height rather than a pow2 padded
2803 // one but this requires original height stored somewhere (pOut->height)
2804 ADDR_ASSERT(pOut->height != 0);
2805
2806 // next level's height is just current level's >> 1 in pixels
2807 nextHeight = pOut->height >> 1;
2808 // Special format such as FMT_1 and FMT_32_32_32 can be linear only so we consider block
2809 // compressed foramts
2810 if (ElemLib::IsBlockCompressed(pIn->format))
2811 {
2812 nextHeight = (nextHeight + 3) / 4;
2813 }
2814 nextHeight = NextPow2(nextHeight);
2815
2816 // nextSlices may be 0 if this level's is 1
2817 if (pIn->flags.volume)
2818 {
2819 nextSlices = Max(1u, pIn->numSlices >> 1);
2820 }
2821 else
2822 {
2823 nextSlices = pIn->numSlices;
2824 }
2825
2826 nextTileMode = ComputeSurfaceMipLevelTileMode(pIn->tileMode,
2827 pIn->bpp,
2828 nextPitch,
2829 nextHeight,
2830 nextSlices,
2831 pIn->numSamples,
2832 pOut->blockWidth,
2833 pOut->blockHeight,
2834 pOut->pTileInfo);
2835
2836 pOut->last2DLevel = IsMicroTiled(nextTileMode);
2837 }
2838 }
2839
2840 /**
2841 ****************************************************************************************************
2842 * SiLib::HwlDegradeThickTileMode
2843 *
2844 * @brief
2845 * Degrades valid tile mode for thick modes if needed
2846 *
2847 * @return
2848 * Suitable tile mode
2849 ****************************************************************************************************
2850 */
2851 AddrTileMode SiLib::HwlDegradeThickTileMode(
2852 AddrTileMode baseTileMode, ///< base tile mode
2853 UINT_32 numSlices, ///< current number of slices
2854 UINT_32* pBytesPerTile ///< [in,out] pointer to bytes per slice
2855 ) const
2856 {
2857 return EgBasedLib::HwlDegradeThickTileMode(baseTileMode, numSlices, pBytesPerTile);
2858 }
2859
2860 /**
2861 ****************************************************************************************************
2862 * SiLib::HwlTileInfoEqual
2863 *
2864 * @brief
2865 * Return TRUE if all field are equal
2866 * @note
2867 * Only takes care of current HWL's data
2868 ****************************************************************************************************
2869 */
2870 BOOL_32 SiLib::HwlTileInfoEqual(
2871 const ADDR_TILEINFO* pLeft, ///<[in] Left compare operand
2872 const ADDR_TILEINFO* pRight ///<[in] Right compare operand
2873 ) const
2874 {
2875 BOOL_32 equal = FALSE;
2876
2877 if (pLeft->pipeConfig == pRight->pipeConfig)
2878 {
2879 equal = EgBasedLib::HwlTileInfoEqual(pLeft, pRight);
2880 }
2881
2882 return equal;
2883 }
2884
2885 /**
2886 ****************************************************************************************************
2887 * SiLib::GetTileSettings
2888 *
2889 * @brief
2890 * Get tile setting infos by index.
2891 * @return
2892 * Tile setting info.
2893 ****************************************************************************************************
2894 */
2895 const TileConfig* SiLib::GetTileSetting(
2896 UINT_32 index ///< [in] Tile index
2897 ) const
2898 {
2899 ADDR_ASSERT(index < m_noOfEntries);
2900 return &m_tileTable[index];
2901 }
2902
2903 /**
2904 ****************************************************************************************************
2905 * SiLib::HwlPostCheckTileIndex
2906 *
2907 * @brief
2908 * Map a tile setting to index if curIndex is invalid, otherwise check if curIndex matches
2909 * tile mode/type/info and change the index if needed
2910 * @return
2911 * Tile index.
2912 ****************************************************************************************************
2913 */
2914 INT_32 SiLib::HwlPostCheckTileIndex(
2915 const ADDR_TILEINFO* pInfo, ///< [in] Tile Info
2916 AddrTileMode mode, ///< [in] Tile mode
2917 AddrTileType type, ///< [in] Tile type
2918 INT curIndex ///< [in] Current index assigned in HwlSetupTileInfo
2919 ) const
2920 {
2921 INT_32 index = curIndex;
2922
2923 if (mode == ADDR_TM_LINEAR_GENERAL)
2924 {
2925 index = TileIndexLinearGeneral;
2926 }
2927 else
2928 {
2929 BOOL_32 macroTiled = IsMacroTiled(mode);
2930
2931 // We need to find a new index if either of them is true
2932 // 1. curIndex is invalid
2933 // 2. tile mode is changed
2934 // 3. tile info does not match for macro tiled
2935 if ((index == TileIndexInvalid ||
2936 (mode != m_tileTable[index].mode) ||
2937 (macroTiled && (HwlTileInfoEqual(pInfo, &m_tileTable[index].info) == FALSE))))
2938 {
2939 for (index = 0; index < static_cast<INT_32>(m_noOfEntries); index++)
2940 {
2941 if (macroTiled)
2942 {
2943 // macro tile modes need all to match
2944 if (HwlTileInfoEqual(pInfo, &m_tileTable[index].info) &&
2945 (mode == m_tileTable[index].mode) &&
2946 (type == m_tileTable[index].type))
2947 {
2948 break;
2949 }
2950 }
2951 else if (mode == ADDR_TM_LINEAR_ALIGNED)
2952 {
2953 // linear mode only needs tile mode to match
2954 if (mode == m_tileTable[index].mode)
2955 {
2956 break;
2957 }
2958 }
2959 else
2960 {
2961 // micro tile modes only need tile mode and tile type to match
2962 if (mode == m_tileTable[index].mode &&
2963 type == m_tileTable[index].type)
2964 {
2965 break;
2966 }
2967 }
2968 }
2969 }
2970 }
2971
2972 ADDR_ASSERT(index < static_cast<INT_32>(m_noOfEntries));
2973
2974 if (index >= static_cast<INT_32>(m_noOfEntries))
2975 {
2976 index = TileIndexInvalid;
2977 }
2978
2979 return index;
2980 }
2981
2982 /**
2983 ****************************************************************************************************
2984 * SiLib::HwlSetupTileCfg
2985 *
2986 * @brief
2987 * Map tile index to tile setting.
2988 * @return
2989 * ADDR_E_RETURNCODE
2990 ****************************************************************************************************
2991 */
2992 ADDR_E_RETURNCODE SiLib::HwlSetupTileCfg(
2993 UINT_32 bpp, ///< Bits per pixel
2994 INT_32 index, ///< Tile index
2995 INT_32 macroModeIndex, ///< Index in macro tile mode table(CI)
2996 ADDR_TILEINFO* pInfo, ///< [out] Tile Info
2997 AddrTileMode* pMode, ///< [out] Tile mode
2998 AddrTileType* pType ///< [out] Tile type
2999 ) const
3000 {
3001 ADDR_E_RETURNCODE returnCode = ADDR_OK;
3002
3003 // Global flag to control usage of tileIndex
3004 if (UseTileIndex(index))
3005 {
3006 if (index == TileIndexLinearGeneral)
3007 {
3008 if (pMode)
3009 {
3010 *pMode = ADDR_TM_LINEAR_GENERAL;
3011 }
3012
3013 if (pType)
3014 {
3015 *pType = ADDR_DISPLAYABLE;
3016 }
3017
3018 if (pInfo)
3019 {
3020 pInfo->banks = 2;
3021 pInfo->bankWidth = 1;
3022 pInfo->bankHeight = 1;
3023 pInfo->macroAspectRatio = 1;
3024 pInfo->tileSplitBytes = 64;
3025 pInfo->pipeConfig = ADDR_PIPECFG_P2;
3026 }
3027 }
3028 else if (static_cast<UINT_32>(index) >= m_noOfEntries)
3029 {
3030 returnCode = ADDR_INVALIDPARAMS;
3031 }
3032 else
3033 {
3034 const TileConfig* pCfgTable = GetTileSetting(index);
3035
3036 if (pInfo)
3037 {
3038 *pInfo = pCfgTable->info;
3039 }
3040 else
3041 {
3042 if (IsMacroTiled(pCfgTable->mode))
3043 {
3044 returnCode = ADDR_INVALIDPARAMS;
3045 }
3046 }
3047
3048 if (pMode)
3049 {
3050 *pMode = pCfgTable->mode;
3051 }
3052
3053 if (pType)
3054 {
3055 *pType = pCfgTable->type;
3056 }
3057 }
3058 }
3059
3060 return returnCode;
3061 }
3062
3063 /**
3064 ****************************************************************************************************
3065 * SiLib::ReadGbTileMode
3066 *
3067 * @brief
3068 * Convert GB_TILE_MODE HW value to TileConfig.
3069 * @return
3070 * NA.
3071 ****************************************************************************************************
3072 */
3073 VOID SiLib::ReadGbTileMode(
3074 UINT_32 regValue, ///< [in] GB_TILE_MODE register
3075 TileConfig* pCfg ///< [out] output structure
3076 ) const
3077 {
3078 GB_TILE_MODE gbTileMode;
3079 gbTileMode.val = regValue;
3080
3081 pCfg->type = static_cast<AddrTileType>(gbTileMode.f.micro_tile_mode);
3082 pCfg->info.bankHeight = 1 << gbTileMode.f.bank_height;
3083 pCfg->info.bankWidth = 1 << gbTileMode.f.bank_width;
3084 pCfg->info.banks = 1 << (gbTileMode.f.num_banks + 1);
3085 pCfg->info.macroAspectRatio = 1 << gbTileMode.f.macro_tile_aspect;
3086 pCfg->info.tileSplitBytes = 64 << gbTileMode.f.tile_split;
3087 pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);
3088
3089 UINT_32 regArrayMode = gbTileMode.f.array_mode;
3090
3091 pCfg->mode = static_cast<AddrTileMode>(regArrayMode);
3092
3093 if (regArrayMode == 8) //ARRAY_2D_TILED_XTHICK
3094 {
3095 pCfg->mode = ADDR_TM_2D_TILED_XTHICK;
3096 }
3097 else if (regArrayMode >= 14) //ARRAY_3D_TILED_XTHICK
3098 {
3099 pCfg->mode = static_cast<AddrTileMode>(pCfg->mode + 3);
3100 }
3101 }
3102
3103 /**
3104 ****************************************************************************************************
3105 * SiLib::InitTileSettingTable
3106 *
3107 * @brief
3108 * Initialize the ADDR_TILE_CONFIG table.
3109 * @return
3110 * TRUE if tile table is correctly initialized
3111 ****************************************************************************************************
3112 */
3113 BOOL_32 SiLib::InitTileSettingTable(
3114 const UINT_32* pCfg, ///< [in] Pointer to table of tile configs
3115 UINT_32 noOfEntries ///< [in] Numbe of entries in the table above
3116 )
3117 {
3118 BOOL_32 initOk = TRUE;
3119
3120 ADDR_ASSERT(noOfEntries <= TileTableSize);
3121
3122 memset(m_tileTable, 0, sizeof(m_tileTable));
3123
3124 if (noOfEntries != 0)
3125 {
3126 m_noOfEntries = noOfEntries;
3127 }
3128 else
3129 {
3130 m_noOfEntries = TileTableSize;
3131 }
3132
3133 if (pCfg) // From Client
3134 {
3135 for (UINT_32 i = 0; i < m_noOfEntries; i++)
3136 {
3137 ReadGbTileMode(*(pCfg + i), &m_tileTable[i]);
3138 }
3139 }
3140 else
3141 {
3142 ADDR_ASSERT_ALWAYS();
3143 initOk = FALSE;
3144 }
3145
3146 if (initOk)
3147 {
3148 ADDR_ASSERT(m_tileTable[TILEINDEX_LINEAR_ALIGNED].mode == ADDR_TM_LINEAR_ALIGNED);
3149 }
3150
3151 return initOk;
3152 }
3153
3154 /**
3155 ****************************************************************************************************
3156 * SiLib::HwlGetTileIndex
3157 *
3158 * @brief
3159 * Return the virtual/real index for given mode/type/info
3160 * @return
3161 * ADDR_OK if successful.
3162 ****************************************************************************************************
3163 */
3164 ADDR_E_RETURNCODE SiLib::HwlGetTileIndex(
3165 const ADDR_GET_TILEINDEX_INPUT* pIn,
3166 ADDR_GET_TILEINDEX_OUTPUT* pOut) const
3167 {
3168 ADDR_E_RETURNCODE returnCode = ADDR_OK;
3169
3170 pOut->index = HwlPostCheckTileIndex(pIn->pTileInfo, pIn->tileMode, pIn->tileType);
3171
3172 return returnCode;
3173 }
3174
3175 /**
3176 ****************************************************************************************************
3177 * SiLib::HwlFmaskPreThunkSurfInfo
3178 *
3179 * @brief
3180 * Some preparation before thunking a ComputeSurfaceInfo call for Fmask
3181 * @return
3182 * ADDR_E_RETURNCODE
3183 ****************************************************************************************************
3184 */
3185 VOID SiLib::HwlFmaskPreThunkSurfInfo(
3186 const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn, ///< [in] Input of fmask info
3187 const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut, ///< [in] Output of fmask info
3188 ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn, ///< [out] Input of thunked surface info
3189 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut ///< [out] Output of thunked surface info
3190 ) const
3191 {
3192 pSurfIn->tileIndex = pFmaskIn->tileIndex;
3193 }
3194
3195 /**
3196 ****************************************************************************************************
3197 * SiLib::HwlFmaskPostThunkSurfInfo
3198 *
3199 * @brief
3200 * Copy hwl extra field after calling thunked ComputeSurfaceInfo
3201 * @return
3202 * ADDR_E_RETURNCODE
3203 ****************************************************************************************************
3204 */
3205 VOID SiLib::HwlFmaskPostThunkSurfInfo(
3206 const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut, ///< [in] Output of surface info
3207 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut ///< [out] Output of fmask info
3208 ) const
3209 {
3210 pFmaskOut->macroModeIndex = TileIndexInvalid;
3211 pFmaskOut->tileIndex = pSurfOut->tileIndex;
3212 }
3213
3214 /**
3215 ****************************************************************************************************
3216 * SiLib::HwlComputeFmaskBits
3217 * @brief
3218 * Computes fmask bits
3219 * @return
3220 * Fmask bits
3221 ****************************************************************************************************
3222 */
3223 UINT_32 SiLib::HwlComputeFmaskBits(
3224 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
3225 UINT_32* pNumSamples
3226 ) const
3227 {
3228 UINT_32 numSamples = pIn->numSamples;
3229 UINT_32 numFrags = GetNumFragments(numSamples, pIn->numFrags);
3230 UINT_32 bpp;
3231
3232 if (numFrags != numSamples) // EQAA
3233 {
3234 ADDR_ASSERT(numFrags <= 8);
3235
3236 if (pIn->resolved == FALSE)
3237 {
3238 if (numFrags == 1)
3239 {
3240 bpp = 1;
3241 numSamples = numSamples == 16 ? 16 : 8;
3242 }
3243 else if (numFrags == 2)
3244 {
3245 ADDR_ASSERT(numSamples >= 4);
3246
3247 bpp = 2;
3248 numSamples = numSamples;
3249 }
3250 else if (numFrags == 4)
3251 {
3252 ADDR_ASSERT(numSamples >= 4);
3253
3254 bpp = 4;
3255 numSamples = numSamples;
3256 }
3257 else // numFrags == 8
3258 {
3259 ADDR_ASSERT(numSamples == 16);
3260
3261 bpp = 4;
3262 numSamples = numSamples;
3263 }
3264 }
3265 else
3266 {
3267 if (numFrags == 1)
3268 {
3269 bpp = (numSamples == 16) ? 16 : 8;
3270 numSamples = 1;
3271 }
3272 else if (numFrags == 2)
3273 {
3274 ADDR_ASSERT(numSamples >= 4);
3275
3276 bpp = numSamples*2;
3277 numSamples = 1;
3278 }
3279 else if (numFrags == 4)
3280 {
3281 ADDR_ASSERT(numSamples >= 4);
3282
3283 bpp = numSamples*4;
3284 numSamples = 1;
3285 }
3286 else // numFrags == 8
3287 {
3288 ADDR_ASSERT(numSamples >= 16);
3289
3290 bpp = 16*4;
3291 numSamples = 1;
3292 }
3293 }
3294 }
3295 else // Normal AA
3296 {
3297 if (pIn->resolved == FALSE)
3298 {
3299 bpp = ComputeFmaskNumPlanesFromNumSamples(numSamples);
3300 numSamples = numSamples == 2 ? 8 : numSamples;
3301 }
3302 else
3303 {
3304 // The same as 8XX
3305 bpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
3306 numSamples = 1; // 1x sample
3307 }
3308 }
3309
3310 SafeAssign(pNumSamples, numSamples);
3311
3312 return bpp;
3313 }
3314
3315 /**
3316 ****************************************************************************************************
3317 * SiLib::HwlOptimizeTileMode
3318 *
3319 * @brief
3320 * Optimize tile mode on SI
3321 *
3322 * @return
3323 * N/A
3324 *
3325 ****************************************************************************************************
3326 */
3327 VOID SiLib::HwlOptimizeTileMode(
3328 ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
3329 ) const
3330 {
3331 AddrTileMode tileMode = pInOut->tileMode;
3332
3333 if ((pInOut->flags.needEquation == TRUE) &&
3334 (IsMacroTiled(tileMode) == TRUE) &&
3335 (pInOut->numSamples <= 1))
3336 {
3337 UINT_32 thickness = Thickness(tileMode);
3338
3339 if (thickness > 1)
3340 {
3341 tileMode = ADDR_TM_1D_TILED_THICK;
3342 }
3343 else if (pInOut->numSlices > 1)
3344 {
3345 tileMode = ADDR_TM_1D_TILED_THIN1;
3346 }
3347 else
3348 {
3349 tileMode = ADDR_TM_2D_TILED_THIN1;
3350 }
3351 }
3352
3353 if (tileMode != pInOut->tileMode)
3354 {
3355 pInOut->tileMode = tileMode;
3356 }
3357 }
3358
3359 /**
3360 ****************************************************************************************************
3361 * SiLib::HwlOverrideTileMode
3362 *
3363 * @brief
3364 * Override tile modes (for PRT only, avoid client passes in an invalid PRT mode for SI.
3365 *
3366 * @return
3367 * N/A
3368 *
3369 ****************************************************************************************************
3370 */
3371 VOID SiLib::HwlOverrideTileMode(
3372 ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
3373 ) const
3374 {
3375 AddrTileMode tileMode = pInOut->tileMode;
3376
3377 switch (tileMode)
3378 {
3379 case ADDR_TM_PRT_TILED_THIN1:
3380 tileMode = ADDR_TM_2D_TILED_THIN1;
3381 break;
3382
3383 case ADDR_TM_PRT_TILED_THICK:
3384 tileMode = ADDR_TM_2D_TILED_THICK;
3385 break;
3386
3387 case ADDR_TM_PRT_2D_TILED_THICK:
3388 tileMode = ADDR_TM_2D_TILED_THICK;
3389 break;
3390
3391 case ADDR_TM_PRT_3D_TILED_THICK:
3392 tileMode = ADDR_TM_3D_TILED_THICK;
3393 break;
3394
3395 default:
3396 break;
3397 }
3398
3399 if (tileMode != pInOut->tileMode)
3400 {
3401 pInOut->tileMode = tileMode;
3402 // Only PRT tile modes are overridden for now. Revisit this once new modes are added above.
3403 pInOut->flags.prt = TRUE;
3404 }
3405 }
3406
3407 /**
3408 ****************************************************************************************************
3409 * SiLib::HwlSetPrtTileMode
3410 *
3411 * @brief
3412 * Set prt tile modes.
3413 *
3414 * @return
3415 * N/A
3416 *
3417 ****************************************************************************************************
3418 */
3419 VOID SiLib::HwlSetPrtTileMode(
3420 ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
3421 ) const
3422 {
3423 pInOut->tileMode = ADDR_TM_2D_TILED_THIN1;
3424 pInOut->tileType = (pInOut->tileType == ADDR_DEPTH_SAMPLE_ORDER) ?
3425 ADDR_DEPTH_SAMPLE_ORDER : ADDR_NON_DISPLAYABLE;
3426 pInOut->flags.prt = TRUE;
3427 }
3428
3429 /**
3430 ****************************************************************************************************
3431 * SiLib::HwlSelectTileMode
3432 *
3433 * @brief
3434 * Select tile modes.
3435 *
3436 * @return
3437 * N/A
3438 *
3439 ****************************************************************************************************
3440 */
3441 VOID SiLib::HwlSelectTileMode(
3442 ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
3443 ) const
3444 {
3445 AddrTileMode tileMode;
3446 AddrTileType tileType;
3447
3448 if (pInOut->flags.volume)
3449 {
3450 if (pInOut->numSlices >= 8)
3451 {
3452 tileMode = ADDR_TM_2D_TILED_XTHICK;
3453 }
3454 else if (pInOut->numSlices >= 4)
3455 {
3456 tileMode = ADDR_TM_2D_TILED_THICK;
3457 }
3458 else
3459 {
3460 tileMode = ADDR_TM_2D_TILED_THIN1;
3461 }
3462 tileType = ADDR_NON_DISPLAYABLE;
3463 }
3464 else
3465 {
3466 tileMode = ADDR_TM_2D_TILED_THIN1;
3467
3468 if (pInOut->flags.depth || pInOut->flags.stencil)
3469 {
3470 tileType = ADDR_DEPTH_SAMPLE_ORDER;
3471 }
3472 else if ((pInOut->bpp <= 32) ||
3473 (pInOut->flags.display == TRUE) ||
3474 (pInOut->flags.overlay == TRUE))
3475 {
3476 tileType = ADDR_DISPLAYABLE;
3477 }
3478 else
3479 {
3480 tileType = ADDR_NON_DISPLAYABLE;
3481 }
3482 }
3483
3484 if (pInOut->flags.prt)
3485 {
3486 tileMode = ADDR_TM_2D_TILED_THIN1;
3487 tileType = (tileType == ADDR_DISPLAYABLE) ? ADDR_NON_DISPLAYABLE : tileType;
3488 }
3489
3490 pInOut->tileMode = tileMode;
3491 pInOut->tileType = tileType;
3492
3493 // Optimize tile mode if possible
3494 pInOut->flags.opt4Space = TRUE;
3495
3496 // Optimize tile mode if possible
3497 OptimizeTileMode(pInOut);
3498
3499 HwlOverrideTileMode(pInOut);
3500 }
3501
3502 /**
3503 ****************************************************************************************************
3504 * SiLib::HwlComputeMaxBaseAlignments
3505 *
3506 * @brief
3507 * Gets maximum alignments
3508 * @return
3509 * maximum alignments
3510 ****************************************************************************************************
3511 */
3512 UINT_32 SiLib::HwlComputeMaxBaseAlignments() const
3513 {
3514 const UINT_32 pipes = HwlGetPipes(&m_tileTable[0].info);
3515
3516 // Initial size is 64 KiB for PRT.
3517 UINT_32 maxBaseAlign = 64 * 1024;
3518
3519 for (UINT_32 i = 0; i < m_noOfEntries; i++)
3520 {
3521 if ((IsMacroTiled(m_tileTable[i].mode) == TRUE) &&
3522 (IsPrtTileMode(m_tileTable[i].mode) == FALSE))
3523 {
3524 // The maximum tile size is 16 byte-per-pixel and either 8-sample or 8-slice.
3525 UINT_32 tileSize = Min(m_tileTable[i].info.tileSplitBytes,
3526 MicroTilePixels * 8 * 16);
3527
3528 UINT_32 baseAlign = tileSize * pipes * m_tileTable[i].info.banks *
3529 m_tileTable[i].info.bankWidth * m_tileTable[i].info.bankHeight;
3530
3531 if (baseAlign > maxBaseAlign)
3532 {
3533 maxBaseAlign = baseAlign;
3534 }
3535 }
3536 }
3537
3538 return maxBaseAlign;
3539 }
3540
3541 /**
3542 ****************************************************************************************************
3543 * SiLib::HwlComputeMaxMetaBaseAlignments
3544 *
3545 * @brief
3546 * Gets maximum alignments for metadata
3547 * @return
3548 * maximum alignments for metadata
3549 ****************************************************************************************************
3550 */
3551 UINT_32 SiLib::HwlComputeMaxMetaBaseAlignments() const
3552 {
3553 UINT_32 maxPipe = 1;
3554
3555 for (UINT_32 i = 0; i < m_noOfEntries; i++)
3556 {
3557 maxPipe = Max(maxPipe, HwlGetPipes(&m_tileTable[i].info));
3558 }
3559
3560 return m_pipeInterleaveBytes * maxPipe;
3561 }
3562
3563 /**
3564 ****************************************************************************************************
3565 * SiLib::HwlComputeSurfaceAlignmentsMacroTiled
3566 *
3567 * @brief
3568 * Hardware layer function to compute alignment request for macro tile mode
3569 *
3570 * @return
3571 * N/A
3572 *
3573 ****************************************************************************************************
3574 */
3575 VOID SiLib::HwlComputeSurfaceAlignmentsMacroTiled(
3576 AddrTileMode tileMode, ///< [in] tile mode
3577 UINT_32 bpp, ///< [in] bits per pixel
3578 ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
3579 UINT_32 mipLevel, ///< [in] mip level
3580 UINT_32 numSamples, ///< [in] number of samples
3581 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out] Surface output
3582 ) const
3583 {
3584 if ((mipLevel == 0) && (flags.prt))
3585 {
3586 UINT_32 macroTileSize = pOut->blockWidth * pOut->blockHeight * numSamples * bpp / 8;
3587
3588 if (macroTileSize < PrtTileSize)
3589 {
3590 UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
3591
3592 ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
3593
3594 pOut->pitchAlign *= numMacroTiles;
3595 pOut->baseAlign *= numMacroTiles;
3596 }
3597 }
3598 }
3599
3600 /**
3601 ****************************************************************************************************
3602 * SiLib::InitEquationTable
3603 *
3604 * @brief
3605 * Initialize Equation table.
3606 *
3607 * @return
3608 * N/A
3609 ****************************************************************************************************
3610 */
3611 VOID SiLib::InitEquationTable()
3612 {
3613 ADDR_EQUATION_KEY equationKeyTable[EquationTableSize];
3614 memset(equationKeyTable, 0, sizeof(equationKeyTable));
3615
3616 memset(m_equationTable, 0, sizeof(m_equationTable));
3617
3618 memset(m_blockWidth, 0, sizeof(m_blockWidth));
3619
3620 memset(m_blockHeight, 0, sizeof(m_blockHeight));
3621
3622 memset(m_blockSlices, 0, sizeof(m_blockSlices));
3623
3624 // Loop all possible bpp
3625 for (UINT_32 log2ElementBytes = 0; log2ElementBytes < MaxNumElementBytes; log2ElementBytes++)
3626 {
3627 // Get bits per pixel
3628 UINT_32 bpp = 1 << (log2ElementBytes + 3);
3629
3630 // Loop all possible tile index
3631 for (INT_32 tileIndex = 0; tileIndex < static_cast<INT_32>(m_noOfEntries); tileIndex++)
3632 {
3633 UINT_32 equationIndex = ADDR_INVALID_EQUATION_INDEX;
3634
3635 TileConfig tileConfig = m_tileTable[tileIndex];
3636
3637 ADDR_SURFACE_FLAGS flags = {{0}};
3638
3639 // Compute tile info, hardcode numSamples to 1 because MSAA is not supported
3640 // in swizzle pattern equation
3641 HwlComputeMacroModeIndex(tileIndex, flags, bpp, 1, &tileConfig.info, NULL, NULL);
3642
3643 // Check if the input is supported
3644 if (IsEquationSupported(bpp, tileConfig, tileIndex, log2ElementBytes) == TRUE)
3645 {
3646 ADDR_EQUATION_KEY key = {{0}};
3647
3648 // Generate swizzle equation key from bpp and tile config
3649 key.fields.log2ElementBytes = log2ElementBytes;
3650 key.fields.tileMode = tileConfig.mode;
3651 // Treat depth micro tile type and non-display micro tile type as the same key
3652 // because they have the same equation actually
3653 key.fields.microTileType = (tileConfig.type == ADDR_DEPTH_SAMPLE_ORDER) ?
3654 ADDR_NON_DISPLAYABLE : tileConfig.type;
3655 key.fields.pipeConfig = tileConfig.info.pipeConfig;
3656 key.fields.numBanksLog2 = Log2(tileConfig.info.banks);
3657 key.fields.bankWidth = tileConfig.info.bankWidth;
3658 key.fields.bankHeight = tileConfig.info.bankHeight;
3659 key.fields.macroAspectRatio = tileConfig.info.macroAspectRatio;
3660 key.fields.prt = ((m_chipFamily == ADDR_CHIP_FAMILY_SI) &&
3661 ((1 << tileIndex) & SiPrtTileIndexMask)) ? 1 : 0;
3662
3663 // Find in the table if the equation has been built based on the key
3664 for (UINT_32 i = 0; i < m_numEquations; i++)
3665 {
3666 if (key.value == equationKeyTable[i].value)
3667 {
3668 equationIndex = i;
3669 break;
3670 }
3671 }
3672
3673 // If found, just fill the index into the lookup table and no need
3674 // to generate the equation again. Otherwise, generate the equation.
3675 if (equationIndex == ADDR_INVALID_EQUATION_INDEX)
3676 {
3677 ADDR_EQUATION equation;
3678 ADDR_E_RETURNCODE retCode;
3679
3680 memset(&equation, 0, sizeof(ADDR_EQUATION));
3681
3682 // Generate the equation
3683 if (IsMicroTiled(tileConfig.mode))
3684 {
3685 retCode = ComputeMicroTileEquation(log2ElementBytes,
3686 tileConfig.mode,
3687 tileConfig.type,
3688 &equation);
3689 }
3690 else
3691 {
3692 retCode = ComputeMacroTileEquation(log2ElementBytes,
3693 tileConfig.mode,
3694 tileConfig.type,
3695 &tileConfig.info,
3696 &equation);
3697 }
3698 // Only fill the equation into the table if the return code is ADDR_OK,
3699 // otherwise if the return code is not ADDR_OK, it indicates this is not
3700 // a valid input, we do nothing but just fill invalid equation index
3701 // into the lookup table.
3702 if (retCode == ADDR_OK)
3703 {
3704 equationIndex = m_numEquations;
3705 ADDR_ASSERT(equationIndex < EquationTableSize);
3706
3707 m_blockSlices[equationIndex] = Thickness(tileConfig.mode);
3708
3709 if (IsMicroTiled(tileConfig.mode))
3710 {
3711 m_blockWidth[equationIndex] = MicroTileWidth;
3712 m_blockHeight[equationIndex] = MicroTileHeight;
3713 }
3714 else
3715 {
3716 const ADDR_TILEINFO* pTileInfo = &tileConfig.info;
3717
3718 m_blockWidth[equationIndex] =
3719 HwlGetPipes(pTileInfo) * MicroTileWidth * pTileInfo->bankWidth *
3720 pTileInfo->macroAspectRatio;
3721 m_blockHeight[equationIndex] =
3722 MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks /
3723 pTileInfo->macroAspectRatio;
3724
3725 if (key.fields.prt)
3726 {
3727 UINT_32 macroTileSize =
3728 m_blockWidth[equationIndex] * m_blockHeight[equationIndex] *
3729 bpp / 8;
3730
3731 if (macroTileSize < PrtTileSize)
3732 {
3733 UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
3734
3735 ADDR_ASSERT(macroTileSize == (1u << equation.numBits));
3736 ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
3737
3738 UINT_32 numBits = Log2(numMacroTiles);
3739
3740 UINT_32 xStart = Log2(m_blockWidth[equationIndex]) +
3741 log2ElementBytes;
3742
3743 m_blockWidth[equationIndex] *= numMacroTiles;
3744
3745 for (UINT_32 i = 0; i < numBits; i++)
3746 {
3747 equation.addr[equation.numBits + i].valid = 1;
3748 equation.addr[equation.numBits + i].index = xStart + i;
3749 }
3750
3751 equation.numBits += numBits;
3752 }
3753 }
3754 }
3755
3756 equationKeyTable[equationIndex] = key;
3757 m_equationTable[equationIndex] = equation;
3758
3759 m_numEquations++;
3760 }
3761 }
3762 }
3763
3764 // Fill the index into the lookup table, if the combination is not supported
3765 // fill the invalid equation index
3766 m_equationLookupTable[log2ElementBytes][tileIndex] = equationIndex;
3767 }
3768
3769 if (m_chipFamily == ADDR_CHIP_FAMILY_SI)
3770 {
3771 // For tile index 3 which is shared between PRT depth and uncompressed depth
3772 m_uncompressDepthEqIndex = m_numEquations;
3773
3774 for (UINT_32 log2ElemBytes = 0; log2ElemBytes < MaxNumElementBytes; log2ElemBytes++)
3775 {
3776 TileConfig tileConfig = m_tileTable[3];
3777 ADDR_EQUATION equation;
3778 ADDR_E_RETURNCODE retCode;
3779
3780 memset(&equation, 0, sizeof(ADDR_EQUATION));
3781
3782 retCode = ComputeMacroTileEquation(log2ElemBytes,
3783 tileConfig.mode,
3784 tileConfig.type,
3785 &tileConfig.info,
3786 &equation);
3787
3788 if (retCode == ADDR_OK)
3789 {
3790 UINT_32 equationIndex = m_numEquations;
3791 ADDR_ASSERT(equationIndex < EquationTableSize);
3792
3793 m_blockSlices[equationIndex] = 1;
3794
3795 const ADDR_TILEINFO* pTileInfo = &tileConfig.info;
3796
3797 m_blockWidth[equationIndex] =
3798 HwlGetPipes(pTileInfo) * MicroTileWidth * pTileInfo->bankWidth *
3799 pTileInfo->macroAspectRatio;
3800 m_blockHeight[equationIndex] =
3801 MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks /
3802 pTileInfo->macroAspectRatio;
3803
3804 m_equationTable[equationIndex] = equation;
3805
3806 m_numEquations++;
3807 }
3808 }
3809 }
3810 }
3811 }
3812
3813 /**
3814 ****************************************************************************************************
3815 * SiLib::IsEquationSupported
3816 *
3817 * @brief
3818 * Check if it is supported for given bpp and tile config to generate a equation.
3819 *
3820 * @return
3821 * TRUE if supported
3822 ****************************************************************************************************
3823 */
3824 BOOL_32 SiLib::IsEquationSupported(
3825 UINT_32 bpp, ///< Bits per pixel
3826 TileConfig tileConfig, ///< Tile config
3827 INT_32 tileIndex, ///< Tile index
3828 UINT_32 elementBytesLog2 ///< Log2 of element bytes
3829 ) const
3830 {
3831 BOOL_32 supported = TRUE;
3832
3833 // Linear tile mode is not supported in swizzle pattern equation
3834 if (IsLinear(tileConfig.mode))
3835 {
3836 supported = FALSE;
3837 }
3838 // These tile modes are for Tex2DArray and Tex3D which has depth (num_slice > 1) use,
3839 // which is not supported in swizzle pattern equation due to slice rotation
3840 else if ((tileConfig.mode == ADDR_TM_2D_TILED_THICK) ||
3841 (tileConfig.mode == ADDR_TM_2D_TILED_XTHICK) ||
3842 (tileConfig.mode == ADDR_TM_3D_TILED_THIN1) ||
3843 (tileConfig.mode == ADDR_TM_3D_TILED_THICK) ||
3844 (tileConfig.mode == ADDR_TM_3D_TILED_XTHICK))
3845 {
3846 supported = FALSE;
3847 }
3848 // Only 8bpp(stencil), 16bpp and 32bpp is supported for depth
3849 else if ((tileConfig.type == ADDR_DEPTH_SAMPLE_ORDER) && (bpp > 32))
3850 {
3851 supported = FALSE;
3852 }
3853 // Tile split is not supported in swizzle pattern equation
3854 else if (IsMacroTiled(tileConfig.mode))
3855 {
3856 UINT_32 thickness = Thickness(tileConfig.mode);
3857 if (((bpp >> 3) * MicroTilePixels * thickness) > tileConfig.info.tileSplitBytes)
3858 {
3859 supported = FALSE;
3860 }
3861
3862 if ((supported == TRUE) && (m_chipFamily == ADDR_CHIP_FAMILY_SI))
3863 {
3864 supported = m_EquationSupport[tileIndex][elementBytesLog2];
3865 }
3866 }
3867
3868 return supported;
3869 }
3870
3871 } // V1
3872 } // Addr