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[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "sid.h"
28 #include "gfx9d.h"
29
30 #include "util/u_math.h"
31
32 #include <stdio.h>
33
34 #include <xf86drm.h>
35 #include <amdgpu_drm.h>
36
37 #include <amdgpu.h>
38
39 #define CIK_TILE_MODE_COLOR_2D 14
40
41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
42 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
56
57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
58 {
59 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
60
61 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
62 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
63 return 2;
64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
68 return 4;
69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
76 return 8;
77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
79 return 16;
80 default:
81 fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
82 assert(!"this should never occur");
83 return 2;
84 }
85 }
86
87 static bool has_syncobj(int fd)
88 {
89 uint64_t value;
90 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
91 return false;
92 return value ? true : false;
93 }
94
95 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
96 struct radeon_info *info,
97 struct amdgpu_gpu_info *amdinfo)
98 {
99 struct amdgpu_buffer_size_alignments alignment_info = {};
100 struct amdgpu_heap_info vram, vram_vis, gtt;
101 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
102 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
103 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
104 struct amdgpu_gds_resource_info gds = {};
105 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
106 int r, i, j;
107 drmDevicePtr devinfo;
108
109 /* Get PCI info. */
110 r = drmGetDevice2(fd, 0, &devinfo);
111 if (r) {
112 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
113 return false;
114 }
115 info->pci_domain = devinfo->businfo.pci->domain;
116 info->pci_bus = devinfo->businfo.pci->bus;
117 info->pci_dev = devinfo->businfo.pci->dev;
118 info->pci_func = devinfo->businfo.pci->func;
119 drmFreeDevice(&devinfo);
120
121 /* Query hardware and driver information. */
122 r = amdgpu_query_gpu_info(dev, amdinfo);
123 if (r) {
124 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
125 return false;
126 }
127
128 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
129 if (r) {
130 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
131 return false;
132 }
133
134 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
135 if (r) {
136 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
137 return false;
138 }
139
140 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
141 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
142 &vram_vis);
143 if (r) {
144 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
145 return false;
146 }
147
148 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
149 if (r) {
150 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
151 return false;
152 }
153
154 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
155 if (r) {
156 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
157 return false;
158 }
159
160 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
161 if (r) {
162 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
163 return false;
164 }
165
166 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
167 if (r) {
168 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
169 return false;
170 }
171
172 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
173 if (r) {
174 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
175 return false;
176 }
177
178 if (info->drm_major == 3 && info->drm_minor >= 17) {
179 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
180 if (r) {
181 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
182 return false;
183 }
184 }
185
186 if (info->drm_major == 3 && info->drm_minor >= 17) {
187 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
188 if (r) {
189 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
190 return false;
191 }
192 }
193
194 if (info->drm_major == 3 && info->drm_minor >= 17) {
195 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
196 if (r) {
197 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
198 return false;
199 }
200 }
201
202 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
203 &info->me_fw_version,
204 &info->me_fw_feature);
205 if (r) {
206 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
207 return false;
208 }
209
210 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
211 &info->pfp_fw_version,
212 &info->pfp_fw_feature);
213 if (r) {
214 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
215 return false;
216 }
217
218 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
219 &info->ce_fw_version,
220 &info->ce_fw_feature);
221 if (r) {
222 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
223 return false;
224 }
225
226 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
227 &uvd_version, &uvd_feature);
228 if (r) {
229 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
230 return false;
231 }
232
233 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
234 if (r) {
235 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
236 return false;
237 }
238
239 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
240 &vce_version, &vce_feature);
241 if (r) {
242 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
243 return false;
244 }
245
246 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
247 if (r) {
248 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
249 return false;
250 }
251
252 r = amdgpu_query_gds_info(dev, &gds);
253 if (r) {
254 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
255 return false;
256 }
257
258 /* Set chip identification. */
259 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
260 info->vce_harvest_config = amdinfo->vce_harvest_config;
261
262 switch (info->pci_id) {
263 #define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
264 #include "pci_ids/radeonsi_pci_ids.h"
265 #undef CHIPSET
266
267 default:
268 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
269 return false;
270 }
271
272 if (info->family >= CHIP_VEGA10)
273 info->chip_class = GFX9;
274 else if (info->family >= CHIP_TONGA)
275 info->chip_class = VI;
276 else if (info->family >= CHIP_BONAIRE)
277 info->chip_class = CIK;
278 else if (info->family >= CHIP_TAHITI)
279 info->chip_class = SI;
280 else {
281 fprintf(stderr, "amdgpu: Unknown family.\n");
282 return false;
283 }
284
285 /* Set which chips have dedicated VRAM. */
286 info->has_dedicated_vram =
287 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
288
289 /* Set hardware information. */
290 info->gart_size = gtt.heap_size;
291 info->vram_size = vram.heap_size;
292 info->vram_vis_size = vram_vis.heap_size;
293 info->gds_size = gds.gds_total_size;
294 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
295 /* The kernel can split large buffers in VRAM but not in GTT, so large
296 * allocations can fail or cause buffer movement failures in the kernel.
297 */
298 info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 0.7);
299 /* convert the shader clock from KHz to MHz */
300 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
301 info->max_se = amdinfo->num_shader_engines;
302 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
303 info->has_hw_decode =
304 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
305 info->uvd_fw_version =
306 uvd.available_rings ? uvd_version : 0;
307 info->vce_fw_version =
308 vce.available_rings ? vce_version : 0;
309 info->uvd_enc_supported =
310 uvd_enc.available_rings ? true : false;
311 info->has_userptr = true;
312 info->has_syncobj = has_syncobj(fd);
313 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
314 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
315 info->has_ctx_priority = info->drm_minor >= 22;
316 /* TODO: Enable this once the kernel handles it efficiently. */
317 info->has_local_buffers = info->drm_minor >= 20 &&
318 !info->has_dedicated_vram;
319 info->kernel_flushes_hdp_before_ib = true;
320 info->htile_cmask_support_1d_tiling = true;
321 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
322 info->has_bo_metadata = true;
323 info->has_gpu_reset_status_query = true;
324 info->has_gpu_reset_counter_query = false;
325 info->has_eqaa_surface_allocator = true;
326 info->has_format_bc1_through_bc7 = true;
327 /* DRM 3.1.0 doesn't flush TC for VI correctly. */
328 info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
329 info->drm_minor >= 2;
330 info->has_indirect_compute_dispatch = true;
331 /* SI doesn't support unaligned loads. */
332 info->has_unaligned_shader_loads = info->chip_class != SI;
333
334 info->num_render_backends = amdinfo->rb_pipes;
335 /* The value returned by the kernel driver was wrong. */
336 if (info->family == CHIP_KAVERI)
337 info->num_render_backends = 2;
338
339 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
340 if (!info->clock_crystal_freq) {
341 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
342 info->clock_crystal_freq = 1;
343 }
344 info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
345 info->gb_addr_config = amdinfo->gb_addr_cfg;
346 if (info->chip_class == GFX9) {
347 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
348 info->pipe_interleave_bytes =
349 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
350 } else {
351 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
352 info->pipe_interleave_bytes =
353 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
354 }
355 info->r600_has_virtual_memory = true;
356
357 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
358 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
359
360 info->num_sdma_rings = util_bitcount(dma.available_rings);
361 info->num_compute_rings = util_bitcount(compute.available_rings);
362
363 /* Get the number of good compute units. */
364 info->num_good_compute_units = 0;
365 for (i = 0; i < info->max_se; i++)
366 for (j = 0; j < info->max_sh_per_se; j++)
367 info->num_good_compute_units +=
368 util_bitcount(amdinfo->cu_bitmap[i][j]);
369
370 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
371 sizeof(amdinfo->gb_tile_mode));
372 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
373
374 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
375 sizeof(amdinfo->gb_macro_tile_mode));
376
377 info->pte_fragment_size = alignment_info.size_local;
378 info->gart_page_size = alignment_info.size_remote;
379
380 if (info->chip_class == SI)
381 info->gfx_ib_pad_with_type2 = TRUE;
382
383 unsigned ib_align = 0;
384 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
385 ib_align = MAX2(ib_align, compute.ib_start_alignment);
386 ib_align = MAX2(ib_align, dma.ib_start_alignment);
387 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
388 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
389 ib_align = MAX2(ib_align, vce.ib_start_alignment);
390 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
391 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
392 assert(ib_align);
393 info->ib_start_alignment = ib_align;
394
395 return true;
396 }
397
398 void ac_compute_driver_uuid(char *uuid, size_t size)
399 {
400 char amd_uuid[] = "AMD-MESA-DRV";
401
402 assert(size >= sizeof(amd_uuid));
403
404 memset(uuid, 0, size);
405 strncpy(uuid, amd_uuid, size);
406 }
407
408 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
409 {
410 uint32_t *uint_uuid = (uint32_t*)uuid;
411
412 assert(size >= sizeof(uint32_t)*4);
413
414 /**
415 * Use the device info directly instead of using a sha1. GL/VK UUIDs
416 * are 16 byte vs 20 byte for sha1, and the truncation that would be
417 * required would get rid of part of the little entropy we have.
418 * */
419 memset(uuid, 0, size);
420 uint_uuid[0] = info->pci_domain;
421 uint_uuid[1] = info->pci_bus;
422 uint_uuid[2] = info->pci_dev;
423 uint_uuid[3] = info->pci_func;
424 }
425
426 void ac_print_gpu_info(struct radeon_info *info)
427 {
428 printf("Device info:\n");
429 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
430 info->pci_domain, info->pci_bus,
431 info->pci_dev, info->pci_func);
432 printf(" pci_id = 0x%x\n", info->pci_id);
433 printf(" family = %i\n", info->family);
434 printf(" chip_class = %i\n", info->chip_class);
435 printf(" num_compute_rings = %u\n", info->num_compute_rings);
436 printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
437 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
438 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
439
440 printf("Memory info:\n");
441 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
442 printf(" gart_page_size = %u\n", info->gart_page_size);
443 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
444 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
445 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
446 printf(" gds_size = %u kB\n", info->gds_size / 1024);
447 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
448 printf(" max_alloc_size = %i MB\n",
449 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
450 printf(" min_alloc_size = %u\n", info->min_alloc_size);
451 printf(" address32_hi = %u\n", info->address32_hi);
452 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
453
454 printf("CP info:\n");
455 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
456 printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
457 printf(" me_fw_version = %i\n", info->me_fw_version);
458 printf(" me_fw_feature = %i\n", info->me_fw_feature);
459 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
460 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
461 printf(" ce_fw_version = %i\n", info->ce_fw_version);
462 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
463
464 printf("Multimedia info:\n");
465 printf(" has_hw_decode = %u\n", info->has_hw_decode);
466 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
467 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
468 printf(" vce_fw_version = %u\n", info->vce_fw_version);
469 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
470
471 printf("Kernel & winsys capabilities:\n");
472 printf(" drm = %i.%i.%i\n", info->drm_major,
473 info->drm_minor, info->drm_patchlevel);
474 printf(" has_userptr = %i\n", info->has_userptr);
475 printf(" has_syncobj = %u\n", info->has_syncobj);
476 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
477 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
478 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
479 printf(" has_local_buffers = %u\n", info->has_local_buffers);
480 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
481 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
482 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
483 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
484 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
485 printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
486 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
487 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
488 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
489 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
490 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
491
492 printf("Shader core info:\n");
493 printf(" max_shader_clock = %i\n", info->max_shader_clock);
494 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
495 printf(" max_se = %i\n", info->max_se);
496 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
497
498 printf("Render backend info:\n");
499 printf(" num_render_backends = %i\n", info->num_render_backends);
500 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
501 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
502 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
503 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
504
505 printf("GB_ADDR_CONFIG:\n");
506 if (info->chip_class >= GFX9) {
507 printf(" num_pipes = %u\n",
508 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
509 printf(" pipe_interleave_size = %u\n",
510 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
511 printf(" max_compressed_frags = %u\n",
512 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
513 printf(" bank_interleave_size = %u\n",
514 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
515 printf(" num_banks = %u\n",
516 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
517 printf(" shader_engine_tile_size = %u\n",
518 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
519 printf(" num_shader_engines = %u\n",
520 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
521 printf(" num_gpus = %u (raw)\n",
522 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
523 printf(" multi_gpu_tile_size = %u (raw)\n",
524 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
525 printf(" num_rb_per_se = %u\n",
526 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
527 printf(" row_size = %u\n",
528 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
529 printf(" num_lower_pipes = %u (raw)\n",
530 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
531 printf(" se_enable = %u (raw)\n",
532 G_0098F8_SE_ENABLE(info->gb_addr_config));
533 } else {
534 printf(" num_pipes = %u\n",
535 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
536 printf(" pipe_interleave_size = %u\n",
537 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
538 printf(" bank_interleave_size = %u\n",
539 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
540 printf(" num_shader_engines = %u\n",
541 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
542 printf(" shader_engine_tile_size = %u\n",
543 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
544 printf(" num_gpus = %u (raw)\n",
545 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
546 printf(" multi_gpu_tile_size = %u (raw)\n",
547 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
548 printf(" row_size = %u\n",
549 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
550 printf(" num_lower_pipes = %u (raw)\n",
551 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
552 }
553 }
554
555 int
556 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
557 {
558 if (chip_class >= GFX9)
559 return -1;
560
561 switch (family) {
562 case CHIP_OLAND:
563 case CHIP_HAINAN:
564 case CHIP_KAVERI:
565 case CHIP_KABINI:
566 case CHIP_MULLINS:
567 case CHIP_ICELAND:
568 case CHIP_CARRIZO:
569 case CHIP_STONEY:
570 return 16;
571 case CHIP_TAHITI:
572 case CHIP_PITCAIRN:
573 case CHIP_VERDE:
574 case CHIP_BONAIRE:
575 case CHIP_HAWAII:
576 case CHIP_TONGA:
577 case CHIP_FIJI:
578 case CHIP_POLARIS10:
579 case CHIP_POLARIS11:
580 case CHIP_POLARIS12:
581 case CHIP_VEGAM:
582 return 32;
583 default:
584 unreachable("Unknown GPU");
585 }
586 }
587
588 void
589 ac_get_raster_config(struct radeon_info *info,
590 uint32_t *raster_config_p,
591 uint32_t *raster_config_1_p)
592 {
593 unsigned raster_config, raster_config_1;
594
595 switch (info->family) {
596 /* 1 SE / 1 RB */
597 case CHIP_HAINAN:
598 case CHIP_KABINI:
599 case CHIP_MULLINS:
600 case CHIP_STONEY:
601 raster_config = 0x00000000;
602 raster_config_1 = 0x00000000;
603 break;
604 /* 1 SE / 4 RBs */
605 case CHIP_VERDE:
606 raster_config = 0x0000124a;
607 raster_config_1 = 0x00000000;
608 break;
609 /* 1 SE / 2 RBs (Oland is special) */
610 case CHIP_OLAND:
611 raster_config = 0x00000082;
612 raster_config_1 = 0x00000000;
613 break;
614 /* 1 SE / 2 RBs */
615 case CHIP_KAVERI:
616 case CHIP_ICELAND:
617 case CHIP_CARRIZO:
618 raster_config = 0x00000002;
619 raster_config_1 = 0x00000000;
620 break;
621 /* 2 SEs / 4 RBs */
622 case CHIP_BONAIRE:
623 case CHIP_POLARIS11:
624 case CHIP_POLARIS12:
625 raster_config = 0x16000012;
626 raster_config_1 = 0x00000000;
627 break;
628 /* 2 SEs / 8 RBs */
629 case CHIP_TAHITI:
630 case CHIP_PITCAIRN:
631 raster_config = 0x2a00126a;
632 raster_config_1 = 0x00000000;
633 break;
634 /* 4 SEs / 8 RBs */
635 case CHIP_TONGA:
636 case CHIP_POLARIS10:
637 raster_config = 0x16000012;
638 raster_config_1 = 0x0000002a;
639 break;
640 /* 4 SEs / 16 RBs */
641 case CHIP_HAWAII:
642 case CHIP_FIJI:
643 case CHIP_VEGAM:
644 raster_config = 0x3a00161a;
645 raster_config_1 = 0x0000002e;
646 break;
647 default:
648 fprintf(stderr,
649 "ac: Unknown GPU, using 0 for raster_config\n");
650 raster_config = 0x00000000;
651 raster_config_1 = 0x00000000;
652 break;
653 }
654
655 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
656 * This decreases performance by up to 50% when the RB is the bottleneck.
657 */
658 if (info->family == CHIP_KAVERI && info->drm_major == 2)
659 raster_config = 0x00000000;
660
661 /* Fiji: Old kernels have incorrect tiling config. This decreases
662 * RB performance by 25%. (it disables 1 RB in the second packer)
663 */
664 if (info->family == CHIP_FIJI &&
665 info->cik_macrotile_mode_array[0] == 0x000000e8) {
666 raster_config = 0x16000012;
667 raster_config_1 = 0x0000002a;
668 }
669
670 *raster_config_p = raster_config;
671 *raster_config_1_p = raster_config_1;
672 }
673
674 void
675 ac_get_harvested_configs(struct radeon_info *info,
676 unsigned raster_config,
677 unsigned *cik_raster_config_1_p,
678 unsigned *raster_config_se)
679 {
680 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
681 unsigned num_se = MAX2(info->max_se, 1);
682 unsigned rb_mask = info->enabled_rb_mask;
683 unsigned num_rb = MIN2(info->num_render_backends, 16);
684 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
685 unsigned rb_per_se = num_rb / num_se;
686 unsigned se_mask[4];
687 unsigned se;
688
689 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
690 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
691 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
692 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
693
694 assert(num_se == 1 || num_se == 2 || num_se == 4);
695 assert(sh_per_se == 1 || sh_per_se == 2);
696 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
697
698
699 if (info->chip_class >= CIK) {
700 unsigned raster_config_1 = *cik_raster_config_1_p;
701 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
702 (!se_mask[2] && !se_mask[3]))) {
703 raster_config_1 &= C_028354_SE_PAIR_MAP;
704
705 if (!se_mask[0] && !se_mask[1]) {
706 raster_config_1 |=
707 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
708 } else {
709 raster_config_1 |=
710 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
711 }
712 *cik_raster_config_1_p = raster_config_1;
713 }
714 }
715
716 for (se = 0; se < num_se; se++) {
717 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
718 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
719 int idx = (se / 2) * 2;
720
721 raster_config_se[se] = raster_config;
722 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
723 raster_config_se[se] &= C_028350_SE_MAP;
724
725 if (!se_mask[idx]) {
726 raster_config_se[se] |=
727 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
728 } else {
729 raster_config_se[se] |=
730 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
731 }
732 }
733
734 pkr0_mask &= rb_mask;
735 pkr1_mask &= rb_mask;
736 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
737 raster_config_se[se] &= C_028350_PKR_MAP;
738
739 if (!pkr0_mask) {
740 raster_config_se[se] |=
741 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
742 } else {
743 raster_config_se[se] |=
744 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
745 }
746 }
747
748 if (rb_per_se >= 2) {
749 unsigned rb0_mask = 1 << (se * rb_per_se);
750 unsigned rb1_mask = rb0_mask << 1;
751
752 rb0_mask &= rb_mask;
753 rb1_mask &= rb_mask;
754 if (!rb0_mask || !rb1_mask) {
755 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
756
757 if (!rb0_mask) {
758 raster_config_se[se] |=
759 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
760 } else {
761 raster_config_se[se] |=
762 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
763 }
764 }
765
766 if (rb_per_se > 2) {
767 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
768 rb1_mask = rb0_mask << 1;
769 rb0_mask &= rb_mask;
770 rb1_mask &= rb_mask;
771 if (!rb0_mask || !rb1_mask) {
772 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
773
774 if (!rb0_mask) {
775 raster_config_se[se] |=
776 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
777 } else {
778 raster_config_se[se] |=
779 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
780 }
781 }
782 }
783 }
784 }
785 }