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ac: stop using PCI IDs for chip identification
[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "addrlib/src/amdgpu_asic_addr.h"
28 #include "sid.h"
29
30 #include "util/macros.h"
31 #include "util/u_math.h"
32
33 #include <stdio.h>
34
35 #include <xf86drm.h>
36 #include <amdgpu_drm.h>
37
38 #include <amdgpu.h>
39
40 #define CIK_TILE_MODE_COLOR_2D 14
41
42 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
56 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
57
58 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
59 {
60 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
61
62 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
63 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
64 return 2;
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
68 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
69 return 4;
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
76 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
77 return 8;
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
79 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
80 return 16;
81 default:
82 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
83 assert(!"this should never occur");
84 return 2;
85 }
86 }
87
88 static bool has_syncobj(int fd)
89 {
90 uint64_t value;
91 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
92 return false;
93 return value ? true : false;
94 }
95
96 bool ac_query_gpu_info(int fd, void *dev_p,
97 struct radeon_info *info,
98 struct amdgpu_gpu_info *amdinfo)
99 {
100 struct drm_amdgpu_info_device device_info = {};
101 struct amdgpu_buffer_size_alignments alignment_info = {};
102 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
103 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
104 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
105 struct amdgpu_gds_resource_info gds = {};
106 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
107 int r, i, j;
108 amdgpu_device_handle dev = dev_p;
109 drmDevicePtr devinfo;
110
111 /* Get PCI info. */
112 r = drmGetDevice2(fd, 0, &devinfo);
113 if (r) {
114 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
115 return false;
116 }
117 info->pci_domain = devinfo->businfo.pci->domain;
118 info->pci_bus = devinfo->businfo.pci->bus;
119 info->pci_dev = devinfo->businfo.pci->dev;
120 info->pci_func = devinfo->businfo.pci->func;
121 drmFreeDevice(&devinfo);
122
123 assert(info->drm_major == 3);
124 info->is_amdgpu = true;
125
126 /* Query hardware and driver information. */
127 r = amdgpu_query_gpu_info(dev, amdinfo);
128 if (r) {
129 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
130 return false;
131 }
132
133 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
134 &device_info);
135 if (r) {
136 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
137 return false;
138 }
139
140 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
141 if (r) {
142 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
143 return false;
144 }
145
146 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
147 if (r) {
148 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
149 return false;
150 }
151
152 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
153 if (r) {
154 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
155 return false;
156 }
157
158 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
159 if (r) {
160 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
161 return false;
162 }
163
164 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
165 if (r) {
166 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
167 return false;
168 }
169
170 if (info->drm_minor >= 17) {
171 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
172 if (r) {
173 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
174 return false;
175 }
176 }
177
178 if (info->drm_minor >= 17) {
179 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
180 if (r) {
181 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
182 return false;
183 }
184 }
185
186 if (info->drm_minor >= 17) {
187 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
188 if (r) {
189 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
190 return false;
191 }
192 }
193
194 if (info->drm_minor >= 27) {
195 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
196 if (r) {
197 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
198 return false;
199 }
200 }
201
202 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
203 &info->me_fw_version,
204 &info->me_fw_feature);
205 if (r) {
206 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
207 return false;
208 }
209
210 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
211 &info->pfp_fw_version,
212 &info->pfp_fw_feature);
213 if (r) {
214 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
215 return false;
216 }
217
218 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
219 &info->ce_fw_version,
220 &info->ce_fw_feature);
221 if (r) {
222 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
223 return false;
224 }
225
226 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
227 &uvd_version, &uvd_feature);
228 if (r) {
229 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
230 return false;
231 }
232
233 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
234 if (r) {
235 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
236 return false;
237 }
238
239 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
240 &vce_version, &vce_feature);
241 if (r) {
242 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
243 return false;
244 }
245
246 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
247 if (r) {
248 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
249 return false;
250 }
251
252 r = amdgpu_query_gds_info(dev, &gds);
253 if (r) {
254 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
255 return false;
256 }
257
258 if (info->drm_minor >= 9) {
259 struct drm_amdgpu_memory_info meminfo = {};
260
261 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
262 if (r) {
263 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
264 return false;
265 }
266
267 /* Note: usable_heap_size values can be random and can't be relied on. */
268 info->gart_size = meminfo.gtt.total_heap_size;
269 info->vram_size = meminfo.vram.total_heap_size;
270 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
271 } else {
272 /* This is a deprecated interface, which reports usable sizes
273 * (total minus pinned), but the pinned size computation is
274 * buggy, so the values returned from these functions can be
275 * random.
276 */
277 struct amdgpu_heap_info vram, vram_vis, gtt;
278
279 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
280 if (r) {
281 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
282 return false;
283 }
284
285 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
286 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
287 &vram_vis);
288 if (r) {
289 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
290 return false;
291 }
292
293 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
294 if (r) {
295 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
296 return false;
297 }
298
299 info->gart_size = gtt.heap_size;
300 info->vram_size = vram.heap_size;
301 info->vram_vis_size = vram_vis.heap_size;
302 }
303
304 /* Set chip identification. */
305 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
306 info->vce_harvest_config = amdinfo->vce_harvest_config;
307
308 #define identify_chip2(asic, chipname) \
309 if (ASICREV_IS(amdinfo->chip_external_rev, asic)) { \
310 info->family = CHIP_##chipname; \
311 info->name = #chipname; \
312 }
313 #define identify_chip(chipname) identify_chip2(chipname, chipname)
314
315 switch (amdinfo->family_id) {
316 case AMDGPU_FAMILY_SI:
317 identify_chip(TAHITI);
318 identify_chip(PITCAIRN);
319 identify_chip2(CAPEVERDE, VERDE);
320 identify_chip(OLAND);
321 identify_chip(HAINAN);
322 break;
323 case AMDGPU_FAMILY_CI:
324 identify_chip(BONAIRE);
325 identify_chip(HAWAII);
326 break;
327 case AMDGPU_FAMILY_KV:
328 identify_chip2(SPECTRE, KAVERI);
329 identify_chip2(SPOOKY, KAVERI);
330 identify_chip2(KALINDI, KABINI);
331 identify_chip2(GODAVARI, KABINI);
332 break;
333 case AMDGPU_FAMILY_VI:
334 identify_chip(ICELAND);
335 identify_chip(TONGA);
336 identify_chip(FIJI);
337 identify_chip(POLARIS10);
338 identify_chip(POLARIS11);
339 identify_chip(POLARIS12);
340 identify_chip(VEGAM);
341 break;
342 case AMDGPU_FAMILY_CZ:
343 identify_chip(CARRIZO);
344 identify_chip(STONEY);
345 break;
346 case AMDGPU_FAMILY_AI:
347 identify_chip(VEGA10);
348 identify_chip(VEGA12);
349 identify_chip(VEGA20);
350 identify_chip(ARCTURUS);
351 break;
352 case AMDGPU_FAMILY_RV:
353 identify_chip(RAVEN);
354 identify_chip(RAVEN2);
355 identify_chip(RENOIR);
356 break;
357 case AMDGPU_FAMILY_NV:
358 identify_chip(NAVI10);
359 identify_chip(NAVI12);
360 identify_chip(NAVI14);
361 break;
362 }
363
364 if (!info->name) {
365 fprintf(stderr, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
366 amdinfo->family_id, amdinfo->chip_external_rev);
367 return false;
368 }
369
370 if (info->family >= CHIP_NAVI10)
371 info->chip_class = GFX10;
372 else if (info->family >= CHIP_VEGA10)
373 info->chip_class = GFX9;
374 else if (info->family >= CHIP_TONGA)
375 info->chip_class = GFX8;
376 else if (info->family >= CHIP_BONAIRE)
377 info->chip_class = GFX7;
378 else if (info->family >= CHIP_TAHITI)
379 info->chip_class = GFX6;
380 else {
381 fprintf(stderr, "amdgpu: Unknown family.\n");
382 return false;
383 }
384
385 info->family_id = amdinfo->family_id;
386 info->chip_external_rev = amdinfo->chip_external_rev;
387 info->marketing_name = amdgpu_get_marketing_name(dev);
388 info->is_pro_graphics = info->marketing_name &&
389 (!strcmp(info->marketing_name, "Pro") ||
390 !strcmp(info->marketing_name, "PRO") ||
391 !strcmp(info->marketing_name, "Frontier"));
392
393 /* Set which chips have dedicated VRAM. */
394 info->has_dedicated_vram =
395 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
396
397 /* The kernel can split large buffers in VRAM but not in GTT, so large
398 * allocations can fail or cause buffer movement failures in the kernel.
399 */
400 if (info->has_dedicated_vram)
401 info->max_alloc_size = info->vram_size * 0.8;
402 else
403 info->max_alloc_size = info->gart_size * 0.7;
404
405 /* Set hardware information. */
406 info->gds_size = gds.gds_total_size;
407 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
408 /* convert the shader clock from KHz to MHz */
409 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
410 info->num_tcc_blocks = device_info.num_tcc_blocks;
411 info->max_se = amdinfo->num_shader_engines;
412 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
413 info->has_hw_decode =
414 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
415 (vcn_jpeg.available_rings != 0);
416 info->uvd_fw_version =
417 uvd.available_rings ? uvd_version : 0;
418 info->vce_fw_version =
419 vce.available_rings ? vce_version : 0;
420 info->uvd_enc_supported =
421 uvd_enc.available_rings ? true : false;
422 info->has_userptr = true;
423 info->has_syncobj = has_syncobj(fd);
424 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
425 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
426 info->has_ctx_priority = info->drm_minor >= 22;
427 info->has_local_buffers = info->drm_minor >= 20;
428 info->kernel_flushes_hdp_before_ib = true;
429 info->htile_cmask_support_1d_tiling = true;
430 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
431 info->has_bo_metadata = true;
432 info->has_gpu_reset_status_query = true;
433 info->has_eqaa_surface_allocator = true;
434 info->has_format_bc1_through_bc7 = true;
435 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
436 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
437 info->drm_minor >= 2;
438 info->has_indirect_compute_dispatch = true;
439 /* GFX6 doesn't support unaligned loads. */
440 info->has_unaligned_shader_loads = info->chip_class != GFX6;
441 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
442 * these faults are mitigated in software.
443 * Disable sparse mappings on GFX9 due to hangs.
444 */
445 info->has_sparse_vm_mappings =
446 info->chip_class >= GFX7 && info->chip_class <= GFX8 &&
447 info->drm_minor >= 13;
448 info->has_2d_tiling = true;
449 info->has_read_registers_query = true;
450 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
451
452 info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
453 info->num_render_backends = amdinfo->rb_pipes;
454 /* The value returned by the kernel driver was wrong. */
455 if (info->family == CHIP_KAVERI)
456 info->num_render_backends = 2;
457
458 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
459 if (!info->clock_crystal_freq) {
460 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
461 info->clock_crystal_freq = 1;
462 }
463 if (info->chip_class >= GFX10) {
464 info->tcc_cache_line_size = 128;
465 } else {
466 info->tcc_cache_line_size = 64;
467 }
468 info->gb_addr_config = amdinfo->gb_addr_cfg;
469 if (info->chip_class == GFX9) {
470 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
471 info->pipe_interleave_bytes =
472 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
473 } else {
474 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
475 info->pipe_interleave_bytes =
476 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
477 }
478 info->r600_has_virtual_memory = true;
479
480 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
481 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
482
483 info->has_graphics = gfx.available_rings > 0;
484 info->num_sdma_rings = util_bitcount(dma.available_rings);
485 info->num_compute_rings = util_bitcount(compute.available_rings);
486
487 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
488 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
489 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
490 */
491 info->has_clear_state = info->chip_class >= GFX7;
492
493 info->has_distributed_tess = info->chip_class >= GFX8 &&
494 info->max_se >= 2;
495
496 info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
497 info->family == CHIP_RENOIR ||
498 info->chip_class >= GFX10;
499
500 info->has_rbplus = info->family == CHIP_STONEY ||
501 info->chip_class >= GFX9;
502
503 /* Some chips have RB+ registers, but don't support RB+. Those must
504 * always disable it.
505 */
506 info->rbplus_allowed = info->has_rbplus &&
507 (info->family == CHIP_STONEY ||
508 info->family == CHIP_VEGA12 ||
509 info->family == CHIP_RAVEN ||
510 info->family == CHIP_RAVEN2 ||
511 info->family == CHIP_RENOIR);
512
513 info->has_out_of_order_rast = info->chip_class >= GFX8 &&
514 info->max_se >= 2;
515
516 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
517 info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
518 (info->chip_class >= GFX8 &&
519 info->me_fw_feature >= 41);
520
521 info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
522
523 info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 ||
524 info->family == CHIP_RAVEN;
525
526 info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 &&
527 info->chip_class <= GFX9;
528
529 info->has_msaa_sample_loc_bug = (info->family >= CHIP_POLARIS10 &&
530 info->family <= CHIP_POLARIS12) ||
531 info->family == CHIP_VEGA10 ||
532 info->family == CHIP_RAVEN;
533
534 info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 ||
535 info->family == CHIP_RAVEN;
536
537 /* Get the number of good compute units. */
538 info->num_good_compute_units = 0;
539 for (i = 0; i < info->max_se; i++)
540 for (j = 0; j < info->max_sh_per_se; j++)
541 info->num_good_compute_units +=
542 util_bitcount(amdinfo->cu_bitmap[i][j]);
543 info->num_good_cu_per_sh = info->num_good_compute_units /
544 (info->max_se * info->max_sh_per_se);
545
546 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
547 sizeof(amdinfo->gb_tile_mode));
548 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
549
550 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
551 sizeof(amdinfo->gb_macro_tile_mode));
552
553 info->pte_fragment_size = alignment_info.size_local;
554 info->gart_page_size = alignment_info.size_remote;
555
556 if (info->chip_class == GFX6)
557 info->gfx_ib_pad_with_type2 = true;
558
559 unsigned ib_align = 0;
560 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
561 ib_align = MAX2(ib_align, compute.ib_start_alignment);
562 ib_align = MAX2(ib_align, dma.ib_start_alignment);
563 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
564 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
565 ib_align = MAX2(ib_align, vce.ib_start_alignment);
566 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
567 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
568 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
569 assert(ib_align);
570 info->ib_start_alignment = ib_align;
571
572 if (info->drm_minor >= 31 &&
573 (info->family == CHIP_RAVEN ||
574 info->family == CHIP_RAVEN2 ||
575 info->family == CHIP_RENOIR)) {
576 if (info->num_render_backends == 1)
577 info->use_display_dcc_unaligned = true;
578 else
579 info->use_display_dcc_with_retile_blit = true;
580 }
581
582 info->has_gds_ordered_append = info->chip_class >= GFX7 &&
583 info->drm_minor >= 29;
584
585 if (info->chip_class >= GFX9) {
586 unsigned pc_lines = 0;
587
588 switch (info->family) {
589 case CHIP_VEGA10:
590 case CHIP_VEGA12:
591 case CHIP_VEGA20:
592 pc_lines = 2048;
593 break;
594 case CHIP_RAVEN:
595 case CHIP_RAVEN2:
596 case CHIP_RENOIR:
597 case CHIP_NAVI10:
598 case CHIP_NAVI12:
599 pc_lines = 1024;
600 break;
601 case CHIP_NAVI14:
602 pc_lines = 512;
603 break;
604 default:
605 assert(0);
606 }
607
608 if (info->chip_class >= GFX10) {
609 info->pbb_max_alloc_count = pc_lines / 3;
610 } else {
611 info->pbb_max_alloc_count =
612 MIN2(128, pc_lines / (4 * info->max_se));
613 }
614 }
615
616 if (info->chip_class >= GFX10) {
617 switch (info->family) {
618 case CHIP_NAVI10:
619 case CHIP_NAVI12:
620 info->num_sdp_interfaces = 16;
621 break;
622 case CHIP_NAVI14:
623 info->num_sdp_interfaces = 8;
624 break;
625 default:
626 assert(0);
627 }
628 }
629
630 info->max_wave64_per_simd = info->family >= CHIP_POLARIS10 &&
631 info->family <= CHIP_VEGAM ? 8 : 10;
632
633 /* The number is per SIMD. There is enough SGPRs for the maximum number
634 * of Wave32, which is double the number for Wave64.
635 */
636 if (info->chip_class >= GFX10)
637 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2;
638 else if (info->chip_class >= GFX8)
639 info->num_physical_sgprs_per_simd = 800;
640 else
641 info->num_physical_sgprs_per_simd = 512;
642
643 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
644 return true;
645 }
646
647 void ac_compute_driver_uuid(char *uuid, size_t size)
648 {
649 char amd_uuid[] = "AMD-MESA-DRV";
650
651 assert(size >= sizeof(amd_uuid));
652
653 memset(uuid, 0, size);
654 strncpy(uuid, amd_uuid, size);
655 }
656
657 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
658 {
659 uint32_t *uint_uuid = (uint32_t*)uuid;
660
661 assert(size >= sizeof(uint32_t)*4);
662
663 /**
664 * Use the device info directly instead of using a sha1. GL/VK UUIDs
665 * are 16 byte vs 20 byte for sha1, and the truncation that would be
666 * required would get rid of part of the little entropy we have.
667 * */
668 memset(uuid, 0, size);
669 uint_uuid[0] = info->pci_domain;
670 uint_uuid[1] = info->pci_bus;
671 uint_uuid[2] = info->pci_dev;
672 uint_uuid[3] = info->pci_func;
673 }
674
675 void ac_print_gpu_info(struct radeon_info *info)
676 {
677 printf("Device info:\n");
678 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
679 info->pci_domain, info->pci_bus,
680 info->pci_dev, info->pci_func);
681 printf(" pci_id = 0x%x\n", info->pci_id);
682 printf(" family = %i\n", info->family);
683 printf(" chip_class = %i\n", info->chip_class);
684 printf(" chip_external_rev = %i\n", info->chip_external_rev);
685 printf(" num_compute_rings = %u\n", info->num_compute_rings);
686 printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
687 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
688 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
689
690 printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
691 printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
692
693 printf("Memory info:\n");
694 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
695 printf(" gart_page_size = %u\n", info->gart_page_size);
696 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
697 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
698 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
699 printf(" gds_size = %u kB\n", info->gds_size / 1024);
700 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
701 printf(" max_alloc_size = %i MB\n",
702 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
703 printf(" min_alloc_size = %u\n", info->min_alloc_size);
704 printf(" address32_hi = %u\n", info->address32_hi);
705 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
706
707 printf("CP info:\n");
708 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
709 printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
710 printf(" me_fw_version = %i\n", info->me_fw_version);
711 printf(" me_fw_feature = %i\n", info->me_fw_feature);
712 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
713 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
714 printf(" ce_fw_version = %i\n", info->ce_fw_version);
715 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
716
717 printf("Multimedia info:\n");
718 printf(" has_hw_decode = %u\n", info->has_hw_decode);
719 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
720 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
721 printf(" vce_fw_version = %u\n", info->vce_fw_version);
722 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
723
724 printf("Kernel & winsys capabilities:\n");
725 printf(" drm = %i.%i.%i\n", info->drm_major,
726 info->drm_minor, info->drm_patchlevel);
727 printf(" has_userptr = %i\n", info->has_userptr);
728 printf(" has_syncobj = %u\n", info->has_syncobj);
729 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
730 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
731 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
732 printf(" has_local_buffers = %u\n", info->has_local_buffers);
733 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
734 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
735 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
736 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
737 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
738 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
739 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
740 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
741 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
742 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
743 printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
744 printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
745 printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
746 printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
747 printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
748
749 printf("Shader core info:\n");
750 printf(" max_shader_clock = %i\n", info->max_shader_clock);
751 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
752 printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh);
753 printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
754 printf(" max_se = %i\n", info->max_se);
755 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
756
757 printf("Render backend info:\n");
758 printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
759 printf(" num_render_backends = %i\n", info->num_render_backends);
760 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
761 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
762 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
763 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
764
765 printf("GB_ADDR_CONFIG:\n");
766 if (info->chip_class >= GFX9) {
767 printf(" num_pipes = %u\n",
768 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
769 printf(" pipe_interleave_size = %u\n",
770 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
771 printf(" max_compressed_frags = %u\n",
772 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
773 printf(" bank_interleave_size = %u\n",
774 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
775 printf(" num_banks = %u\n",
776 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
777 printf(" shader_engine_tile_size = %u\n",
778 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
779 printf(" num_shader_engines = %u\n",
780 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
781 printf(" num_gpus = %u (raw)\n",
782 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
783 printf(" multi_gpu_tile_size = %u (raw)\n",
784 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
785 printf(" num_rb_per_se = %u\n",
786 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
787 printf(" row_size = %u\n",
788 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
789 printf(" num_lower_pipes = %u (raw)\n",
790 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
791 printf(" se_enable = %u (raw)\n",
792 G_0098F8_SE_ENABLE(info->gb_addr_config));
793 } else {
794 printf(" num_pipes = %u\n",
795 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
796 printf(" pipe_interleave_size = %u\n",
797 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
798 printf(" bank_interleave_size = %u\n",
799 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
800 printf(" num_shader_engines = %u\n",
801 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
802 printf(" shader_engine_tile_size = %u\n",
803 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
804 printf(" num_gpus = %u (raw)\n",
805 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
806 printf(" multi_gpu_tile_size = %u (raw)\n",
807 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
808 printf(" row_size = %u\n",
809 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
810 printf(" num_lower_pipes = %u (raw)\n",
811 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
812 }
813 }
814
815 int
816 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
817 {
818 if (chip_class >= GFX9)
819 return -1;
820
821 switch (family) {
822 case CHIP_OLAND:
823 case CHIP_HAINAN:
824 case CHIP_KAVERI:
825 case CHIP_KABINI:
826 case CHIP_ICELAND:
827 case CHIP_CARRIZO:
828 case CHIP_STONEY:
829 return 16;
830 case CHIP_TAHITI:
831 case CHIP_PITCAIRN:
832 case CHIP_VERDE:
833 case CHIP_BONAIRE:
834 case CHIP_HAWAII:
835 case CHIP_TONGA:
836 case CHIP_FIJI:
837 case CHIP_POLARIS10:
838 case CHIP_POLARIS11:
839 case CHIP_POLARIS12:
840 case CHIP_VEGAM:
841 return 32;
842 default:
843 unreachable("Unknown GPU");
844 }
845 }
846
847 void
848 ac_get_raster_config(struct radeon_info *info,
849 uint32_t *raster_config_p,
850 uint32_t *raster_config_1_p,
851 uint32_t *se_tile_repeat_p)
852 {
853 unsigned raster_config, raster_config_1, se_tile_repeat;
854
855 switch (info->family) {
856 /* 1 SE / 1 RB */
857 case CHIP_HAINAN:
858 case CHIP_KABINI:
859 case CHIP_STONEY:
860 raster_config = 0x00000000;
861 raster_config_1 = 0x00000000;
862 break;
863 /* 1 SE / 4 RBs */
864 case CHIP_VERDE:
865 raster_config = 0x0000124a;
866 raster_config_1 = 0x00000000;
867 break;
868 /* 1 SE / 2 RBs (Oland is special) */
869 case CHIP_OLAND:
870 raster_config = 0x00000082;
871 raster_config_1 = 0x00000000;
872 break;
873 /* 1 SE / 2 RBs */
874 case CHIP_KAVERI:
875 case CHIP_ICELAND:
876 case CHIP_CARRIZO:
877 raster_config = 0x00000002;
878 raster_config_1 = 0x00000000;
879 break;
880 /* 2 SEs / 4 RBs */
881 case CHIP_BONAIRE:
882 case CHIP_POLARIS11:
883 case CHIP_POLARIS12:
884 raster_config = 0x16000012;
885 raster_config_1 = 0x00000000;
886 break;
887 /* 2 SEs / 8 RBs */
888 case CHIP_TAHITI:
889 case CHIP_PITCAIRN:
890 raster_config = 0x2a00126a;
891 raster_config_1 = 0x00000000;
892 break;
893 /* 4 SEs / 8 RBs */
894 case CHIP_TONGA:
895 case CHIP_POLARIS10:
896 raster_config = 0x16000012;
897 raster_config_1 = 0x0000002a;
898 break;
899 /* 4 SEs / 16 RBs */
900 case CHIP_HAWAII:
901 case CHIP_FIJI:
902 case CHIP_VEGAM:
903 raster_config = 0x3a00161a;
904 raster_config_1 = 0x0000002e;
905 break;
906 default:
907 fprintf(stderr,
908 "ac: Unknown GPU, using 0 for raster_config\n");
909 raster_config = 0x00000000;
910 raster_config_1 = 0x00000000;
911 break;
912 }
913
914 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
915 * This decreases performance by up to 50% when the RB is the bottleneck.
916 */
917 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
918 raster_config = 0x00000000;
919
920 /* Fiji: Old kernels have incorrect tiling config. This decreases
921 * RB performance by 25%. (it disables 1 RB in the second packer)
922 */
923 if (info->family == CHIP_FIJI &&
924 info->cik_macrotile_mode_array[0] == 0x000000e8) {
925 raster_config = 0x16000012;
926 raster_config_1 = 0x0000002a;
927 }
928
929 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
930 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
931
932 /* I don't know how to calculate this, though this is probably a good guess. */
933 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
934
935 *raster_config_p = raster_config;
936 *raster_config_1_p = raster_config_1;
937 if (se_tile_repeat_p)
938 *se_tile_repeat_p = se_tile_repeat;
939 }
940
941 void
942 ac_get_harvested_configs(struct radeon_info *info,
943 unsigned raster_config,
944 unsigned *cik_raster_config_1_p,
945 unsigned *raster_config_se)
946 {
947 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
948 unsigned num_se = MAX2(info->max_se, 1);
949 unsigned rb_mask = info->enabled_rb_mask;
950 unsigned num_rb = MIN2(info->num_render_backends, 16);
951 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
952 unsigned rb_per_se = num_rb / num_se;
953 unsigned se_mask[4];
954 unsigned se;
955
956 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
957 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
958 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
959 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
960
961 assert(num_se == 1 || num_se == 2 || num_se == 4);
962 assert(sh_per_se == 1 || sh_per_se == 2);
963 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
964
965
966 if (info->chip_class >= GFX7) {
967 unsigned raster_config_1 = *cik_raster_config_1_p;
968 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
969 (!se_mask[2] && !se_mask[3]))) {
970 raster_config_1 &= C_028354_SE_PAIR_MAP;
971
972 if (!se_mask[0] && !se_mask[1]) {
973 raster_config_1 |=
974 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
975 } else {
976 raster_config_1 |=
977 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
978 }
979 *cik_raster_config_1_p = raster_config_1;
980 }
981 }
982
983 for (se = 0; se < num_se; se++) {
984 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
985 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
986 int idx = (se / 2) * 2;
987
988 raster_config_se[se] = raster_config;
989 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
990 raster_config_se[se] &= C_028350_SE_MAP;
991
992 if (!se_mask[idx]) {
993 raster_config_se[se] |=
994 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
995 } else {
996 raster_config_se[se] |=
997 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
998 }
999 }
1000
1001 pkr0_mask &= rb_mask;
1002 pkr1_mask &= rb_mask;
1003 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1004 raster_config_se[se] &= C_028350_PKR_MAP;
1005
1006 if (!pkr0_mask) {
1007 raster_config_se[se] |=
1008 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
1009 } else {
1010 raster_config_se[se] |=
1011 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
1012 }
1013 }
1014
1015 if (rb_per_se >= 2) {
1016 unsigned rb0_mask = 1 << (se * rb_per_se);
1017 unsigned rb1_mask = rb0_mask << 1;
1018
1019 rb0_mask &= rb_mask;
1020 rb1_mask &= rb_mask;
1021 if (!rb0_mask || !rb1_mask) {
1022 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
1023
1024 if (!rb0_mask) {
1025 raster_config_se[se] |=
1026 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
1027 } else {
1028 raster_config_se[se] |=
1029 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
1030 }
1031 }
1032
1033 if (rb_per_se > 2) {
1034 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1035 rb1_mask = rb0_mask << 1;
1036 rb0_mask &= rb_mask;
1037 rb1_mask &= rb_mask;
1038 if (!rb0_mask || !rb1_mask) {
1039 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
1040
1041 if (!rb0_mask) {
1042 raster_config_se[se] |=
1043 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
1044 } else {
1045 raster_config_se[se] |=
1046 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
1047 }
1048 }
1049 }
1050 }
1051 }
1052 }
1053
1054 unsigned ac_get_compute_resource_limits(struct radeon_info *info,
1055 unsigned waves_per_threadgroup,
1056 unsigned max_waves_per_sh,
1057 unsigned threadgroups_per_cu)
1058 {
1059 unsigned compute_resource_limits =
1060 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
1061
1062 if (info->chip_class >= GFX7) {
1063 unsigned num_cu_per_se = info->num_good_compute_units /
1064 info->max_se;
1065
1066 /* Force even distribution on all SIMDs in CU if the workgroup
1067 * size is 64. This has shown some good improvements if # of CUs
1068 * per SE is not a multiple of 4.
1069 */
1070 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
1071 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
1072
1073 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
1074 compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
1075 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
1076 } else {
1077 /* GFX6 */
1078 if (max_waves_per_sh) {
1079 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
1080 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
1081 }
1082 }
1083 return compute_resource_limits;
1084 }