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meson: drop `intel_` prefix on imgui_core
[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "addrlib/src/amdgpu_asic_addr.h"
28 #include "sid.h"
29
30 #include "util/macros.h"
31 #include "util/u_math.h"
32
33 #include <stdio.h>
34
35 #include <xf86drm.h>
36 #include <amdgpu_drm.h>
37
38 #include <amdgpu.h>
39
40 #define CIK_TILE_MODE_COLOR_2D 14
41
42 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
56 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
57
58 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
59 {
60 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
61
62 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
63 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
64 return 2;
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
68 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
69 return 4;
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
76 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
77 return 8;
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
79 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
80 return 16;
81 default:
82 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
83 assert(!"this should never occur");
84 return 2;
85 }
86 }
87
88 static bool has_syncobj(int fd)
89 {
90 uint64_t value;
91 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
92 return false;
93 return value ? true : false;
94 }
95
96 static uint64_t fix_vram_size(uint64_t size)
97 {
98 /* The VRAM size is underreported, so we need to fix it, because
99 * it's used to compute the number of memory modules for harvesting.
100 */
101 return align64(size, 256*1024*1024);
102 }
103
104 bool ac_query_gpu_info(int fd, void *dev_p,
105 struct radeon_info *info,
106 struct amdgpu_gpu_info *amdinfo)
107 {
108 struct drm_amdgpu_info_device device_info = {};
109 struct amdgpu_buffer_size_alignments alignment_info = {};
110 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
111 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
112 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
113 struct amdgpu_gds_resource_info gds = {};
114 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
115 int r, i, j;
116 amdgpu_device_handle dev = dev_p;
117 drmDevicePtr devinfo;
118
119 /* Get PCI info. */
120 r = drmGetDevice2(fd, 0, &devinfo);
121 if (r) {
122 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
123 return false;
124 }
125 info->pci_domain = devinfo->businfo.pci->domain;
126 info->pci_bus = devinfo->businfo.pci->bus;
127 info->pci_dev = devinfo->businfo.pci->dev;
128 info->pci_func = devinfo->businfo.pci->func;
129 drmFreeDevice(&devinfo);
130
131 assert(info->drm_major == 3);
132 info->is_amdgpu = true;
133
134 /* Query hardware and driver information. */
135 r = amdgpu_query_gpu_info(dev, amdinfo);
136 if (r) {
137 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
138 return false;
139 }
140
141 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
142 &device_info);
143 if (r) {
144 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
145 return false;
146 }
147
148 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
149 if (r) {
150 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
151 return false;
152 }
153
154 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
155 if (r) {
156 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
157 return false;
158 }
159
160 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
161 if (r) {
162 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
163 return false;
164 }
165
166 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
167 if (r) {
168 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
169 return false;
170 }
171
172 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
173 if (r) {
174 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
175 return false;
176 }
177
178 if (info->drm_minor >= 17) {
179 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
180 if (r) {
181 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
182 return false;
183 }
184 }
185
186 if (info->drm_minor >= 17) {
187 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
188 if (r) {
189 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
190 return false;
191 }
192 }
193
194 if (info->drm_minor >= 17) {
195 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
196 if (r) {
197 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
198 return false;
199 }
200 }
201
202 if (info->drm_minor >= 27) {
203 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
204 if (r) {
205 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
206 return false;
207 }
208 }
209
210 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
211 &info->me_fw_version,
212 &info->me_fw_feature);
213 if (r) {
214 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
215 return false;
216 }
217
218 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
219 &info->pfp_fw_version,
220 &info->pfp_fw_feature);
221 if (r) {
222 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
223 return false;
224 }
225
226 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
227 &info->ce_fw_version,
228 &info->ce_fw_feature);
229 if (r) {
230 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
231 return false;
232 }
233
234 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
235 &uvd_version, &uvd_feature);
236 if (r) {
237 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
238 return false;
239 }
240
241 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
242 if (r) {
243 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
244 return false;
245 }
246
247 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
248 &vce_version, &vce_feature);
249 if (r) {
250 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
251 return false;
252 }
253
254 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
255 if (r) {
256 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
257 return false;
258 }
259
260 r = amdgpu_query_gds_info(dev, &gds);
261 if (r) {
262 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
263 return false;
264 }
265
266 if (info->drm_minor >= 9) {
267 struct drm_amdgpu_memory_info meminfo = {};
268
269 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
270 if (r) {
271 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
272 return false;
273 }
274
275 /* Note: usable_heap_size values can be random and can't be relied on. */
276 info->gart_size = meminfo.gtt.total_heap_size;
277 info->vram_size = fix_vram_size(meminfo.vram.total_heap_size);
278 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
279 } else {
280 /* This is a deprecated interface, which reports usable sizes
281 * (total minus pinned), but the pinned size computation is
282 * buggy, so the values returned from these functions can be
283 * random.
284 */
285 struct amdgpu_heap_info vram, vram_vis, gtt;
286
287 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
288 if (r) {
289 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
290 return false;
291 }
292
293 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
294 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
295 &vram_vis);
296 if (r) {
297 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
298 return false;
299 }
300
301 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
302 if (r) {
303 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
304 return false;
305 }
306
307 info->gart_size = gtt.heap_size;
308 info->vram_size = fix_vram_size(vram.heap_size);
309 info->vram_vis_size = vram_vis.heap_size;
310 }
311
312 /* Set chip identification. */
313 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
314 info->vce_harvest_config = amdinfo->vce_harvest_config;
315
316 #define identify_chip2(asic, chipname) \
317 if (ASICREV_IS(amdinfo->chip_external_rev, asic)) { \
318 info->family = CHIP_##chipname; \
319 info->name = #chipname; \
320 }
321 #define identify_chip(chipname) identify_chip2(chipname, chipname)
322
323 switch (amdinfo->family_id) {
324 case FAMILY_SI:
325 identify_chip(TAHITI);
326 identify_chip(PITCAIRN);
327 identify_chip2(CAPEVERDE, VERDE);
328 identify_chip(OLAND);
329 identify_chip(HAINAN);
330 break;
331 case FAMILY_CI:
332 identify_chip(BONAIRE);
333 identify_chip(HAWAII);
334 break;
335 case FAMILY_KV:
336 identify_chip2(SPECTRE, KAVERI);
337 identify_chip2(SPOOKY, KAVERI);
338 identify_chip2(KALINDI, KABINI);
339 identify_chip2(GODAVARI, KABINI);
340 break;
341 case FAMILY_VI:
342 identify_chip(ICELAND);
343 identify_chip(TONGA);
344 identify_chip(FIJI);
345 identify_chip(POLARIS10);
346 identify_chip(POLARIS11);
347 identify_chip(POLARIS12);
348 identify_chip(VEGAM);
349 break;
350 case FAMILY_CZ:
351 identify_chip(CARRIZO);
352 identify_chip(STONEY);
353 break;
354 case FAMILY_AI:
355 identify_chip(VEGA10);
356 identify_chip(VEGA12);
357 identify_chip(VEGA20);
358 identify_chip(ARCTURUS);
359 break;
360 case FAMILY_RV:
361 identify_chip(RAVEN);
362 identify_chip(RAVEN2);
363 identify_chip(RENOIR);
364 break;
365 case FAMILY_NV:
366 identify_chip(NAVI10);
367 identify_chip(NAVI12);
368 identify_chip(NAVI14);
369 break;
370 }
371
372 if (!info->name) {
373 fprintf(stderr, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
374 amdinfo->family_id, amdinfo->chip_external_rev);
375 return false;
376 }
377
378 if (info->family >= CHIP_NAVI10)
379 info->chip_class = GFX10;
380 else if (info->family >= CHIP_VEGA10)
381 info->chip_class = GFX9;
382 else if (info->family >= CHIP_TONGA)
383 info->chip_class = GFX8;
384 else if (info->family >= CHIP_BONAIRE)
385 info->chip_class = GFX7;
386 else if (info->family >= CHIP_TAHITI)
387 info->chip_class = GFX6;
388 else {
389 fprintf(stderr, "amdgpu: Unknown family.\n");
390 return false;
391 }
392
393 info->family_id = amdinfo->family_id;
394 info->chip_external_rev = amdinfo->chip_external_rev;
395 info->marketing_name = amdgpu_get_marketing_name(dev);
396 info->is_pro_graphics = info->marketing_name &&
397 (!strcmp(info->marketing_name, "Pro") ||
398 !strcmp(info->marketing_name, "PRO") ||
399 !strcmp(info->marketing_name, "Frontier"));
400
401 /* Set which chips have dedicated VRAM. */
402 info->has_dedicated_vram =
403 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
404
405 /* The kernel can split large buffers in VRAM but not in GTT, so large
406 * allocations can fail or cause buffer movement failures in the kernel.
407 */
408 if (info->has_dedicated_vram)
409 info->max_alloc_size = info->vram_size * 0.8;
410 else
411 info->max_alloc_size = info->gart_size * 0.7;
412
413 /* Set which chips have uncached device memory. */
414 info->has_l2_uncached = info->chip_class >= GFX9;
415
416 /* Set hardware information. */
417 info->gds_size = gds.gds_total_size;
418 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
419 /* convert the shader clock from KHz to MHz */
420 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
421 info->num_tcc_blocks = device_info.num_tcc_blocks;
422 info->max_se = amdinfo->num_shader_engines;
423 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
424 info->has_hw_decode =
425 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
426 (vcn_jpeg.available_rings != 0);
427 info->uvd_fw_version =
428 uvd.available_rings ? uvd_version : 0;
429 info->vce_fw_version =
430 vce.available_rings ? vce_version : 0;
431 info->uvd_enc_supported =
432 uvd_enc.available_rings ? true : false;
433 info->has_userptr = true;
434 info->has_syncobj = has_syncobj(fd);
435 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
436 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
437 info->has_ctx_priority = info->drm_minor >= 22;
438 info->has_local_buffers = info->drm_minor >= 20;
439 info->kernel_flushes_hdp_before_ib = true;
440 info->htile_cmask_support_1d_tiling = true;
441 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
442 info->has_bo_metadata = true;
443 info->has_gpu_reset_status_query = true;
444 info->has_eqaa_surface_allocator = true;
445 info->has_format_bc1_through_bc7 = true;
446 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
447 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
448 info->drm_minor >= 2;
449 info->has_indirect_compute_dispatch = true;
450 /* GFX6 doesn't support unaligned loads. */
451 info->has_unaligned_shader_loads = info->chip_class != GFX6;
452 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
453 * these faults are mitigated in software.
454 * Disable sparse mappings on GFX9 due to hangs.
455 */
456 info->has_sparse_vm_mappings =
457 info->chip_class >= GFX7 && info->chip_class <= GFX8 &&
458 info->drm_minor >= 13;
459 info->has_2d_tiling = true;
460 info->has_read_registers_query = true;
461 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
462
463 info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
464 info->num_render_backends = amdinfo->rb_pipes;
465 /* The value returned by the kernel driver was wrong. */
466 if (info->family == CHIP_KAVERI)
467 info->num_render_backends = 2;
468
469 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
470 if (!info->clock_crystal_freq) {
471 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
472 info->clock_crystal_freq = 1;
473 }
474 if (info->chip_class >= GFX10) {
475 info->tcc_cache_line_size = 128;
476
477 if (info->drm_minor >= 35) {
478 info->tcc_harvested = device_info.tcc_disabled_mask != 0;
479 } else {
480 /* This is a hack, but it's all we can do without a kernel upgrade. */
481 info->tcc_harvested =
482 (info->vram_size / info->num_tcc_blocks) != 512*1024*1024;
483 }
484 } else {
485 info->tcc_cache_line_size = 64;
486 }
487 info->gb_addr_config = amdinfo->gb_addr_cfg;
488 if (info->chip_class == GFX9) {
489 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
490 info->pipe_interleave_bytes =
491 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
492 } else {
493 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
494 info->pipe_interleave_bytes =
495 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
496 }
497 info->r600_has_virtual_memory = true;
498
499 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
500 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
501
502 info->has_graphics = gfx.available_rings > 0;
503 info->num_rings[RING_GFX] = util_bitcount(gfx.available_rings);
504 info->num_rings[RING_COMPUTE] = util_bitcount(compute.available_rings);
505 info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);
506 info->num_rings[RING_UVD] = util_bitcount(uvd.available_rings);
507 info->num_rings[RING_VCE] = util_bitcount(vce.available_rings);
508 info->num_rings[RING_UVD_ENC] = util_bitcount(uvd_enc.available_rings);
509 info->num_rings[RING_VCN_DEC] = util_bitcount(vcn_dec.available_rings);
510 info->num_rings[RING_VCN_ENC] = util_bitcount(vcn_enc.available_rings);
511 info->num_rings[RING_VCN_JPEG] = util_bitcount(vcn_jpeg.available_rings);
512
513 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
514 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
515 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
516 */
517 info->has_clear_state = info->chip_class >= GFX7;
518
519 info->has_distributed_tess = info->chip_class >= GFX8 &&
520 info->max_se >= 2;
521
522 info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
523 info->family == CHIP_RENOIR ||
524 info->chip_class >= GFX10;
525
526 info->has_rbplus = info->family == CHIP_STONEY ||
527 info->chip_class >= GFX9;
528
529 /* Some chips have RB+ registers, but don't support RB+. Those must
530 * always disable it.
531 */
532 info->rbplus_allowed = info->has_rbplus &&
533 (info->family == CHIP_STONEY ||
534 info->family == CHIP_VEGA12 ||
535 info->family == CHIP_RAVEN ||
536 info->family == CHIP_RAVEN2 ||
537 info->family == CHIP_RENOIR);
538
539 info->has_out_of_order_rast = info->chip_class >= GFX8 &&
540 info->max_se >= 2;
541
542 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
543 info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
544 (info->chip_class >= GFX8 &&
545 info->me_fw_feature >= 41);
546
547 info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
548
549 info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 ||
550 info->family == CHIP_RAVEN;
551
552 info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 &&
553 info->chip_class <= GFX9;
554
555 info->has_msaa_sample_loc_bug = (info->family >= CHIP_POLARIS10 &&
556 info->family <= CHIP_POLARIS12) ||
557 info->family == CHIP_VEGA10 ||
558 info->family == CHIP_RAVEN;
559
560 info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 ||
561 info->family == CHIP_RAVEN;
562
563 /* Get the number of good compute units. */
564 info->num_good_compute_units = 0;
565 for (i = 0; i < info->max_se; i++)
566 for (j = 0; j < info->max_sh_per_se; j++)
567 info->num_good_compute_units +=
568 util_bitcount(amdinfo->cu_bitmap[i][j]);
569 info->num_good_cu_per_sh = info->num_good_compute_units /
570 (info->max_se * info->max_sh_per_se);
571
572 /* Round down to the nearest multiple of 2, because the hw can't
573 * disable CUs. It can only disable whole WGPs (dual-CUs).
574 */
575 if (info->chip_class >= GFX10)
576 info->num_good_cu_per_sh -= info->num_good_cu_per_sh % 2;
577
578 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
579 sizeof(amdinfo->gb_tile_mode));
580 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
581
582 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
583 sizeof(amdinfo->gb_macro_tile_mode));
584
585 info->pte_fragment_size = alignment_info.size_local;
586 info->gart_page_size = alignment_info.size_remote;
587
588 if (info->chip_class == GFX6)
589 info->gfx_ib_pad_with_type2 = true;
590
591 unsigned ib_align = 0;
592 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
593 ib_align = MAX2(ib_align, compute.ib_start_alignment);
594 ib_align = MAX2(ib_align, dma.ib_start_alignment);
595 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
596 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
597 ib_align = MAX2(ib_align, vce.ib_start_alignment);
598 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
599 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
600 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
601 assert(ib_align);
602 info->ib_start_alignment = ib_align;
603
604 if (info->drm_minor >= 31 &&
605 (info->family == CHIP_RAVEN ||
606 info->family == CHIP_RAVEN2 ||
607 info->family == CHIP_RENOIR)) {
608 if (info->num_render_backends == 1)
609 info->use_display_dcc_unaligned = true;
610 else
611 info->use_display_dcc_with_retile_blit = true;
612 }
613
614 info->has_gds_ordered_append = info->chip_class >= GFX7 &&
615 info->drm_minor >= 29;
616
617 if (info->chip_class >= GFX9) {
618 unsigned pc_lines = 0;
619
620 switch (info->family) {
621 case CHIP_VEGA10:
622 case CHIP_VEGA12:
623 case CHIP_VEGA20:
624 pc_lines = 2048;
625 break;
626 case CHIP_RAVEN:
627 case CHIP_RAVEN2:
628 case CHIP_RENOIR:
629 case CHIP_NAVI10:
630 case CHIP_NAVI12:
631 pc_lines = 1024;
632 break;
633 case CHIP_NAVI14:
634 pc_lines = 512;
635 break;
636 case CHIP_ARCTURUS:
637 break;
638 default:
639 assert(0);
640 }
641
642 if (info->chip_class >= GFX10) {
643 info->pbb_max_alloc_count = pc_lines / 3;
644 } else {
645 info->pbb_max_alloc_count =
646 MIN2(128, pc_lines / (4 * info->max_se));
647 }
648 }
649
650 /* The number of SDPs is the same as the number of TCCs for now. */
651 if (info->chip_class >= GFX10)
652 info->num_sdp_interfaces = device_info.num_tcc_blocks;
653
654 info->max_wave64_per_simd = info->family >= CHIP_POLARIS10 &&
655 info->family <= CHIP_VEGAM ? 8 : 10;
656
657 /* The number is per SIMD. There is enough SGPRs for the maximum number
658 * of Wave32, which is double the number for Wave64.
659 */
660 if (info->chip_class >= GFX10)
661 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2;
662 else if (info->chip_class >= GFX8)
663 info->num_physical_sgprs_per_simd = 800;
664 else
665 info->num_physical_sgprs_per_simd = 512;
666
667 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
668 return true;
669 }
670
671 void ac_compute_driver_uuid(char *uuid, size_t size)
672 {
673 char amd_uuid[] = "AMD-MESA-DRV";
674
675 assert(size >= sizeof(amd_uuid));
676
677 memset(uuid, 0, size);
678 strncpy(uuid, amd_uuid, size);
679 }
680
681 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
682 {
683 uint32_t *uint_uuid = (uint32_t*)uuid;
684
685 assert(size >= sizeof(uint32_t)*4);
686
687 /**
688 * Use the device info directly instead of using a sha1. GL/VK UUIDs
689 * are 16 byte vs 20 byte for sha1, and the truncation that would be
690 * required would get rid of part of the little entropy we have.
691 * */
692 memset(uuid, 0, size);
693 uint_uuid[0] = info->pci_domain;
694 uint_uuid[1] = info->pci_bus;
695 uint_uuid[2] = info->pci_dev;
696 uint_uuid[3] = info->pci_func;
697 }
698
699 void ac_print_gpu_info(struct radeon_info *info)
700 {
701 printf("Device info:\n");
702 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
703 info->pci_domain, info->pci_bus,
704 info->pci_dev, info->pci_func);
705
706 printf(" name = %s\n", info->name);
707 printf(" marketing_name = %s\n", info->marketing_name);
708 printf(" is_pro_graphics = %u\n", info->is_pro_graphics);
709 printf(" pci_id = 0x%x\n", info->pci_id);
710 printf(" family = %i\n", info->family);
711 printf(" chip_class = %i\n", info->chip_class);
712 printf(" family_id = %i\n", info->family_id);
713 printf(" chip_external_rev = %i\n", info->chip_external_rev);
714 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
715
716 printf("Features:\n");
717 printf(" has_graphics = %i\n", info->has_graphics);
718 printf(" num_rings[RING_GFX] = %i\n", info->num_rings[RING_GFX]);
719 printf(" num_rings[RING_DMA] = %i\n", info->num_rings[RING_DMA]);
720 printf(" num_rings[RING_COMPUTE] = %u\n", info->num_rings[RING_COMPUTE]);
721 printf(" num_rings[RING_UVD] = %i\n", info->num_rings[RING_UVD]);
722 printf(" num_rings[RING_VCE] = %i\n", info->num_rings[RING_VCE]);
723 printf(" num_rings[RING_UVD_ENC] = %i\n", info->num_rings[RING_UVD_ENC]);
724 printf(" num_rings[RING_VCN_DEC] = %i\n", info->num_rings[RING_VCN_DEC]);
725 printf(" num_rings[RING_VCN_ENC] = %i\n", info->num_rings[RING_VCN_ENC]);
726 printf(" num_rings[RING_VCN_JPEG] = %i\n", info->num_rings[RING_VCN_JPEG]);
727 printf(" has_clear_state = %u\n", info->has_clear_state);
728 printf(" has_distributed_tess = %u\n", info->has_distributed_tess);
729 printf(" has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode);
730 printf(" has_rbplus = %u\n", info->has_rbplus);
731 printf(" rbplus_allowed = %u\n", info->rbplus_allowed);
732 printf(" has_load_ctx_reg_pkt = %u\n", info->has_load_ctx_reg_pkt);
733 printf(" has_out_of_order_rast = %u\n", info->has_out_of_order_rast);
734 printf(" cpdma_prefetch_writes_memory = %u\n", info->cpdma_prefetch_writes_memory);
735 printf(" has_gfx9_scissor_bug = %i\n", info->has_gfx9_scissor_bug);
736 printf(" has_tc_compat_zrange_bug = %i\n", info->has_tc_compat_zrange_bug);
737 printf(" has_msaa_sample_loc_bug = %i\n", info->has_msaa_sample_loc_bug);
738 printf(" has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug);
739
740 printf("Display features:\n");
741 printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
742 printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
743
744 printf("Memory info:\n");
745 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
746 printf(" gart_page_size = %u\n", info->gart_page_size);
747 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
748 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
749 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
750 printf(" gds_size = %u kB\n", info->gds_size / 1024);
751 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
752 printf(" max_alloc_size = %i MB\n",
753 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
754 printf(" min_alloc_size = %u\n", info->min_alloc_size);
755 printf(" address32_hi = %u\n", info->address32_hi);
756 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
757 printf(" num_sdp_interfaces = %u\n", info->num_sdp_interfaces);
758 printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
759 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
760 printf(" tcc_harvested = %u\n", info->tcc_harvested);
761
762 printf("CP info:\n");
763 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
764 printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
765 printf(" me_fw_version = %i\n", info->me_fw_version);
766 printf(" me_fw_feature = %i\n", info->me_fw_feature);
767 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
768 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
769 printf(" ce_fw_version = %i\n", info->ce_fw_version);
770 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
771
772 printf("Multimedia info:\n");
773 printf(" has_hw_decode = %u\n", info->has_hw_decode);
774 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
775 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
776 printf(" vce_fw_version = %u\n", info->vce_fw_version);
777 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
778
779 printf("Kernel & winsys capabilities:\n");
780 printf(" drm = %i.%i.%i\n", info->drm_major,
781 info->drm_minor, info->drm_patchlevel);
782 printf(" has_userptr = %i\n", info->has_userptr);
783 printf(" has_syncobj = %u\n", info->has_syncobj);
784 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
785 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
786 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
787 printf(" has_local_buffers = %u\n", info->has_local_buffers);
788 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
789 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
790 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
791 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
792 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
793 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
794 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
795 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
796 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
797 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
798 printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
799 printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
800 printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
801 printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
802 printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
803
804 printf("Shader core info:\n");
805 printf(" max_shader_clock = %i\n", info->max_shader_clock);
806 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
807 printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh);
808 printf(" max_se = %i\n", info->max_se);
809 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
810 printf(" max_wave64_per_simd = %i\n", info->max_wave64_per_simd);
811 printf(" num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd);
812 printf(" num_physical_wave64_vgprs_per_simd = %i\n", info->num_physical_wave64_vgprs_per_simd);
813
814 printf("Render backend info:\n");
815 printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
816 printf(" num_render_backends = %i\n", info->num_render_backends);
817 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
818 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
819 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
820 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
821 printf(" pbb_max_alloc_count = %u\n", info->pbb_max_alloc_count);
822
823 printf("GB_ADDR_CONFIG: 0x%08x\n", info->gb_addr_config);
824 if (info->chip_class >= GFX10) {
825 printf(" num_pipes = %u\n",
826 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
827 printf(" pipe_interleave_size = %u\n",
828 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
829 printf(" max_compressed_frags = %u\n",
830 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
831 } else if (info->chip_class == GFX9) {
832 printf(" num_pipes = %u\n",
833 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
834 printf(" pipe_interleave_size = %u\n",
835 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
836 printf(" max_compressed_frags = %u\n",
837 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
838 printf(" bank_interleave_size = %u\n",
839 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
840 printf(" num_banks = %u\n",
841 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
842 printf(" shader_engine_tile_size = %u\n",
843 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
844 printf(" num_shader_engines = %u\n",
845 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
846 printf(" num_gpus = %u (raw)\n",
847 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
848 printf(" multi_gpu_tile_size = %u (raw)\n",
849 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
850 printf(" num_rb_per_se = %u\n",
851 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
852 printf(" row_size = %u\n",
853 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
854 printf(" num_lower_pipes = %u (raw)\n",
855 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
856 printf(" se_enable = %u (raw)\n",
857 G_0098F8_SE_ENABLE(info->gb_addr_config));
858 } else {
859 printf(" num_pipes = %u\n",
860 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
861 printf(" pipe_interleave_size = %u\n",
862 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
863 printf(" bank_interleave_size = %u\n",
864 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
865 printf(" num_shader_engines = %u\n",
866 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
867 printf(" shader_engine_tile_size = %u\n",
868 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
869 printf(" num_gpus = %u (raw)\n",
870 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
871 printf(" multi_gpu_tile_size = %u (raw)\n",
872 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
873 printf(" row_size = %u\n",
874 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
875 printf(" num_lower_pipes = %u (raw)\n",
876 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
877 }
878 }
879
880 int
881 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
882 {
883 if (chip_class >= GFX9)
884 return -1;
885
886 switch (family) {
887 case CHIP_OLAND:
888 case CHIP_HAINAN:
889 case CHIP_KAVERI:
890 case CHIP_KABINI:
891 case CHIP_ICELAND:
892 case CHIP_CARRIZO:
893 case CHIP_STONEY:
894 return 16;
895 case CHIP_TAHITI:
896 case CHIP_PITCAIRN:
897 case CHIP_VERDE:
898 case CHIP_BONAIRE:
899 case CHIP_HAWAII:
900 case CHIP_TONGA:
901 case CHIP_FIJI:
902 case CHIP_POLARIS10:
903 case CHIP_POLARIS11:
904 case CHIP_POLARIS12:
905 case CHIP_VEGAM:
906 return 32;
907 default:
908 unreachable("Unknown GPU");
909 }
910 }
911
912 void
913 ac_get_raster_config(struct radeon_info *info,
914 uint32_t *raster_config_p,
915 uint32_t *raster_config_1_p,
916 uint32_t *se_tile_repeat_p)
917 {
918 unsigned raster_config, raster_config_1, se_tile_repeat;
919
920 switch (info->family) {
921 /* 1 SE / 1 RB */
922 case CHIP_HAINAN:
923 case CHIP_KABINI:
924 case CHIP_STONEY:
925 raster_config = 0x00000000;
926 raster_config_1 = 0x00000000;
927 break;
928 /* 1 SE / 4 RBs */
929 case CHIP_VERDE:
930 raster_config = 0x0000124a;
931 raster_config_1 = 0x00000000;
932 break;
933 /* 1 SE / 2 RBs (Oland is special) */
934 case CHIP_OLAND:
935 raster_config = 0x00000082;
936 raster_config_1 = 0x00000000;
937 break;
938 /* 1 SE / 2 RBs */
939 case CHIP_KAVERI:
940 case CHIP_ICELAND:
941 case CHIP_CARRIZO:
942 raster_config = 0x00000002;
943 raster_config_1 = 0x00000000;
944 break;
945 /* 2 SEs / 4 RBs */
946 case CHIP_BONAIRE:
947 case CHIP_POLARIS11:
948 case CHIP_POLARIS12:
949 raster_config = 0x16000012;
950 raster_config_1 = 0x00000000;
951 break;
952 /* 2 SEs / 8 RBs */
953 case CHIP_TAHITI:
954 case CHIP_PITCAIRN:
955 raster_config = 0x2a00126a;
956 raster_config_1 = 0x00000000;
957 break;
958 /* 4 SEs / 8 RBs */
959 case CHIP_TONGA:
960 case CHIP_POLARIS10:
961 raster_config = 0x16000012;
962 raster_config_1 = 0x0000002a;
963 break;
964 /* 4 SEs / 16 RBs */
965 case CHIP_HAWAII:
966 case CHIP_FIJI:
967 case CHIP_VEGAM:
968 raster_config = 0x3a00161a;
969 raster_config_1 = 0x0000002e;
970 break;
971 default:
972 fprintf(stderr,
973 "ac: Unknown GPU, using 0 for raster_config\n");
974 raster_config = 0x00000000;
975 raster_config_1 = 0x00000000;
976 break;
977 }
978
979 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
980 * This decreases performance by up to 50% when the RB is the bottleneck.
981 */
982 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
983 raster_config = 0x00000000;
984
985 /* Fiji: Old kernels have incorrect tiling config. This decreases
986 * RB performance by 25%. (it disables 1 RB in the second packer)
987 */
988 if (info->family == CHIP_FIJI &&
989 info->cik_macrotile_mode_array[0] == 0x000000e8) {
990 raster_config = 0x16000012;
991 raster_config_1 = 0x0000002a;
992 }
993
994 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
995 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
996
997 /* I don't know how to calculate this, though this is probably a good guess. */
998 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
999
1000 *raster_config_p = raster_config;
1001 *raster_config_1_p = raster_config_1;
1002 if (se_tile_repeat_p)
1003 *se_tile_repeat_p = se_tile_repeat;
1004 }
1005
1006 void
1007 ac_get_harvested_configs(struct radeon_info *info,
1008 unsigned raster_config,
1009 unsigned *cik_raster_config_1_p,
1010 unsigned *raster_config_se)
1011 {
1012 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
1013 unsigned num_se = MAX2(info->max_se, 1);
1014 unsigned rb_mask = info->enabled_rb_mask;
1015 unsigned num_rb = MIN2(info->num_render_backends, 16);
1016 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
1017 unsigned rb_per_se = num_rb / num_se;
1018 unsigned se_mask[4];
1019 unsigned se;
1020
1021 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1022 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1023 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1024 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1025
1026 assert(num_se == 1 || num_se == 2 || num_se == 4);
1027 assert(sh_per_se == 1 || sh_per_se == 2);
1028 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
1029
1030
1031 if (info->chip_class >= GFX7) {
1032 unsigned raster_config_1 = *cik_raster_config_1_p;
1033 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1034 (!se_mask[2] && !se_mask[3]))) {
1035 raster_config_1 &= C_028354_SE_PAIR_MAP;
1036
1037 if (!se_mask[0] && !se_mask[1]) {
1038 raster_config_1 |=
1039 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
1040 } else {
1041 raster_config_1 |=
1042 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
1043 }
1044 *cik_raster_config_1_p = raster_config_1;
1045 }
1046 }
1047
1048 for (se = 0; se < num_se; se++) {
1049 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1050 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1051 int idx = (se / 2) * 2;
1052
1053 raster_config_se[se] = raster_config;
1054 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1055 raster_config_se[se] &= C_028350_SE_MAP;
1056
1057 if (!se_mask[idx]) {
1058 raster_config_se[se] |=
1059 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
1060 } else {
1061 raster_config_se[se] |=
1062 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
1063 }
1064 }
1065
1066 pkr0_mask &= rb_mask;
1067 pkr1_mask &= rb_mask;
1068 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1069 raster_config_se[se] &= C_028350_PKR_MAP;
1070
1071 if (!pkr0_mask) {
1072 raster_config_se[se] |=
1073 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
1074 } else {
1075 raster_config_se[se] |=
1076 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
1077 }
1078 }
1079
1080 if (rb_per_se >= 2) {
1081 unsigned rb0_mask = 1 << (se * rb_per_se);
1082 unsigned rb1_mask = rb0_mask << 1;
1083
1084 rb0_mask &= rb_mask;
1085 rb1_mask &= rb_mask;
1086 if (!rb0_mask || !rb1_mask) {
1087 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
1088
1089 if (!rb0_mask) {
1090 raster_config_se[se] |=
1091 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
1092 } else {
1093 raster_config_se[se] |=
1094 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
1095 }
1096 }
1097
1098 if (rb_per_se > 2) {
1099 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1100 rb1_mask = rb0_mask << 1;
1101 rb0_mask &= rb_mask;
1102 rb1_mask &= rb_mask;
1103 if (!rb0_mask || !rb1_mask) {
1104 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
1105
1106 if (!rb0_mask) {
1107 raster_config_se[se] |=
1108 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
1109 } else {
1110 raster_config_se[se] |=
1111 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
1112 }
1113 }
1114 }
1115 }
1116 }
1117 }
1118
1119 unsigned ac_get_compute_resource_limits(struct radeon_info *info,
1120 unsigned waves_per_threadgroup,
1121 unsigned max_waves_per_sh,
1122 unsigned threadgroups_per_cu)
1123 {
1124 unsigned compute_resource_limits =
1125 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
1126
1127 if (info->chip_class >= GFX7) {
1128 unsigned num_cu_per_se = info->num_good_compute_units /
1129 info->max_se;
1130
1131 /* Force even distribution on all SIMDs in CU if the workgroup
1132 * size is 64. This has shown some good improvements if # of CUs
1133 * per SE is not a multiple of 4.
1134 */
1135 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
1136 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
1137
1138 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
1139 compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
1140 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
1141 } else {
1142 /* GFX6 */
1143 if (max_waves_per_sh) {
1144 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
1145 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
1146 }
1147 }
1148 return compute_resource_limits;
1149 }