src/amd/common/ac_gpu_info.c

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #include "ac_gpu_info.h"
  27 #include "sid.h"
  28 #include "gfx9d.h"
  29
  30 #include "util/u_math.h"
  31
  32 #include <stdio.h>
  33
  34 #include <xf86drm.h>
  35 #include <amdgpu_drm.h>
  36
  37 #include <amdgpu.h>
  38
  39 #define CIK_TILE_MODE_COLOR_2D                  14
  40
  41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  42 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  43 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  44 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  45 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  46 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  47 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  48 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  54 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  55 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  56
  57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  58 {
  59    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  60
  61    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  62    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  63        return 2;
  64    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  65    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  66    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  67    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  68        return 4;
  69    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  70    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  71    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  72    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  73    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  74    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  75    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  76        return 8;
  77    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  78    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  79        return 16;
  80    default:
  81        fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
  82        assert(!"this should never occur");
  83        return 2;
  84    }
  85 }
  86
  87 static bool has_syncobj(int fd)
  88 {
  89         uint64_t value;
  90         if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
  91                 return false;
  92         return value ? true : false;
  93 }
  94
  95 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
  96                        struct radeon_info *info,
  97                        struct amdgpu_gpu_info *amdinfo)
  98 {
  99         struct amdgpu_buffer_size_alignments alignment_info = {};
 100         struct amdgpu_heap_info vram, vram_vis, gtt;
 101         struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_enc = {};
 102         uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
 103         int r, i, j;
 104         drmDevicePtr devinfo;
 105
 106         /* Get PCI info. */
 107         r = drmGetDevice2(fd, 0, &devinfo);
 108         if (r) {
 109                 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
 110                 return false;
 111         }
 112         info->pci_domain = devinfo->businfo.pci->domain;
 113         info->pci_bus = devinfo->businfo.pci->bus;
 114         info->pci_dev = devinfo->businfo.pci->dev;
 115         info->pci_func = devinfo->businfo.pci->func;
 116         drmFreeDevice(&devinfo);
 117
 118         /* Query hardware and driver information. */
 119         r = amdgpu_query_gpu_info(dev, amdinfo);
 120         if (r) {
 121                 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 122                 return false;
 123         }
 124
 125         r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
 126         if (r) {
 127                 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 128                 return false;
 129         }
 130
 131         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 132         if (r) {
 133                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 134                 return false;
 135         }
 136
 137         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
 138                                 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 139                                 &vram_vis);
 140         if (r) {
 141                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
 142                 return false;
 143         }
 144
 145         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 146         if (r) {
 147                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 148                 return false;
 149         }
 150
 151         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
 152         if (r) {
 153                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 154                 return false;
 155         }
 156
 157         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
 158         if (r) {
 159                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
 160                 return false;
 161         }
 162
 163         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 164         if (r) {
 165                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 166                 return false;
 167         }
 168
 169         if (info->drm_major == 3 && info->drm_minor >= 17) {
 170                 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
 171                 if (r) {
 172                         fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
 173                         return false;
 174                 }
 175         }
 176
 177         if (info->drm_major == 3 && info->drm_minor >= 17) {
 178                 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
 179                 if (r) {
 180                         fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
 181                         return false;
 182                 }
 183         }
 184
 185         if (info->drm_major == 3 && info->drm_minor >= 17) {
 186                 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
 187                 if (r) {
 188                         fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
 189                         return false;
 190                 }
 191         }
 192
 193         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
 194                                         &info->me_fw_version,
 195                                         &info->me_fw_feature);
 196         if (r) {
 197                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
 198                 return false;
 199         }
 200
 201         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
 202                                         &info->pfp_fw_version,
 203                                         &info->pfp_fw_feature);
 204         if (r) {
 205                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
 206                 return false;
 207         }
 208
 209         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
 210                                         &info->ce_fw_version,
 211                                         &info->ce_fw_feature);
 212         if (r) {
 213                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
 214                 return false;
 215         }
 216
 217         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
 218                                         &uvd_version, &uvd_feature);
 219         if (r) {
 220                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
 221                 return false;
 222         }
 223
 224         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
 225         if (r) {
 226                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 227                 return false;
 228         }
 229
 230         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
 231                                         &vce_version, &vce_feature);
 232         if (r) {
 233                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 234                 return false;
 235         }
 236
 237         r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
 238         if (r) {
 239                 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
 240                 return false;
 241         }
 242
 243         /* Set chip identification. */
 244         info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
 245         info->vce_harvest_config = amdinfo->vce_harvest_config;
 246
 247         switch (info->pci_id) {
 248 #define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
 249 #include "pci_ids/radeonsi_pci_ids.h"
 250 #undef CHIPSET
 251
 252         default:
 253                 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 254                 return false;
 255         }
 256
 257         if (info->family >= CHIP_VEGA10)
 258                 info->chip_class = GFX9;
 259         else if (info->family >= CHIP_TONGA)
 260                 info->chip_class = VI;
 261         else if (info->family >= CHIP_BONAIRE)
 262                 info->chip_class = CIK;
 263         else if (info->family >= CHIP_TAHITI)
 264                 info->chip_class = SI;
 265         else {
 266                 fprintf(stderr, "amdgpu: Unknown family.\n");
 267                 return false;
 268         }
 269
 270         /* Set which chips have dedicated VRAM. */
 271         info->has_dedicated_vram =
 272                 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
 273
 274         /* Set hardware information. */
 275         info->gart_size = gtt.heap_size;
 276         info->vram_size = vram.heap_size;
 277         info->vram_vis_size = vram_vis.heap_size;
 278         /* The kernel can split large buffers in VRAM but not in GTT, so large
 279          * allocations can fail or cause buffer movement failures in the kernel.
 280          */
 281         info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 0.7);
 282         /* convert the shader clock from KHz to MHz */
 283         info->max_shader_clock = amdinfo->max_engine_clk / 1000;
 284         info->max_se = amdinfo->num_shader_engines;
 285         info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
 286         info->has_hw_decode =
 287                 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
 288         info->uvd_fw_version =
 289                 uvd.available_rings ? uvd_version : 0;
 290         info->vce_fw_version =
 291                 vce.available_rings ? vce_version : 0;
 292         info->uvd_enc_supported =
 293                 uvd_enc.available_rings ? true : false;
 294         info->has_userptr = true;
 295         info->has_syncobj = has_syncobj(fd);
 296         info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
 297         info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
 298         info->has_ctx_priority = info->drm_minor >= 22;
 299         info->num_render_backends = amdinfo->rb_pipes;
 300         info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 301         if (!info->clock_crystal_freq) {
 302                 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
 303                 info->clock_crystal_freq = 1;
 304         }
 305         info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 306         if (info->chip_class == GFX9) {
 307                 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
 308                 info->pipe_interleave_bytes =
 309                         256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
 310         } else {
 311                 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
 312                 info->pipe_interleave_bytes =
 313                         256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
 314         }
 315         info->has_virtual_memory = true;
 316
 317         assert(util_is_power_of_two(dma.available_rings + 1));
 318         assert(util_is_power_of_two(compute.available_rings + 1));
 319
 320         info->num_sdma_rings = util_bitcount(dma.available_rings);
 321         info->num_compute_rings = util_bitcount(compute.available_rings);
 322
 323         /* Get the number of good compute units. */
 324         info->num_good_compute_units = 0;
 325         for (i = 0; i < info->max_se; i++)
 326                 for (j = 0; j < info->max_sh_per_se; j++)
 327                         info->num_good_compute_units +=
 328                                 util_bitcount(amdinfo->cu_bitmap[i][j]);
 329
 330         memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
 331                 sizeof(amdinfo->gb_tile_mode));
 332         info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
 333
 334         memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
 335                 sizeof(amdinfo->gb_macro_tile_mode));
 336
 337         info->pte_fragment_size = alignment_info.size_local;
 338         info->gart_page_size = alignment_info.size_remote;
 339
 340         if (info->chip_class == SI)
 341                 info->gfx_ib_pad_with_type2 = TRUE;
 342
 343         return true;
 344 }
 345
 346 void ac_compute_driver_uuid(char *uuid, size_t size)
 347 {
 348         char amd_uuid[] = "AMD-MESA-DRV";
 349
 350         assert(size >= sizeof(amd_uuid));
 351
 352         memset(uuid, 0, size);
 353         strncpy(uuid, amd_uuid, size);
 354 }
 355
 356 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
 357 {
 358         uint32_t *uint_uuid = (uint32_t*)uuid;
 359
 360         assert(size >= sizeof(uint32_t)*4);
 361
 362         /**
 363          * Use the device info directly instead of using a sha1. GL/VK UUIDs
 364          * are 16 byte vs 20 byte for sha1, and the truncation that would be
 365          * required would get rid of part of the little entropy we have.
 366          * */
 367         memset(uuid, 0, size);
 368         uint_uuid[0] = info->pci_domain;
 369         uint_uuid[1] = info->pci_bus;
 370         uint_uuid[2] = info->pci_dev;
 371         uint_uuid[3] = info->pci_func;
 372 }
 373
 374 void ac_print_gpu_info(struct radeon_info *info)
 375 {
 376         printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
 377                info->pci_domain, info->pci_bus,
 378                info->pci_dev, info->pci_func);
 379         printf("pci_id = 0x%x\n", info->pci_id);
 380         printf("family = %i\n", info->family);
 381         printf("chip_class = %i\n", info->chip_class);
 382         printf("pte_fragment_size = %u\n", info->pte_fragment_size);
 383         printf("gart_page_size = %u\n", info->gart_page_size);
 384         printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
 385         printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
 386         printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
 387         printf("max_alloc_size = %i MB\n",
 388                (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
 389         printf("min_alloc_size = %u\n", info->min_alloc_size);
 390         printf("address32_hi = %u\n", info->address32_hi);
 391         printf("has_dedicated_vram = %u\n", info->has_dedicated_vram);
 392         printf("has_virtual_memory = %i\n", info->has_virtual_memory);
 393         printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
 394         printf("has_hw_decode = %u\n", info->has_hw_decode);
 395         printf("num_sdma_rings = %i\n", info->num_sdma_rings);
 396         printf("num_compute_rings = %u\n", info->num_compute_rings);
 397         printf("uvd_fw_version = %u\n", info->uvd_fw_version);
 398         printf("vce_fw_version = %u\n", info->vce_fw_version);
 399         printf("me_fw_version = %i\n", info->me_fw_version);
 400         printf("me_fw_feature = %i\n", info->me_fw_feature);
 401         printf("pfp_fw_version = %i\n", info->pfp_fw_version);
 402         printf("pfp_fw_feature = %i\n", info->pfp_fw_feature);
 403         printf("ce_fw_version = %i\n", info->ce_fw_version);
 404         printf("ce_fw_feature = %i\n", info->ce_fw_feature);
 405         printf("vce_harvest_config = %i\n", info->vce_harvest_config);
 406         printf("clock_crystal_freq = %i\n", info->clock_crystal_freq);
 407         printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
 408         printf("drm = %i.%i.%i\n", info->drm_major,
 409                info->drm_minor, info->drm_patchlevel);
 410         printf("has_userptr = %i\n", info->has_userptr);
 411         printf("has_syncobj = %u\n", info->has_syncobj);
 412         printf("has_fence_to_handle = %u\n", info->has_fence_to_handle);
 413
 414         printf("r600_max_quad_pipes = %i\n", info->r600_max_quad_pipes);
 415         printf("max_shader_clock = %i\n", info->max_shader_clock);
 416         printf("num_good_compute_units = %i\n", info->num_good_compute_units);
 417         printf("max_se = %i\n", info->max_se);
 418         printf("max_sh_per_se = %i\n", info->max_sh_per_se);
 419
 420         printf("r600_gb_backend_map = %i\n", info->r600_gb_backend_map);
 421         printf("r600_gb_backend_map_valid = %i\n", info->r600_gb_backend_map_valid);
 422         printf("r600_num_banks = %i\n", info->r600_num_banks);
 423         printf("num_render_backends = %i\n", info->num_render_backends);
 424         printf("num_tile_pipes = %i\n", info->num_tile_pipes);
 425         printf("pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
 426         printf("enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
 427         printf("max_alignment = %u\n", (unsigned)info->max_alignment);
 428 }