2 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
26 #include "ac_gpu_info.h"
30 #include "util/u_math.h"
35 #include <amdgpu_drm.h>
39 #define CIK_TILE_MODE_COLOR_2D 14
41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
42 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info
*info
)
59 unsigned mode2d
= info
->gb_tile_mode
[CIK_TILE_MODE_COLOR_2D
];
61 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d
)) {
62 case CIK__PIPE_CONFIG__ADDR_SURF_P2
:
64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16
:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16
:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32
:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32
:
69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16
:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16
:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16
:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16
:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16
:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32
:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32
:
77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16
:
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16
:
81 fprintf(stderr
, "Invalid CIK pipe configuration, assuming P2\n");
82 assert(!"this should never occur");
87 static bool has_syncobj(int fd
)
90 if (drmGetCap(fd
, DRM_CAP_SYNCOBJ
, &value
))
92 return value
? true : false;
95 bool ac_query_gpu_info(int fd
, amdgpu_device_handle dev
,
96 struct radeon_info
*info
,
97 struct amdgpu_gpu_info
*amdinfo
)
99 struct drm_amdgpu_info_device device_info
= {};
100 struct amdgpu_buffer_size_alignments alignment_info
= {};
101 struct drm_amdgpu_info_hw_ip dma
= {}, compute
= {}, uvd
= {};
102 struct drm_amdgpu_info_hw_ip uvd_enc
= {}, vce
= {}, vcn_dec
= {};
103 struct drm_amdgpu_info_hw_ip vcn_enc
= {}, gfx
= {};
104 struct amdgpu_gds_resource_info gds
= {};
105 uint32_t vce_version
= 0, vce_feature
= 0, uvd_version
= 0, uvd_feature
= 0;
107 drmDevicePtr devinfo
;
110 r
= drmGetDevice2(fd
, 0, &devinfo
);
112 fprintf(stderr
, "amdgpu: drmGetDevice2 failed.\n");
115 info
->pci_domain
= devinfo
->businfo
.pci
->domain
;
116 info
->pci_bus
= devinfo
->businfo
.pci
->bus
;
117 info
->pci_dev
= devinfo
->businfo
.pci
->dev
;
118 info
->pci_func
= devinfo
->businfo
.pci
->func
;
119 drmFreeDevice(&devinfo
);
121 /* Query hardware and driver information. */
122 r
= amdgpu_query_gpu_info(dev
, amdinfo
);
124 fprintf(stderr
, "amdgpu: amdgpu_query_gpu_info failed.\n");
128 r
= amdgpu_query_info(dev
, AMDGPU_INFO_DEV_INFO
, sizeof(device_info
),
131 fprintf(stderr
, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
135 r
= amdgpu_query_buffer_size_alignment(dev
, &alignment_info
);
137 fprintf(stderr
, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
141 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_DMA
, 0, &dma
);
143 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
147 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_GFX
, 0, &gfx
);
149 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
153 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_COMPUTE
, 0, &compute
);
155 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
159 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_UVD
, 0, &uvd
);
161 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
165 if (info
->drm_major
== 3 && info
->drm_minor
>= 17) {
166 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_UVD_ENC
, 0, &uvd_enc
);
168 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
173 if (info
->drm_major
== 3 && info
->drm_minor
>= 17) {
174 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCN_DEC
, 0, &vcn_dec
);
176 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
181 if (info
->drm_major
== 3 && info
->drm_minor
>= 17) {
182 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCN_ENC
, 0, &vcn_enc
);
184 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
189 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_ME
, 0, 0,
190 &info
->me_fw_version
,
191 &info
->me_fw_feature
);
193 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
197 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_PFP
, 0, 0,
198 &info
->pfp_fw_version
,
199 &info
->pfp_fw_feature
);
201 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
205 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_CE
, 0, 0,
206 &info
->ce_fw_version
,
207 &info
->ce_fw_feature
);
209 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
213 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_UVD
, 0, 0,
214 &uvd_version
, &uvd_feature
);
216 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
220 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCE
, 0, &vce
);
222 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
226 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_VCE
, 0, 0,
227 &vce_version
, &vce_feature
);
229 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
233 r
= amdgpu_query_sw_info(dev
, amdgpu_sw_info_address32_hi
, &info
->address32_hi
);
235 fprintf(stderr
, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
239 r
= amdgpu_query_gds_info(dev
, &gds
);
241 fprintf(stderr
, "amdgpu: amdgpu_query_gds_info failed.\n");
245 if (info
->drm_minor
>= 9) {
246 struct drm_amdgpu_memory_info meminfo
= {};
248 r
= amdgpu_query_info(dev
, AMDGPU_INFO_MEMORY
, sizeof(meminfo
), &meminfo
);
250 fprintf(stderr
, "amdgpu: amdgpu_query_info(memory) failed.\n");
254 /* Note: usable_heap_size values can be random and can't be relied on. */
255 info
->gart_size
= meminfo
.gtt
.total_heap_size
;
256 info
->vram_size
= meminfo
.vram
.total_heap_size
;
257 info
->vram_vis_size
= meminfo
.cpu_accessible_vram
.total_heap_size
;
259 info
->max_alloc_size
= MAX2(meminfo
.vram
.max_allocation
,
260 meminfo
.gtt
.max_allocation
);
262 /* This is a deprecated interface, which reports usable sizes
263 * (total minus pinned), but the pinned size computation is
264 * buggy, so the values returned from these functions can be
267 struct amdgpu_heap_info vram
, vram_vis
, gtt
;
269 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &vram
);
271 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
275 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_VRAM
,
276 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
279 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
283 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, >t
);
285 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
289 info
->gart_size
= gtt
.heap_size
;
290 info
->vram_size
= vram
.heap_size
;
291 info
->vram_vis_size
= vram_vis
.heap_size
;
293 /* The kernel can split large buffers in VRAM but not in GTT, so large
294 * allocations can fail or cause buffer movement failures in the kernel.
296 info
->max_alloc_size
= MAX2(info
->vram_size
* 0.9, info
->gart_size
* 0.7);
299 /* Set chip identification. */
300 info
->pci_id
= amdinfo
->asic_id
; /* TODO: is this correct? */
301 info
->vce_harvest_config
= amdinfo
->vce_harvest_config
;
303 switch (info
->pci_id
) {
304 #define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
305 #include "pci_ids/radeonsi_pci_ids.h"
309 fprintf(stderr
, "amdgpu: Invalid PCI ID.\n");
313 if (info
->family
>= CHIP_VEGA10
)
314 info
->chip_class
= GFX9
;
315 else if (info
->family
>= CHIP_TONGA
)
316 info
->chip_class
= VI
;
317 else if (info
->family
>= CHIP_BONAIRE
)
318 info
->chip_class
= CIK
;
319 else if (info
->family
>= CHIP_TAHITI
)
320 info
->chip_class
= SI
;
322 fprintf(stderr
, "amdgpu: Unknown family.\n");
326 /* Set which chips have dedicated VRAM. */
327 info
->has_dedicated_vram
=
328 !(amdinfo
->ids_flags
& AMDGPU_IDS_FLAGS_FUSION
);
330 /* Set hardware information. */
331 info
->gds_size
= gds
.gds_total_size
;
332 info
->gds_gfx_partition_size
= gds
.gds_gfx_partition_size
;
333 /* convert the shader clock from KHz to MHz */
334 info
->max_shader_clock
= amdinfo
->max_engine_clk
/ 1000;
335 info
->num_tcc_blocks
= device_info
.num_tcc_blocks
;
336 info
->max_se
= amdinfo
->num_shader_engines
;
337 info
->max_sh_per_se
= amdinfo
->num_shader_arrays_per_engine
;
338 info
->has_hw_decode
=
339 (uvd
.available_rings
!= 0) || (vcn_dec
.available_rings
!= 0);
340 info
->uvd_fw_version
=
341 uvd
.available_rings
? uvd_version
: 0;
342 info
->vce_fw_version
=
343 vce
.available_rings
? vce_version
: 0;
344 info
->uvd_enc_supported
=
345 uvd_enc
.available_rings
? true : false;
346 info
->has_userptr
= true;
347 info
->has_syncobj
= has_syncobj(fd
);
348 info
->has_syncobj_wait_for_submit
= info
->has_syncobj
&& info
->drm_minor
>= 20;
349 info
->has_fence_to_handle
= info
->has_syncobj
&& info
->drm_minor
>= 21;
350 info
->has_ctx_priority
= info
->drm_minor
>= 22;
351 /* TODO: Enable this once the kernel handles it efficiently. */
352 info
->has_local_buffers
= info
->drm_minor
>= 20 &&
353 !info
->has_dedicated_vram
;
354 info
->kernel_flushes_hdp_before_ib
= true;
355 info
->htile_cmask_support_1d_tiling
= true;
356 info
->si_TA_CS_BC_BASE_ADDR_allowed
= true;
357 info
->has_bo_metadata
= true;
358 info
->has_gpu_reset_status_query
= true;
359 info
->has_gpu_reset_counter_query
= false;
360 info
->has_eqaa_surface_allocator
= true;
361 info
->has_format_bc1_through_bc7
= true;
362 /* DRM 3.1.0 doesn't flush TC for VI correctly. */
363 info
->kernel_flushes_tc_l2_after_ib
= info
->chip_class
!= VI
||
364 info
->drm_minor
>= 2;
365 info
->has_indirect_compute_dispatch
= true;
366 /* SI doesn't support unaligned loads. */
367 info
->has_unaligned_shader_loads
= info
->chip_class
!= SI
;
368 /* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once
369 * these faults are mitigated in software.
370 * Disable sparse mappings on GFX9 due to hangs.
372 info
->has_sparse_vm_mappings
=
373 info
->chip_class
>= CIK
&& info
->chip_class
<= VI
&&
374 info
->drm_minor
>= 13;
375 info
->has_2d_tiling
= true;
376 info
->has_read_registers_query
= true;
378 info
->num_render_backends
= amdinfo
->rb_pipes
;
379 /* The value returned by the kernel driver was wrong. */
380 if (info
->family
== CHIP_KAVERI
)
381 info
->num_render_backends
= 2;
383 info
->clock_crystal_freq
= amdinfo
->gpu_counter_freq
;
384 if (!info
->clock_crystal_freq
) {
385 fprintf(stderr
, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
386 info
->clock_crystal_freq
= 1;
388 info
->tcc_cache_line_size
= 64; /* TC L2 line size on GCN */
389 info
->gb_addr_config
= amdinfo
->gb_addr_cfg
;
390 if (info
->chip_class
== GFX9
) {
391 info
->num_tile_pipes
= 1 << G_0098F8_NUM_PIPES(amdinfo
->gb_addr_cfg
);
392 info
->pipe_interleave_bytes
=
393 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo
->gb_addr_cfg
);
395 info
->num_tile_pipes
= cik_get_num_tile_pipes(amdinfo
);
396 info
->pipe_interleave_bytes
=
397 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo
->gb_addr_cfg
);
399 info
->r600_has_virtual_memory
= true;
401 assert(util_is_power_of_two_or_zero(dma
.available_rings
+ 1));
402 assert(util_is_power_of_two_or_zero(compute
.available_rings
+ 1));
404 info
->num_sdma_rings
= util_bitcount(dma
.available_rings
);
405 info
->num_compute_rings
= util_bitcount(compute
.available_rings
);
407 /* Get the number of good compute units. */
408 info
->num_good_compute_units
= 0;
409 for (i
= 0; i
< info
->max_se
; i
++)
410 for (j
= 0; j
< info
->max_sh_per_se
; j
++)
411 info
->num_good_compute_units
+=
412 util_bitcount(amdinfo
->cu_bitmap
[i
][j
]);
414 memcpy(info
->si_tile_mode_array
, amdinfo
->gb_tile_mode
,
415 sizeof(amdinfo
->gb_tile_mode
));
416 info
->enabled_rb_mask
= amdinfo
->enabled_rb_pipes_mask
;
418 memcpy(info
->cik_macrotile_mode_array
, amdinfo
->gb_macro_tile_mode
,
419 sizeof(amdinfo
->gb_macro_tile_mode
));
421 info
->pte_fragment_size
= alignment_info
.size_local
;
422 info
->gart_page_size
= alignment_info
.size_remote
;
424 if (info
->chip_class
== SI
)
425 info
->gfx_ib_pad_with_type2
= TRUE
;
427 unsigned ib_align
= 0;
428 ib_align
= MAX2(ib_align
, gfx
.ib_start_alignment
);
429 ib_align
= MAX2(ib_align
, compute
.ib_start_alignment
);
430 ib_align
= MAX2(ib_align
, dma
.ib_start_alignment
);
431 ib_align
= MAX2(ib_align
, uvd
.ib_start_alignment
);
432 ib_align
= MAX2(ib_align
, uvd_enc
.ib_start_alignment
);
433 ib_align
= MAX2(ib_align
, vce
.ib_start_alignment
);
434 ib_align
= MAX2(ib_align
, vcn_dec
.ib_start_alignment
);
435 ib_align
= MAX2(ib_align
, vcn_enc
.ib_start_alignment
);
437 info
->ib_start_alignment
= ib_align
;
442 void ac_compute_driver_uuid(char *uuid
, size_t size
)
444 char amd_uuid
[] = "AMD-MESA-DRV";
446 assert(size
>= sizeof(amd_uuid
));
448 memset(uuid
, 0, size
);
449 strncpy(uuid
, amd_uuid
, size
);
452 void ac_compute_device_uuid(struct radeon_info
*info
, char *uuid
, size_t size
)
454 uint32_t *uint_uuid
= (uint32_t*)uuid
;
456 assert(size
>= sizeof(uint32_t)*4);
459 * Use the device info directly instead of using a sha1. GL/VK UUIDs
460 * are 16 byte vs 20 byte for sha1, and the truncation that would be
461 * required would get rid of part of the little entropy we have.
463 memset(uuid
, 0, size
);
464 uint_uuid
[0] = info
->pci_domain
;
465 uint_uuid
[1] = info
->pci_bus
;
466 uint_uuid
[2] = info
->pci_dev
;
467 uint_uuid
[3] = info
->pci_func
;
470 void ac_print_gpu_info(struct radeon_info
*info
)
472 printf("Device info:\n");
473 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
474 info
->pci_domain
, info
->pci_bus
,
475 info
->pci_dev
, info
->pci_func
);
476 printf(" pci_id = 0x%x\n", info
->pci_id
);
477 printf(" family = %i\n", info
->family
);
478 printf(" chip_class = %i\n", info
->chip_class
);
479 printf(" num_compute_rings = %u\n", info
->num_compute_rings
);
480 printf(" num_sdma_rings = %i\n", info
->num_sdma_rings
);
481 printf(" clock_crystal_freq = %i\n", info
->clock_crystal_freq
);
482 printf(" tcc_cache_line_size = %u\n", info
->tcc_cache_line_size
);
484 printf("Memory info:\n");
485 printf(" pte_fragment_size = %u\n", info
->pte_fragment_size
);
486 printf(" gart_page_size = %u\n", info
->gart_page_size
);
487 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info
->gart_size
, 1024*1024));
488 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info
->vram_size
, 1024*1024));
489 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info
->vram_vis_size
, 1024*1024));
490 printf(" gds_size = %u kB\n", info
->gds_size
/ 1024);
491 printf(" gds_gfx_partition_size = %u kB\n", info
->gds_gfx_partition_size
/ 1024);
492 printf(" max_alloc_size = %i MB\n",
493 (int)DIV_ROUND_UP(info
->max_alloc_size
, 1024*1024));
494 printf(" min_alloc_size = %u\n", info
->min_alloc_size
);
495 printf(" address32_hi = %u\n", info
->address32_hi
);
496 printf(" has_dedicated_vram = %u\n", info
->has_dedicated_vram
);
498 printf("CP info:\n");
499 printf(" gfx_ib_pad_with_type2 = %i\n", info
->gfx_ib_pad_with_type2
);
500 printf(" ib_start_alignment = %u\n", info
->ib_start_alignment
);
501 printf(" me_fw_version = %i\n", info
->me_fw_version
);
502 printf(" me_fw_feature = %i\n", info
->me_fw_feature
);
503 printf(" pfp_fw_version = %i\n", info
->pfp_fw_version
);
504 printf(" pfp_fw_feature = %i\n", info
->pfp_fw_feature
);
505 printf(" ce_fw_version = %i\n", info
->ce_fw_version
);
506 printf(" ce_fw_feature = %i\n", info
->ce_fw_feature
);
508 printf("Multimedia info:\n");
509 printf(" has_hw_decode = %u\n", info
->has_hw_decode
);
510 printf(" uvd_enc_supported = %u\n", info
->uvd_enc_supported
);
511 printf(" uvd_fw_version = %u\n", info
->uvd_fw_version
);
512 printf(" vce_fw_version = %u\n", info
->vce_fw_version
);
513 printf(" vce_harvest_config = %i\n", info
->vce_harvest_config
);
515 printf("Kernel & winsys capabilities:\n");
516 printf(" drm = %i.%i.%i\n", info
->drm_major
,
517 info
->drm_minor
, info
->drm_patchlevel
);
518 printf(" has_userptr = %i\n", info
->has_userptr
);
519 printf(" has_syncobj = %u\n", info
->has_syncobj
);
520 printf(" has_syncobj_wait_for_submit = %u\n", info
->has_syncobj_wait_for_submit
);
521 printf(" has_fence_to_handle = %u\n", info
->has_fence_to_handle
);
522 printf(" has_ctx_priority = %u\n", info
->has_ctx_priority
);
523 printf(" has_local_buffers = %u\n", info
->has_local_buffers
);
524 printf(" kernel_flushes_hdp_before_ib = %u\n", info
->kernel_flushes_hdp_before_ib
);
525 printf(" htile_cmask_support_1d_tiling = %u\n", info
->htile_cmask_support_1d_tiling
);
526 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info
->si_TA_CS_BC_BASE_ADDR_allowed
);
527 printf(" has_bo_metadata = %u\n", info
->has_bo_metadata
);
528 printf(" has_gpu_reset_status_query = %u\n", info
->has_gpu_reset_status_query
);
529 printf(" has_gpu_reset_counter_query = %u\n", info
->has_gpu_reset_counter_query
);
530 printf(" has_eqaa_surface_allocator = %u\n", info
->has_eqaa_surface_allocator
);
531 printf(" has_format_bc1_through_bc7 = %u\n", info
->has_format_bc1_through_bc7
);
532 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info
->kernel_flushes_tc_l2_after_ib
);
533 printf(" has_indirect_compute_dispatch = %u\n", info
->has_indirect_compute_dispatch
);
534 printf(" has_unaligned_shader_loads = %u\n", info
->has_unaligned_shader_loads
);
535 printf(" has_sparse_vm_mappings = %u\n", info
->has_sparse_vm_mappings
);
536 printf(" has_2d_tiling = %u\n", info
->has_2d_tiling
);
537 printf(" has_read_registers_query = %u\n", info
->has_read_registers_query
);
539 printf("Shader core info:\n");
540 printf(" max_shader_clock = %i\n", info
->max_shader_clock
);
541 printf(" num_good_compute_units = %i\n", info
->num_good_compute_units
);
542 printf(" num_tcc_blocks = %i\n", info
->num_tcc_blocks
);
543 printf(" max_se = %i\n", info
->max_se
);
544 printf(" max_sh_per_se = %i\n", info
->max_sh_per_se
);
546 printf("Render backend info:\n");
547 printf(" num_render_backends = %i\n", info
->num_render_backends
);
548 printf(" num_tile_pipes = %i\n", info
->num_tile_pipes
);
549 printf(" pipe_interleave_bytes = %i\n", info
->pipe_interleave_bytes
);
550 printf(" enabled_rb_mask = 0x%x\n", info
->enabled_rb_mask
);
551 printf(" max_alignment = %u\n", (unsigned)info
->max_alignment
);
553 printf("GB_ADDR_CONFIG:\n");
554 if (info
->chip_class
>= GFX9
) {
555 printf(" num_pipes = %u\n",
556 1 << G_0098F8_NUM_PIPES(info
->gb_addr_config
));
557 printf(" pipe_interleave_size = %u\n",
558 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info
->gb_addr_config
));
559 printf(" max_compressed_frags = %u\n",
560 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info
->gb_addr_config
));
561 printf(" bank_interleave_size = %u\n",
562 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info
->gb_addr_config
));
563 printf(" num_banks = %u\n",
564 1 << G_0098F8_NUM_BANKS(info
->gb_addr_config
));
565 printf(" shader_engine_tile_size = %u\n",
566 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info
->gb_addr_config
));
567 printf(" num_shader_engines = %u\n",
568 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info
->gb_addr_config
));
569 printf(" num_gpus = %u (raw)\n",
570 G_0098F8_NUM_GPUS_GFX9(info
->gb_addr_config
));
571 printf(" multi_gpu_tile_size = %u (raw)\n",
572 G_0098F8_MULTI_GPU_TILE_SIZE(info
->gb_addr_config
));
573 printf(" num_rb_per_se = %u\n",
574 1 << G_0098F8_NUM_RB_PER_SE(info
->gb_addr_config
));
575 printf(" row_size = %u\n",
576 1024 << G_0098F8_ROW_SIZE(info
->gb_addr_config
));
577 printf(" num_lower_pipes = %u (raw)\n",
578 G_0098F8_NUM_LOWER_PIPES(info
->gb_addr_config
));
579 printf(" se_enable = %u (raw)\n",
580 G_0098F8_SE_ENABLE(info
->gb_addr_config
));
582 printf(" num_pipes = %u\n",
583 1 << G_0098F8_NUM_PIPES(info
->gb_addr_config
));
584 printf(" pipe_interleave_size = %u\n",
585 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info
->gb_addr_config
));
586 printf(" bank_interleave_size = %u\n",
587 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info
->gb_addr_config
));
588 printf(" num_shader_engines = %u\n",
589 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info
->gb_addr_config
));
590 printf(" shader_engine_tile_size = %u\n",
591 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info
->gb_addr_config
));
592 printf(" num_gpus = %u (raw)\n",
593 G_0098F8_NUM_GPUS_GFX6(info
->gb_addr_config
));
594 printf(" multi_gpu_tile_size = %u (raw)\n",
595 G_0098F8_MULTI_GPU_TILE_SIZE(info
->gb_addr_config
));
596 printf(" row_size = %u\n",
597 1024 << G_0098F8_ROW_SIZE(info
->gb_addr_config
));
598 printf(" num_lower_pipes = %u (raw)\n",
599 G_0098F8_NUM_LOWER_PIPES(info
->gb_addr_config
));
604 ac_get_gs_table_depth(enum chip_class chip_class
, enum radeon_family family
)
606 if (chip_class
>= GFX9
)
632 unreachable("Unknown GPU");
637 ac_get_raster_config(struct radeon_info
*info
,
638 uint32_t *raster_config_p
,
639 uint32_t *raster_config_1_p
)
641 unsigned raster_config
, raster_config_1
;
643 switch (info
->family
) {
649 raster_config
= 0x00000000;
650 raster_config_1
= 0x00000000;
654 raster_config
= 0x0000124a;
655 raster_config_1
= 0x00000000;
657 /* 1 SE / 2 RBs (Oland is special) */
659 raster_config
= 0x00000082;
660 raster_config_1
= 0x00000000;
666 raster_config
= 0x00000002;
667 raster_config_1
= 0x00000000;
673 raster_config
= 0x16000012;
674 raster_config_1
= 0x00000000;
679 raster_config
= 0x2a00126a;
680 raster_config_1
= 0x00000000;
685 raster_config
= 0x16000012;
686 raster_config_1
= 0x0000002a;
692 raster_config
= 0x3a00161a;
693 raster_config_1
= 0x0000002e;
697 "ac: Unknown GPU, using 0 for raster_config\n");
698 raster_config
= 0x00000000;
699 raster_config_1
= 0x00000000;
703 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
704 * This decreases performance by up to 50% when the RB is the bottleneck.
706 if (info
->family
== CHIP_KAVERI
&& info
->drm_major
== 2)
707 raster_config
= 0x00000000;
709 /* Fiji: Old kernels have incorrect tiling config. This decreases
710 * RB performance by 25%. (it disables 1 RB in the second packer)
712 if (info
->family
== CHIP_FIJI
&&
713 info
->cik_macrotile_mode_array
[0] == 0x000000e8) {
714 raster_config
= 0x16000012;
715 raster_config_1
= 0x0000002a;
718 *raster_config_p
= raster_config
;
719 *raster_config_1_p
= raster_config_1
;
723 ac_get_harvested_configs(struct radeon_info
*info
,
724 unsigned raster_config
,
725 unsigned *cik_raster_config_1_p
,
726 unsigned *raster_config_se
)
728 unsigned sh_per_se
= MAX2(info
->max_sh_per_se
, 1);
729 unsigned num_se
= MAX2(info
->max_se
, 1);
730 unsigned rb_mask
= info
->enabled_rb_mask
;
731 unsigned num_rb
= MIN2(info
->num_render_backends
, 16);
732 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
733 unsigned rb_per_se
= num_rb
/ num_se
;
737 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
738 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
739 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
740 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
742 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
743 assert(sh_per_se
== 1 || sh_per_se
== 2);
744 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
747 if (info
->chip_class
>= CIK
) {
748 unsigned raster_config_1
= *cik_raster_config_1_p
;
749 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
750 (!se_mask
[2] && !se_mask
[3]))) {
751 raster_config_1
&= C_028354_SE_PAIR_MAP
;
753 if (!se_mask
[0] && !se_mask
[1]) {
755 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
758 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
760 *cik_raster_config_1_p
= raster_config_1
;
764 for (se
= 0; se
< num_se
; se
++) {
765 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
766 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
767 int idx
= (se
/ 2) * 2;
769 raster_config_se
[se
] = raster_config
;
770 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
771 raster_config_se
[se
] &= C_028350_SE_MAP
;
774 raster_config_se
[se
] |=
775 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
777 raster_config_se
[se
] |=
778 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
782 pkr0_mask
&= rb_mask
;
783 pkr1_mask
&= rb_mask
;
784 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
785 raster_config_se
[se
] &= C_028350_PKR_MAP
;
788 raster_config_se
[se
] |=
789 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
791 raster_config_se
[se
] |=
792 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
796 if (rb_per_se
>= 2) {
797 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
798 unsigned rb1_mask
= rb0_mask
<< 1;
802 if (!rb0_mask
|| !rb1_mask
) {
803 raster_config_se
[se
] &= C_028350_RB_MAP_PKR0
;
806 raster_config_se
[se
] |=
807 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
809 raster_config_se
[se
] |=
810 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
815 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
816 rb1_mask
= rb0_mask
<< 1;
819 if (!rb0_mask
|| !rb1_mask
) {
820 raster_config_se
[se
] &= C_028350_RB_MAP_PKR1
;
823 raster_config_se
[se
] |=
824 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
826 raster_config_se
[se
] |=
827 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);