2 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
26 #include "ac_gpu_info.h"
29 #include "util/macros.h"
30 #include "util/u_math.h"
35 #include <amdgpu_drm.h>
39 #define CIK_TILE_MODE_COLOR_2D 14
41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
42 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info
*info
)
59 unsigned mode2d
= info
->gb_tile_mode
[CIK_TILE_MODE_COLOR_2D
];
61 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d
)) {
62 case CIK__PIPE_CONFIG__ADDR_SURF_P2
:
64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16
:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16
:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32
:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32
:
69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16
:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16
:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16
:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16
:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16
:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32
:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32
:
77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16
:
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16
:
81 fprintf(stderr
, "Invalid GFX7 pipe configuration, assuming P2\n");
82 assert(!"this should never occur");
87 static bool has_syncobj(int fd
)
90 if (drmGetCap(fd
, DRM_CAP_SYNCOBJ
, &value
))
92 return value
? true : false;
95 bool ac_query_gpu_info(int fd
, void *dev_p
,
96 struct radeon_info
*info
,
97 struct amdgpu_gpu_info
*amdinfo
)
99 struct drm_amdgpu_info_device device_info
= {};
100 struct amdgpu_buffer_size_alignments alignment_info
= {};
101 struct drm_amdgpu_info_hw_ip dma
= {}, compute
= {}, uvd
= {};
102 struct drm_amdgpu_info_hw_ip uvd_enc
= {}, vce
= {}, vcn_dec
= {}, vcn_jpeg
= {};
103 struct drm_amdgpu_info_hw_ip vcn_enc
= {}, gfx
= {};
104 struct amdgpu_gds_resource_info gds
= {};
105 uint32_t vce_version
= 0, vce_feature
= 0, uvd_version
= 0, uvd_feature
= 0;
107 amdgpu_device_handle dev
= dev_p
;
108 drmDevicePtr devinfo
;
111 r
= drmGetDevice2(fd
, 0, &devinfo
);
113 fprintf(stderr
, "amdgpu: drmGetDevice2 failed.\n");
116 info
->pci_domain
= devinfo
->businfo
.pci
->domain
;
117 info
->pci_bus
= devinfo
->businfo
.pci
->bus
;
118 info
->pci_dev
= devinfo
->businfo
.pci
->dev
;
119 info
->pci_func
= devinfo
->businfo
.pci
->func
;
120 drmFreeDevice(&devinfo
);
122 assert(info
->drm_major
== 3);
123 info
->is_amdgpu
= true;
125 /* Query hardware and driver information. */
126 r
= amdgpu_query_gpu_info(dev
, amdinfo
);
128 fprintf(stderr
, "amdgpu: amdgpu_query_gpu_info failed.\n");
132 r
= amdgpu_query_info(dev
, AMDGPU_INFO_DEV_INFO
, sizeof(device_info
),
135 fprintf(stderr
, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
139 r
= amdgpu_query_buffer_size_alignment(dev
, &alignment_info
);
141 fprintf(stderr
, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
145 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_DMA
, 0, &dma
);
147 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
151 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_GFX
, 0, &gfx
);
153 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
157 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_COMPUTE
, 0, &compute
);
159 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
163 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_UVD
, 0, &uvd
);
165 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
169 if (info
->drm_minor
>= 17) {
170 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_UVD_ENC
, 0, &uvd_enc
);
172 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
177 if (info
->drm_minor
>= 17) {
178 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCN_DEC
, 0, &vcn_dec
);
180 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
185 if (info
->drm_minor
>= 17) {
186 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCN_ENC
, 0, &vcn_enc
);
188 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
193 if (info
->drm_minor
>= 27) {
194 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCN_JPEG
, 0, &vcn_jpeg
);
196 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
201 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_ME
, 0, 0,
202 &info
->me_fw_version
,
203 &info
->me_fw_feature
);
205 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
209 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_PFP
, 0, 0,
210 &info
->pfp_fw_version
,
211 &info
->pfp_fw_feature
);
213 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
217 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_CE
, 0, 0,
218 &info
->ce_fw_version
,
219 &info
->ce_fw_feature
);
221 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
225 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_UVD
, 0, 0,
226 &uvd_version
, &uvd_feature
);
228 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
232 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCE
, 0, &vce
);
234 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
238 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_VCE
, 0, 0,
239 &vce_version
, &vce_feature
);
241 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
245 r
= amdgpu_query_sw_info(dev
, amdgpu_sw_info_address32_hi
, &info
->address32_hi
);
247 fprintf(stderr
, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
251 r
= amdgpu_query_gds_info(dev
, &gds
);
253 fprintf(stderr
, "amdgpu: amdgpu_query_gds_info failed.\n");
257 if (info
->drm_minor
>= 9) {
258 struct drm_amdgpu_memory_info meminfo
= {};
260 r
= amdgpu_query_info(dev
, AMDGPU_INFO_MEMORY
, sizeof(meminfo
), &meminfo
);
262 fprintf(stderr
, "amdgpu: amdgpu_query_info(memory) failed.\n");
266 /* Note: usable_heap_size values can be random and can't be relied on. */
267 info
->gart_size
= meminfo
.gtt
.total_heap_size
;
268 info
->vram_size
= meminfo
.vram
.total_heap_size
;
269 info
->vram_vis_size
= meminfo
.cpu_accessible_vram
.total_heap_size
;
271 /* This is a deprecated interface, which reports usable sizes
272 * (total minus pinned), but the pinned size computation is
273 * buggy, so the values returned from these functions can be
276 struct amdgpu_heap_info vram
, vram_vis
, gtt
;
278 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &vram
);
280 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
284 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_VRAM
,
285 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
288 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
292 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, >t
);
294 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
298 info
->gart_size
= gtt
.heap_size
;
299 info
->vram_size
= vram
.heap_size
;
300 info
->vram_vis_size
= vram_vis
.heap_size
;
303 /* Set chip identification. */
304 info
->pci_id
= amdinfo
->asic_id
; /* TODO: is this correct? */
305 info
->vce_harvest_config
= amdinfo
->vce_harvest_config
;
307 switch (info
->pci_id
) {
308 #define CHIPSET(pci_id, cfamily) \
310 info->family = CHIP_##cfamily; \
311 info->name = #cfamily; \
313 #include "pci_ids/radeonsi_pci_ids.h"
317 fprintf(stderr
, "amdgpu: Invalid PCI ID.\n");
321 /* Raven2 uses the same PCI IDs as Raven1, but different revision IDs. */
322 if (info
->family
== CHIP_RAVEN
&& amdinfo
->chip_rev
>= 0x8) {
323 info
->family
= CHIP_RAVEN2
;
324 info
->name
= "RAVEN2";
327 if (info
->family
>= CHIP_NAVI10
)
328 info
->chip_class
= GFX10
;
329 else if (info
->family
>= CHIP_VEGA10
)
330 info
->chip_class
= GFX9
;
331 else if (info
->family
>= CHIP_TONGA
)
332 info
->chip_class
= GFX8
;
333 else if (info
->family
>= CHIP_BONAIRE
)
334 info
->chip_class
= GFX7
;
335 else if (info
->family
>= CHIP_TAHITI
)
336 info
->chip_class
= GFX6
;
338 fprintf(stderr
, "amdgpu: Unknown family.\n");
342 info
->family_id
= amdinfo
->family_id
;
343 info
->chip_external_rev
= amdinfo
->chip_external_rev
;
344 info
->marketing_name
= amdgpu_get_marketing_name(dev
);
345 info
->is_pro_graphics
= info
->marketing_name
&&
346 (!strcmp(info
->marketing_name
, "Pro") ||
347 !strcmp(info
->marketing_name
, "PRO") ||
348 !strcmp(info
->marketing_name
, "Frontier"));
350 /* Set which chips have dedicated VRAM. */
351 info
->has_dedicated_vram
=
352 !(amdinfo
->ids_flags
& AMDGPU_IDS_FLAGS_FUSION
);
354 /* The kernel can split large buffers in VRAM but not in GTT, so large
355 * allocations can fail or cause buffer movement failures in the kernel.
357 if (info
->has_dedicated_vram
)
358 info
->max_alloc_size
= info
->vram_size
* 0.8;
360 info
->max_alloc_size
= info
->gart_size
* 0.7;
362 /* Set hardware information. */
363 info
->gds_size
= gds
.gds_total_size
;
364 info
->gds_gfx_partition_size
= gds
.gds_gfx_partition_size
;
365 /* convert the shader clock from KHz to MHz */
366 info
->max_shader_clock
= amdinfo
->max_engine_clk
/ 1000;
367 info
->num_tcc_blocks
= device_info
.num_tcc_blocks
;
368 info
->max_se
= amdinfo
->num_shader_engines
;
369 info
->max_sh_per_se
= amdinfo
->num_shader_arrays_per_engine
;
370 info
->has_hw_decode
=
371 (uvd
.available_rings
!= 0) || (vcn_dec
.available_rings
!= 0) ||
372 (vcn_jpeg
.available_rings
!= 0);
373 info
->uvd_fw_version
=
374 uvd
.available_rings
? uvd_version
: 0;
375 info
->vce_fw_version
=
376 vce
.available_rings
? vce_version
: 0;
377 info
->uvd_enc_supported
=
378 uvd_enc
.available_rings
? true : false;
379 info
->has_userptr
= true;
380 info
->has_syncobj
= has_syncobj(fd
);
381 info
->has_syncobj_wait_for_submit
= info
->has_syncobj
&& info
->drm_minor
>= 20;
382 info
->has_fence_to_handle
= info
->has_syncobj
&& info
->drm_minor
>= 21;
383 info
->has_ctx_priority
= info
->drm_minor
>= 22;
384 info
->has_local_buffers
= info
->drm_minor
>= 20;
385 info
->kernel_flushes_hdp_before_ib
= true;
386 info
->htile_cmask_support_1d_tiling
= true;
387 info
->si_TA_CS_BC_BASE_ADDR_allowed
= true;
388 info
->has_bo_metadata
= true;
389 info
->has_gpu_reset_status_query
= true;
390 info
->has_eqaa_surface_allocator
= true;
391 info
->has_format_bc1_through_bc7
= true;
392 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
393 info
->kernel_flushes_tc_l2_after_ib
= info
->chip_class
!= GFX8
||
394 info
->drm_minor
>= 2;
395 info
->has_indirect_compute_dispatch
= true;
396 /* GFX6 doesn't support unaligned loads. */
397 info
->has_unaligned_shader_loads
= info
->chip_class
!= GFX6
;
398 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
399 * these faults are mitigated in software.
400 * Disable sparse mappings on GFX9 due to hangs.
402 info
->has_sparse_vm_mappings
=
403 info
->chip_class
>= GFX7
&& info
->chip_class
<= GFX8
&&
404 info
->drm_minor
>= 13;
405 info
->has_2d_tiling
= true;
406 info
->has_read_registers_query
= true;
407 info
->has_scheduled_fence_dependency
= info
->drm_minor
>= 28;
409 info
->pa_sc_tile_steering_override
= device_info
.pa_sc_tile_steering_override
;
410 info
->num_render_backends
= amdinfo
->rb_pipes
;
411 /* The value returned by the kernel driver was wrong. */
412 if (info
->family
== CHIP_KAVERI
)
413 info
->num_render_backends
= 2;
415 info
->clock_crystal_freq
= amdinfo
->gpu_counter_freq
;
416 if (!info
->clock_crystal_freq
) {
417 fprintf(stderr
, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
418 info
->clock_crystal_freq
= 1;
420 if (info
->chip_class
>= GFX10
) {
421 info
->tcc_cache_line_size
= 128;
423 info
->tcc_cache_line_size
= 64;
425 info
->gb_addr_config
= amdinfo
->gb_addr_cfg
;
426 if (info
->chip_class
== GFX9
) {
427 info
->num_tile_pipes
= 1 << G_0098F8_NUM_PIPES(amdinfo
->gb_addr_cfg
);
428 info
->pipe_interleave_bytes
=
429 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo
->gb_addr_cfg
);
431 info
->num_tile_pipes
= cik_get_num_tile_pipes(amdinfo
);
432 info
->pipe_interleave_bytes
=
433 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo
->gb_addr_cfg
);
435 info
->r600_has_virtual_memory
= true;
437 assert(util_is_power_of_two_or_zero(dma
.available_rings
+ 1));
438 assert(util_is_power_of_two_or_zero(compute
.available_rings
+ 1));
440 info
->has_graphics
= gfx
.available_rings
> 0;
441 info
->num_sdma_rings
= util_bitcount(dma
.available_rings
);
442 info
->num_compute_rings
= util_bitcount(compute
.available_rings
);
444 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
445 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
446 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
448 info
->has_clear_state
= info
->chip_class
>= GFX7
;
450 info
->has_distributed_tess
= info
->chip_class
>= GFX8
&&
453 info
->has_dcc_constant_encode
= info
->family
== CHIP_RAVEN2
||
454 info
->family
== CHIP_RENOIR
||
455 info
->chip_class
>= GFX10
;
457 info
->has_rbplus
= info
->family
== CHIP_STONEY
||
458 info
->chip_class
>= GFX9
;
460 /* Some chips have RB+ registers, but don't support RB+. Those must
463 info
->rbplus_allowed
= info
->has_rbplus
&&
464 (info
->family
== CHIP_STONEY
||
465 info
->family
== CHIP_VEGA12
||
466 info
->family
== CHIP_RAVEN
||
467 info
->family
== CHIP_RAVEN2
||
468 info
->family
== CHIP_RENOIR
);
470 info
->has_out_of_order_rast
= info
->chip_class
>= GFX8
&&
473 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
474 info
->has_load_ctx_reg_pkt
= info
->chip_class
>= GFX9
||
475 (info
->chip_class
>= GFX8
&&
476 info
->me_fw_feature
>= 41);
478 info
->cpdma_prefetch_writes_memory
= info
->chip_class
<= GFX8
;
480 info
->has_gfx9_scissor_bug
= info
->family
== CHIP_VEGA10
||
481 info
->family
== CHIP_RAVEN
;
483 info
->has_tc_compat_zrange_bug
= info
->chip_class
>= GFX8
&&
484 info
->chip_class
<= GFX9
;
486 info
->has_msaa_sample_loc_bug
= (info
->family
>= CHIP_POLARIS10
&&
487 info
->family
<= CHIP_POLARIS12
) ||
488 info
->family
== CHIP_VEGA10
||
489 info
->family
== CHIP_RAVEN
;
491 info
->has_ls_vgpr_init_bug
= info
->family
== CHIP_VEGA10
||
492 info
->family
== CHIP_RAVEN
;
494 /* Get the number of good compute units. */
495 info
->num_good_compute_units
= 0;
496 for (i
= 0; i
< info
->max_se
; i
++)
497 for (j
= 0; j
< info
->max_sh_per_se
; j
++)
498 info
->num_good_compute_units
+=
499 util_bitcount(amdinfo
->cu_bitmap
[i
][j
]);
500 info
->num_good_cu_per_sh
= info
->num_good_compute_units
/
501 (info
->max_se
* info
->max_sh_per_se
);
503 memcpy(info
->si_tile_mode_array
, amdinfo
->gb_tile_mode
,
504 sizeof(amdinfo
->gb_tile_mode
));
505 info
->enabled_rb_mask
= amdinfo
->enabled_rb_pipes_mask
;
507 memcpy(info
->cik_macrotile_mode_array
, amdinfo
->gb_macro_tile_mode
,
508 sizeof(amdinfo
->gb_macro_tile_mode
));
510 info
->pte_fragment_size
= alignment_info
.size_local
;
511 info
->gart_page_size
= alignment_info
.size_remote
;
513 if (info
->chip_class
== GFX6
)
514 info
->gfx_ib_pad_with_type2
= true;
516 unsigned ib_align
= 0;
517 ib_align
= MAX2(ib_align
, gfx
.ib_start_alignment
);
518 ib_align
= MAX2(ib_align
, compute
.ib_start_alignment
);
519 ib_align
= MAX2(ib_align
, dma
.ib_start_alignment
);
520 ib_align
= MAX2(ib_align
, uvd
.ib_start_alignment
);
521 ib_align
= MAX2(ib_align
, uvd_enc
.ib_start_alignment
);
522 ib_align
= MAX2(ib_align
, vce
.ib_start_alignment
);
523 ib_align
= MAX2(ib_align
, vcn_dec
.ib_start_alignment
);
524 ib_align
= MAX2(ib_align
, vcn_enc
.ib_start_alignment
);
525 ib_align
= MAX2(ib_align
, vcn_jpeg
.ib_start_alignment
);
527 info
->ib_start_alignment
= ib_align
;
529 if (info
->drm_minor
>= 31 &&
530 (info
->family
== CHIP_RAVEN
||
531 info
->family
== CHIP_RAVEN2
||
532 info
->family
== CHIP_RENOIR
)) {
533 if (info
->num_render_backends
== 1)
534 info
->use_display_dcc_unaligned
= true;
536 info
->use_display_dcc_with_retile_blit
= true;
539 info
->has_gds_ordered_append
= info
->chip_class
>= GFX7
&&
540 info
->drm_minor
>= 29;
544 void ac_compute_driver_uuid(char *uuid
, size_t size
)
546 char amd_uuid
[] = "AMD-MESA-DRV";
548 assert(size
>= sizeof(amd_uuid
));
550 memset(uuid
, 0, size
);
551 strncpy(uuid
, amd_uuid
, size
);
554 void ac_compute_device_uuid(struct radeon_info
*info
, char *uuid
, size_t size
)
556 uint32_t *uint_uuid
= (uint32_t*)uuid
;
558 assert(size
>= sizeof(uint32_t)*4);
561 * Use the device info directly instead of using a sha1. GL/VK UUIDs
562 * are 16 byte vs 20 byte for sha1, and the truncation that would be
563 * required would get rid of part of the little entropy we have.
565 memset(uuid
, 0, size
);
566 uint_uuid
[0] = info
->pci_domain
;
567 uint_uuid
[1] = info
->pci_bus
;
568 uint_uuid
[2] = info
->pci_dev
;
569 uint_uuid
[3] = info
->pci_func
;
572 void ac_print_gpu_info(struct radeon_info
*info
)
574 printf("Device info:\n");
575 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
576 info
->pci_domain
, info
->pci_bus
,
577 info
->pci_dev
, info
->pci_func
);
578 printf(" pci_id = 0x%x\n", info
->pci_id
);
579 printf(" family = %i\n", info
->family
);
580 printf(" chip_class = %i\n", info
->chip_class
);
581 printf(" chip_external_rev = %i\n", info
->chip_external_rev
);
582 printf(" num_compute_rings = %u\n", info
->num_compute_rings
);
583 printf(" num_sdma_rings = %i\n", info
->num_sdma_rings
);
584 printf(" clock_crystal_freq = %i\n", info
->clock_crystal_freq
);
585 printf(" tcc_cache_line_size = %u\n", info
->tcc_cache_line_size
);
587 printf(" use_display_dcc_unaligned = %u\n", info
->use_display_dcc_unaligned
);
588 printf(" use_display_dcc_with_retile_blit = %u\n", info
->use_display_dcc_with_retile_blit
);
590 printf("Memory info:\n");
591 printf(" pte_fragment_size = %u\n", info
->pte_fragment_size
);
592 printf(" gart_page_size = %u\n", info
->gart_page_size
);
593 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info
->gart_size
, 1024*1024));
594 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info
->vram_size
, 1024*1024));
595 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info
->vram_vis_size
, 1024*1024));
596 printf(" gds_size = %u kB\n", info
->gds_size
/ 1024);
597 printf(" gds_gfx_partition_size = %u kB\n", info
->gds_gfx_partition_size
/ 1024);
598 printf(" max_alloc_size = %i MB\n",
599 (int)DIV_ROUND_UP(info
->max_alloc_size
, 1024*1024));
600 printf(" min_alloc_size = %u\n", info
->min_alloc_size
);
601 printf(" address32_hi = %u\n", info
->address32_hi
);
602 printf(" has_dedicated_vram = %u\n", info
->has_dedicated_vram
);
604 printf("CP info:\n");
605 printf(" gfx_ib_pad_with_type2 = %i\n", info
->gfx_ib_pad_with_type2
);
606 printf(" ib_start_alignment = %u\n", info
->ib_start_alignment
);
607 printf(" me_fw_version = %i\n", info
->me_fw_version
);
608 printf(" me_fw_feature = %i\n", info
->me_fw_feature
);
609 printf(" pfp_fw_version = %i\n", info
->pfp_fw_version
);
610 printf(" pfp_fw_feature = %i\n", info
->pfp_fw_feature
);
611 printf(" ce_fw_version = %i\n", info
->ce_fw_version
);
612 printf(" ce_fw_feature = %i\n", info
->ce_fw_feature
);
614 printf("Multimedia info:\n");
615 printf(" has_hw_decode = %u\n", info
->has_hw_decode
);
616 printf(" uvd_enc_supported = %u\n", info
->uvd_enc_supported
);
617 printf(" uvd_fw_version = %u\n", info
->uvd_fw_version
);
618 printf(" vce_fw_version = %u\n", info
->vce_fw_version
);
619 printf(" vce_harvest_config = %i\n", info
->vce_harvest_config
);
621 printf("Kernel & winsys capabilities:\n");
622 printf(" drm = %i.%i.%i\n", info
->drm_major
,
623 info
->drm_minor
, info
->drm_patchlevel
);
624 printf(" has_userptr = %i\n", info
->has_userptr
);
625 printf(" has_syncobj = %u\n", info
->has_syncobj
);
626 printf(" has_syncobj_wait_for_submit = %u\n", info
->has_syncobj_wait_for_submit
);
627 printf(" has_fence_to_handle = %u\n", info
->has_fence_to_handle
);
628 printf(" has_ctx_priority = %u\n", info
->has_ctx_priority
);
629 printf(" has_local_buffers = %u\n", info
->has_local_buffers
);
630 printf(" kernel_flushes_hdp_before_ib = %u\n", info
->kernel_flushes_hdp_before_ib
);
631 printf(" htile_cmask_support_1d_tiling = %u\n", info
->htile_cmask_support_1d_tiling
);
632 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info
->si_TA_CS_BC_BASE_ADDR_allowed
);
633 printf(" has_bo_metadata = %u\n", info
->has_bo_metadata
);
634 printf(" has_gpu_reset_status_query = %u\n", info
->has_gpu_reset_status_query
);
635 printf(" has_eqaa_surface_allocator = %u\n", info
->has_eqaa_surface_allocator
);
636 printf(" has_format_bc1_through_bc7 = %u\n", info
->has_format_bc1_through_bc7
);
637 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info
->kernel_flushes_tc_l2_after_ib
);
638 printf(" has_indirect_compute_dispatch = %u\n", info
->has_indirect_compute_dispatch
);
639 printf(" has_unaligned_shader_loads = %u\n", info
->has_unaligned_shader_loads
);
640 printf(" has_sparse_vm_mappings = %u\n", info
->has_sparse_vm_mappings
);
641 printf(" has_2d_tiling = %u\n", info
->has_2d_tiling
);
642 printf(" has_read_registers_query = %u\n", info
->has_read_registers_query
);
643 printf(" has_gds_ordered_append = %u\n", info
->has_gds_ordered_append
);
644 printf(" has_scheduled_fence_dependency = %u\n", info
->has_scheduled_fence_dependency
);
646 printf("Shader core info:\n");
647 printf(" max_shader_clock = %i\n", info
->max_shader_clock
);
648 printf(" num_good_compute_units = %i\n", info
->num_good_compute_units
);
649 printf(" num_good_cu_per_sh = %i\n", info
->num_good_cu_per_sh
);
650 printf(" num_tcc_blocks = %i\n", info
->num_tcc_blocks
);
651 printf(" max_se = %i\n", info
->max_se
);
652 printf(" max_sh_per_se = %i\n", info
->max_sh_per_se
);
654 printf("Render backend info:\n");
655 printf(" pa_sc_tile_steering_override = 0x%x\n", info
->pa_sc_tile_steering_override
);
656 printf(" num_render_backends = %i\n", info
->num_render_backends
);
657 printf(" num_tile_pipes = %i\n", info
->num_tile_pipes
);
658 printf(" pipe_interleave_bytes = %i\n", info
->pipe_interleave_bytes
);
659 printf(" enabled_rb_mask = 0x%x\n", info
->enabled_rb_mask
);
660 printf(" max_alignment = %u\n", (unsigned)info
->max_alignment
);
662 printf("GB_ADDR_CONFIG:\n");
663 if (info
->chip_class
>= GFX9
) {
664 printf(" num_pipes = %u\n",
665 1 << G_0098F8_NUM_PIPES(info
->gb_addr_config
));
666 printf(" pipe_interleave_size = %u\n",
667 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info
->gb_addr_config
));
668 printf(" max_compressed_frags = %u\n",
669 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info
->gb_addr_config
));
670 printf(" bank_interleave_size = %u\n",
671 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info
->gb_addr_config
));
672 printf(" num_banks = %u\n",
673 1 << G_0098F8_NUM_BANKS(info
->gb_addr_config
));
674 printf(" shader_engine_tile_size = %u\n",
675 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info
->gb_addr_config
));
676 printf(" num_shader_engines = %u\n",
677 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info
->gb_addr_config
));
678 printf(" num_gpus = %u (raw)\n",
679 G_0098F8_NUM_GPUS_GFX9(info
->gb_addr_config
));
680 printf(" multi_gpu_tile_size = %u (raw)\n",
681 G_0098F8_MULTI_GPU_TILE_SIZE(info
->gb_addr_config
));
682 printf(" num_rb_per_se = %u\n",
683 1 << G_0098F8_NUM_RB_PER_SE(info
->gb_addr_config
));
684 printf(" row_size = %u\n",
685 1024 << G_0098F8_ROW_SIZE(info
->gb_addr_config
));
686 printf(" num_lower_pipes = %u (raw)\n",
687 G_0098F8_NUM_LOWER_PIPES(info
->gb_addr_config
));
688 printf(" se_enable = %u (raw)\n",
689 G_0098F8_SE_ENABLE(info
->gb_addr_config
));
691 printf(" num_pipes = %u\n",
692 1 << G_0098F8_NUM_PIPES(info
->gb_addr_config
));
693 printf(" pipe_interleave_size = %u\n",
694 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info
->gb_addr_config
));
695 printf(" bank_interleave_size = %u\n",
696 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info
->gb_addr_config
));
697 printf(" num_shader_engines = %u\n",
698 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info
->gb_addr_config
));
699 printf(" shader_engine_tile_size = %u\n",
700 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info
->gb_addr_config
));
701 printf(" num_gpus = %u (raw)\n",
702 G_0098F8_NUM_GPUS_GFX6(info
->gb_addr_config
));
703 printf(" multi_gpu_tile_size = %u (raw)\n",
704 G_0098F8_MULTI_GPU_TILE_SIZE(info
->gb_addr_config
));
705 printf(" row_size = %u\n",
706 1024 << G_0098F8_ROW_SIZE(info
->gb_addr_config
));
707 printf(" num_lower_pipes = %u (raw)\n",
708 G_0098F8_NUM_LOWER_PIPES(info
->gb_addr_config
));
713 ac_get_gs_table_depth(enum chip_class chip_class
, enum radeon_family family
)
715 if (chip_class
>= GFX9
)
740 unreachable("Unknown GPU");
745 ac_get_raster_config(struct radeon_info
*info
,
746 uint32_t *raster_config_p
,
747 uint32_t *raster_config_1_p
,
748 uint32_t *se_tile_repeat_p
)
750 unsigned raster_config
, raster_config_1
, se_tile_repeat
;
752 switch (info
->family
) {
757 raster_config
= 0x00000000;
758 raster_config_1
= 0x00000000;
762 raster_config
= 0x0000124a;
763 raster_config_1
= 0x00000000;
765 /* 1 SE / 2 RBs (Oland is special) */
767 raster_config
= 0x00000082;
768 raster_config_1
= 0x00000000;
774 raster_config
= 0x00000002;
775 raster_config_1
= 0x00000000;
781 raster_config
= 0x16000012;
782 raster_config_1
= 0x00000000;
787 raster_config
= 0x2a00126a;
788 raster_config_1
= 0x00000000;
793 raster_config
= 0x16000012;
794 raster_config_1
= 0x0000002a;
800 raster_config
= 0x3a00161a;
801 raster_config_1
= 0x0000002e;
805 "ac: Unknown GPU, using 0 for raster_config\n");
806 raster_config
= 0x00000000;
807 raster_config_1
= 0x00000000;
811 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
812 * This decreases performance by up to 50% when the RB is the bottleneck.
814 if (info
->family
== CHIP_KAVERI
&& !info
->is_amdgpu
)
815 raster_config
= 0x00000000;
817 /* Fiji: Old kernels have incorrect tiling config. This decreases
818 * RB performance by 25%. (it disables 1 RB in the second packer)
820 if (info
->family
== CHIP_FIJI
&&
821 info
->cik_macrotile_mode_array
[0] == 0x000000e8) {
822 raster_config
= 0x16000012;
823 raster_config_1
= 0x0000002a;
826 unsigned se_width
= 8 << G_028350_SE_XSEL_GFX6(raster_config
);
827 unsigned se_height
= 8 << G_028350_SE_YSEL_GFX6(raster_config
);
829 /* I don't know how to calculate this, though this is probably a good guess. */
830 se_tile_repeat
= MAX2(se_width
, se_height
) * info
->max_se
;
832 *raster_config_p
= raster_config
;
833 *raster_config_1_p
= raster_config_1
;
834 if (se_tile_repeat_p
)
835 *se_tile_repeat_p
= se_tile_repeat
;
839 ac_get_harvested_configs(struct radeon_info
*info
,
840 unsigned raster_config
,
841 unsigned *cik_raster_config_1_p
,
842 unsigned *raster_config_se
)
844 unsigned sh_per_se
= MAX2(info
->max_sh_per_se
, 1);
845 unsigned num_se
= MAX2(info
->max_se
, 1);
846 unsigned rb_mask
= info
->enabled_rb_mask
;
847 unsigned num_rb
= MIN2(info
->num_render_backends
, 16);
848 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
849 unsigned rb_per_se
= num_rb
/ num_se
;
853 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
854 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
855 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
856 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
858 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
859 assert(sh_per_se
== 1 || sh_per_se
== 2);
860 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
863 if (info
->chip_class
>= GFX7
) {
864 unsigned raster_config_1
= *cik_raster_config_1_p
;
865 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
866 (!se_mask
[2] && !se_mask
[3]))) {
867 raster_config_1
&= C_028354_SE_PAIR_MAP
;
869 if (!se_mask
[0] && !se_mask
[1]) {
871 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
874 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
876 *cik_raster_config_1_p
= raster_config_1
;
880 for (se
= 0; se
< num_se
; se
++) {
881 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
882 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
883 int idx
= (se
/ 2) * 2;
885 raster_config_se
[se
] = raster_config
;
886 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
887 raster_config_se
[se
] &= C_028350_SE_MAP
;
890 raster_config_se
[se
] |=
891 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
893 raster_config_se
[se
] |=
894 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
898 pkr0_mask
&= rb_mask
;
899 pkr1_mask
&= rb_mask
;
900 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
901 raster_config_se
[se
] &= C_028350_PKR_MAP
;
904 raster_config_se
[se
] |=
905 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
907 raster_config_se
[se
] |=
908 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
912 if (rb_per_se
>= 2) {
913 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
914 unsigned rb1_mask
= rb0_mask
<< 1;
918 if (!rb0_mask
|| !rb1_mask
) {
919 raster_config_se
[se
] &= C_028350_RB_MAP_PKR0
;
922 raster_config_se
[se
] |=
923 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
925 raster_config_se
[se
] |=
926 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
931 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
932 rb1_mask
= rb0_mask
<< 1;
935 if (!rb0_mask
|| !rb1_mask
) {
936 raster_config_se
[se
] &= C_028350_RB_MAP_PKR1
;
939 raster_config_se
[se
] |=
940 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
942 raster_config_se
[se
] |=
943 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
951 unsigned ac_get_compute_resource_limits(struct radeon_info
*info
,
952 unsigned waves_per_threadgroup
,
953 unsigned max_waves_per_sh
,
954 unsigned threadgroups_per_cu
)
956 unsigned compute_resource_limits
=
957 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup
% 4 == 0);
959 if (info
->chip_class
>= GFX7
) {
960 unsigned num_cu_per_se
= info
->num_good_compute_units
/
963 /* Force even distribution on all SIMDs in CU if the workgroup
964 * size is 64. This has shown some good improvements if # of CUs
965 * per SE is not a multiple of 4.
967 if (num_cu_per_se
% 4 && waves_per_threadgroup
== 1)
968 compute_resource_limits
|= S_00B854_FORCE_SIMD_DIST(1);
970 assert(threadgroups_per_cu
>= 1 && threadgroups_per_cu
<= 8);
971 compute_resource_limits
|= S_00B854_WAVES_PER_SH(max_waves_per_sh
) |
972 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu
- 1);
975 if (max_waves_per_sh
) {
976 unsigned limit_div16
= DIV_ROUND_UP(max_waves_per_sh
, 16);
977 compute_resource_limits
|= S_00B854_WAVES_PER_SH_SI(limit_div16
);
980 return compute_resource_limits
;