projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ac/surface: remove addrlib_family_rev_id
[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "sid.h"
28
29 #include "util/u_math.h"
30
31 #include <stdio.h>
32
33 #include <xf86drm.h>
34 #include <amdgpu_drm.h>
35
36 #include <amdgpu.h>
37
38 #define CIK_TILE_MODE_COLOR_2D 14
39
40 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
41 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
42 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
55
56 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
57 {
58 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
59
60 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
61 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
62 return 2;
63 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
67 return 4;
68 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
75 return 8;
76 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
78 return 16;
79 default:
80 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
81 assert(!"this should never occur");
82 return 2;
83 }
84 }
85
86 static bool has_syncobj(int fd)
87 {
88 uint64_t value;
89 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
90 return false;
91 return value ? true : false;
92 }
93
94 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
95 struct radeon_info *info,
96 struct amdgpu_gpu_info *amdinfo)
97 {
98 struct drm_amdgpu_info_device device_info = {};
99 struct amdgpu_buffer_size_alignments alignment_info = {};
100 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
101 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
102 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
103 struct amdgpu_gds_resource_info gds = {};
104 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
105 int r, i, j;
106 drmDevicePtr devinfo;
107
108 /* Get PCI info. */
109 r = drmGetDevice2(fd, 0, &devinfo);
110 if (r) {
111 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
112 return false;
113 }
114 info->pci_domain = devinfo->businfo.pci->domain;
115 info->pci_bus = devinfo->businfo.pci->bus;
116 info->pci_dev = devinfo->businfo.pci->dev;
117 info->pci_func = devinfo->businfo.pci->func;
118 drmFreeDevice(&devinfo);
119
120 assert(info->drm_major == 3);
121 info->is_amdgpu = true;
122
123 /* Query hardware and driver information. */
124 r = amdgpu_query_gpu_info(dev, amdinfo);
125 if (r) {
126 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
127 return false;
128 }
129
130 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
131 &device_info);
132 if (r) {
133 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
134 return false;
135 }
136
137 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
138 if (r) {
139 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
140 return false;
141 }
142
143 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
144 if (r) {
145 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
146 return false;
147 }
148
149 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
150 if (r) {
151 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
152 return false;
153 }
154
155 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
156 if (r) {
157 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
158 return false;
159 }
160
161 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
162 if (r) {
163 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
164 return false;
165 }
166
167 if (info->drm_minor >= 17) {
168 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
169 if (r) {
170 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
171 return false;
172 }
173 }
174
175 if (info->drm_minor >= 17) {
176 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
177 if (r) {
178 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
179 return false;
180 }
181 }
182
183 if (info->drm_minor >= 17) {
184 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
185 if (r) {
186 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
187 return false;
188 }
189 }
190
191 if (info->drm_minor >= 27) {
192 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
193 if (r) {
194 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
195 return false;
196 }
197 }
198
199 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
200 &info->me_fw_version,
201 &info->me_fw_feature);
202 if (r) {
203 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
204 return false;
205 }
206
207 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
208 &info->pfp_fw_version,
209 &info->pfp_fw_feature);
210 if (r) {
211 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
212 return false;
213 }
214
215 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
216 &info->ce_fw_version,
217 &info->ce_fw_feature);
218 if (r) {
219 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
220 return false;
221 }
222
223 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
224 &uvd_version, &uvd_feature);
225 if (r) {
226 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
227 return false;
228 }
229
230 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
231 if (r) {
232 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
233 return false;
234 }
235
236 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
237 &vce_version, &vce_feature);
238 if (r) {
239 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
240 return false;
241 }
242
243 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
244 if (r) {
245 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
246 return false;
247 }
248
249 r = amdgpu_query_gds_info(dev, &gds);
250 if (r) {
251 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
252 return false;
253 }
254
255 if (info->drm_minor >= 9) {
256 struct drm_amdgpu_memory_info meminfo = {};
257
258 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
259 if (r) {
260 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
261 return false;
262 }
263
264 /* Note: usable_heap_size values can be random and can't be relied on. */
265 info->gart_size = meminfo.gtt.total_heap_size;
266 info->vram_size = meminfo.vram.total_heap_size;
267 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
268 } else {
269 /* This is a deprecated interface, which reports usable sizes
270 * (total minus pinned), but the pinned size computation is
271 * buggy, so the values returned from these functions can be
272 * random.
273 */
274 struct amdgpu_heap_info vram, vram_vis, gtt;
275
276 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
277 if (r) {
278 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
279 return false;
280 }
281
282 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
283 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
284 &vram_vis);
285 if (r) {
286 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
287 return false;
288 }
289
290 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
291 if (r) {
292 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
293 return false;
294 }
295
296 info->gart_size = gtt.heap_size;
297 info->vram_size = vram.heap_size;
298 info->vram_vis_size = vram_vis.heap_size;
299 }
300
301 /* Set chip identification. */
302 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
303 info->vce_harvest_config = amdinfo->vce_harvest_config;
304
305 switch (info->pci_id) {
306 #define CHIPSET(pci_id, cfamily) \
307 case pci_id: \
308 info->family = CHIP_##cfamily; \
309 info->name = #cfamily; \
310 break;
311 #include "pci_ids/radeonsi_pci_ids.h"
312 #undef CHIPSET
313
314 default:
315 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
316 return false;
317 }
318
319 /* Raven2 uses the same PCI IDs as Raven1, but different revision IDs. */
320 if (info->family == CHIP_RAVEN && amdinfo->chip_rev >= 0x8) {
321 info->family = CHIP_RAVEN2;
322 info->name = "RAVEN2";
323 }
324
325 if (info->family >= CHIP_VEGA10)
326 info->chip_class = GFX9;
327 else if (info->family >= CHIP_TONGA)
328 info->chip_class = GFX8;
329 else if (info->family >= CHIP_BONAIRE)
330 info->chip_class = GFX7;
331 else if (info->family >= CHIP_TAHITI)
332 info->chip_class = GFX6;
333 else {
334 fprintf(stderr, "amdgpu: Unknown family.\n");
335 return false;
336 }
337
338 info->family_id = amdinfo->family_id;
339 info->chip_external_rev = amdinfo->chip_external_rev;
340 info->marketing_name = amdgpu_get_marketing_name(dev);
341 info->is_pro_graphics = info->marketing_name &&
342 (!strcmp(info->marketing_name, "Pro") ||
343 !strcmp(info->marketing_name, "PRO") ||
344 !strcmp(info->marketing_name, "Frontier"));
345
346 /* Set which chips have dedicated VRAM. */
347 info->has_dedicated_vram =
348 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
349
350 /* The kernel can split large buffers in VRAM but not in GTT, so large
351 * allocations can fail or cause buffer movement failures in the kernel.
352 */
353 if (info->has_dedicated_vram)
354 info->max_alloc_size = info->vram_size * 0.8;
355 else
356 info->max_alloc_size = info->gart_size * 0.7;
357
358 /* Set hardware information. */
359 info->gds_size = gds.gds_total_size;
360 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
361 /* convert the shader clock from KHz to MHz */
362 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
363 info->num_tcc_blocks = device_info.num_tcc_blocks;
364 info->max_se = amdinfo->num_shader_engines;
365 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
366 info->has_hw_decode =
367 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
368 (vcn_jpeg.available_rings != 0);
369 info->uvd_fw_version =
370 uvd.available_rings ? uvd_version : 0;
371 info->vce_fw_version =
372 vce.available_rings ? vce_version : 0;
373 info->uvd_enc_supported =
374 uvd_enc.available_rings ? true : false;
375 info->has_userptr = true;
376 info->has_syncobj = has_syncobj(fd);
377 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
378 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
379 info->has_ctx_priority = info->drm_minor >= 22;
380 info->has_local_buffers = info->drm_minor >= 20;
381 info->kernel_flushes_hdp_before_ib = true;
382 info->htile_cmask_support_1d_tiling = true;
383 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
384 info->has_bo_metadata = true;
385 info->has_gpu_reset_status_query = true;
386 info->has_eqaa_surface_allocator = true;
387 info->has_format_bc1_through_bc7 = true;
388 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
389 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
390 info->drm_minor >= 2;
391 info->has_indirect_compute_dispatch = true;
392 /* GFX6 doesn't support unaligned loads. */
393 info->has_unaligned_shader_loads = info->chip_class != GFX6;
394 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
395 * these faults are mitigated in software.
396 * Disable sparse mappings on GFX9 due to hangs.
397 */
398 info->has_sparse_vm_mappings =
399 info->chip_class >= GFX7 && info->chip_class <= GFX8 &&
400 info->drm_minor >= 13;
401 info->has_2d_tiling = true;
402 info->has_read_registers_query = true;
403 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
404
405 info->num_render_backends = amdinfo->rb_pipes;
406 /* The value returned by the kernel driver was wrong. */
407 if (info->family == CHIP_KAVERI)
408 info->num_render_backends = 2;
409
410 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
411 if (!info->clock_crystal_freq) {
412 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
413 info->clock_crystal_freq = 1;
414 }
415 info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
416 info->gb_addr_config = amdinfo->gb_addr_cfg;
417 if (info->chip_class == GFX9) {
418 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
419 info->pipe_interleave_bytes =
420 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
421 } else {
422 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
423 info->pipe_interleave_bytes =
424 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
425 }
426 info->r600_has_virtual_memory = true;
427
428 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
429 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
430
431 info->num_sdma_rings = util_bitcount(dma.available_rings);
432 info->num_compute_rings = util_bitcount(compute.available_rings);
433
434 /* Get the number of good compute units. */
435 info->num_good_compute_units = 0;
436 for (i = 0; i < info->max_se; i++)
437 for (j = 0; j < info->max_sh_per_se; j++)
438 info->num_good_compute_units +=
439 util_bitcount(amdinfo->cu_bitmap[i][j]);
440 info->num_good_cu_per_sh = info->num_good_compute_units /
441 (info->max_se * info->max_sh_per_se);
442
443 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
444 sizeof(amdinfo->gb_tile_mode));
445 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
446
447 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
448 sizeof(amdinfo->gb_macro_tile_mode));
449
450 info->pte_fragment_size = alignment_info.size_local;
451 info->gart_page_size = alignment_info.size_remote;
452
453 if (info->chip_class == GFX6)
454 info->gfx_ib_pad_with_type2 = TRUE;
455
456 unsigned ib_align = 0;
457 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
458 ib_align = MAX2(ib_align, compute.ib_start_alignment);
459 ib_align = MAX2(ib_align, dma.ib_start_alignment);
460 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
461 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
462 ib_align = MAX2(ib_align, vce.ib_start_alignment);
463 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
464 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
465 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
466 assert(ib_align);
467 info->ib_start_alignment = ib_align;
468
469 if (info->drm_minor >= 31 &&
470 (info->family == CHIP_RAVEN ||
471 info->family == CHIP_RAVEN2)) {
472 if (info->num_render_backends == 1)
473 info->use_display_dcc_unaligned = true;
474 else
475 info->use_display_dcc_with_retile_blit = true;
476 }
477
478 info->has_gds_ordered_append = info->chip_class >= GFX7 &&
479 info->drm_minor >= 29 &&
480 HAVE_LLVM >= 0x0800;
481 return true;
482 }
483
484 void ac_compute_driver_uuid(char *uuid, size_t size)
485 {
486 char amd_uuid[] = "AMD-MESA-DRV";
487
488 assert(size >= sizeof(amd_uuid));
489
490 memset(uuid, 0, size);
491 strncpy(uuid, amd_uuid, size);
492 }
493
494 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
495 {
496 uint32_t *uint_uuid = (uint32_t*)uuid;
497
498 assert(size >= sizeof(uint32_t)*4);
499
500 /**
501 * Use the device info directly instead of using a sha1. GL/VK UUIDs
502 * are 16 byte vs 20 byte for sha1, and the truncation that would be
503 * required would get rid of part of the little entropy we have.
504 * */
505 memset(uuid, 0, size);
506 uint_uuid[0] = info->pci_domain;
507 uint_uuid[1] = info->pci_bus;
508 uint_uuid[2] = info->pci_dev;
509 uint_uuid[3] = info->pci_func;
510 }
511
512 void ac_print_gpu_info(struct radeon_info *info)
513 {
514 printf("Device info:\n");
515 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
516 info->pci_domain, info->pci_bus,
517 info->pci_dev, info->pci_func);
518 printf(" pci_id = 0x%x\n", info->pci_id);
519 printf(" family = %i\n", info->family);
520 printf(" chip_class = %i\n", info->chip_class);
521 printf(" num_compute_rings = %u\n", info->num_compute_rings);
522 printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
523 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
524 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
525
526 printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
527 printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
528
529 printf("Memory info:\n");
530 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
531 printf(" gart_page_size = %u\n", info->gart_page_size);
532 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
533 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
534 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
535 printf(" gds_size = %u kB\n", info->gds_size / 1024);
536 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
537 printf(" max_alloc_size = %i MB\n",
538 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
539 printf(" min_alloc_size = %u\n", info->min_alloc_size);
540 printf(" address32_hi = %u\n", info->address32_hi);
541 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
542
543 printf("CP info:\n");
544 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
545 printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
546 printf(" me_fw_version = %i\n", info->me_fw_version);
547 printf(" me_fw_feature = %i\n", info->me_fw_feature);
548 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
549 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
550 printf(" ce_fw_version = %i\n", info->ce_fw_version);
551 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
552
553 printf("Multimedia info:\n");
554 printf(" has_hw_decode = %u\n", info->has_hw_decode);
555 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
556 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
557 printf(" vce_fw_version = %u\n", info->vce_fw_version);
558 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
559
560 printf("Kernel & winsys capabilities:\n");
561 printf(" drm = %i.%i.%i\n", info->drm_major,
562 info->drm_minor, info->drm_patchlevel);
563 printf(" has_userptr = %i\n", info->has_userptr);
564 printf(" has_syncobj = %u\n", info->has_syncobj);
565 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
566 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
567 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
568 printf(" has_local_buffers = %u\n", info->has_local_buffers);
569 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
570 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
571 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
572 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
573 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
574 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
575 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
576 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
577 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
578 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
579 printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
580 printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
581 printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
582 printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
583 printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
584
585 printf("Shader core info:\n");
586 printf(" max_shader_clock = %i\n", info->max_shader_clock);
587 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
588 printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh);
589 printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
590 printf(" max_se = %i\n", info->max_se);
591 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
592
593 printf("Render backend info:\n");
594 printf(" num_render_backends = %i\n", info->num_render_backends);
595 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
596 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
597 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
598 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
599
600 printf("GB_ADDR_CONFIG:\n");
601 if (info->chip_class >= GFX9) {
602 printf(" num_pipes = %u\n",
603 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
604 printf(" pipe_interleave_size = %u\n",
605 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
606 printf(" max_compressed_frags = %u\n",
607 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
608 printf(" bank_interleave_size = %u\n",
609 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
610 printf(" num_banks = %u\n",
611 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
612 printf(" shader_engine_tile_size = %u\n",
613 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
614 printf(" num_shader_engines = %u\n",
615 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
616 printf(" num_gpus = %u (raw)\n",
617 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
618 printf(" multi_gpu_tile_size = %u (raw)\n",
619 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
620 printf(" num_rb_per_se = %u\n",
621 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
622 printf(" row_size = %u\n",
623 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
624 printf(" num_lower_pipes = %u (raw)\n",
625 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
626 printf(" se_enable = %u (raw)\n",
627 G_0098F8_SE_ENABLE(info->gb_addr_config));
628 } else {
629 printf(" num_pipes = %u\n",
630 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
631 printf(" pipe_interleave_size = %u\n",
632 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
633 printf(" bank_interleave_size = %u\n",
634 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
635 printf(" num_shader_engines = %u\n",
636 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
637 printf(" shader_engine_tile_size = %u\n",
638 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
639 printf(" num_gpus = %u (raw)\n",
640 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
641 printf(" multi_gpu_tile_size = %u (raw)\n",
642 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
643 printf(" row_size = %u\n",
644 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
645 printf(" num_lower_pipes = %u (raw)\n",
646 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
647 }
648 }
649
650 int
651 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
652 {
653 if (chip_class >= GFX9)
654 return -1;
655
656 switch (family) {
657 case CHIP_OLAND:
658 case CHIP_HAINAN:
659 case CHIP_KAVERI:
660 case CHIP_KABINI:
661 case CHIP_ICELAND:
662 case CHIP_CARRIZO:
663 case CHIP_STONEY:
664 return 16;
665 case CHIP_TAHITI:
666 case CHIP_PITCAIRN:
667 case CHIP_VERDE:
668 case CHIP_BONAIRE:
669 case CHIP_HAWAII:
670 case CHIP_TONGA:
671 case CHIP_FIJI:
672 case CHIP_POLARIS10:
673 case CHIP_POLARIS11:
674 case CHIP_POLARIS12:
675 case CHIP_VEGAM:
676 return 32;
677 default:
678 unreachable("Unknown GPU");
679 }
680 }
681
682 void
683 ac_get_raster_config(struct radeon_info *info,
684 uint32_t *raster_config_p,
685 uint32_t *raster_config_1_p,
686 uint32_t *se_tile_repeat_p)
687 {
688 unsigned raster_config, raster_config_1, se_tile_repeat;
689
690 switch (info->family) {
691 /* 1 SE / 1 RB */
692 case CHIP_HAINAN:
693 case CHIP_KABINI:
694 case CHIP_STONEY:
695 raster_config = 0x00000000;
696 raster_config_1 = 0x00000000;
697 break;
698 /* 1 SE / 4 RBs */
699 case CHIP_VERDE:
700 raster_config = 0x0000124a;
701 raster_config_1 = 0x00000000;
702 break;
703 /* 1 SE / 2 RBs (Oland is special) */
704 case CHIP_OLAND:
705 raster_config = 0x00000082;
706 raster_config_1 = 0x00000000;
707 break;
708 /* 1 SE / 2 RBs */
709 case CHIP_KAVERI:
710 case CHIP_ICELAND:
711 case CHIP_CARRIZO:
712 raster_config = 0x00000002;
713 raster_config_1 = 0x00000000;
714 break;
715 /* 2 SEs / 4 RBs */
716 case CHIP_BONAIRE:
717 case CHIP_POLARIS11:
718 case CHIP_POLARIS12:
719 raster_config = 0x16000012;
720 raster_config_1 = 0x00000000;
721 break;
722 /* 2 SEs / 8 RBs */
723 case CHIP_TAHITI:
724 case CHIP_PITCAIRN:
725 raster_config = 0x2a00126a;
726 raster_config_1 = 0x00000000;
727 break;
728 /* 4 SEs / 8 RBs */
729 case CHIP_TONGA:
730 case CHIP_POLARIS10:
731 raster_config = 0x16000012;
732 raster_config_1 = 0x0000002a;
733 break;
734 /* 4 SEs / 16 RBs */
735 case CHIP_HAWAII:
736 case CHIP_FIJI:
737 case CHIP_VEGAM:
738 raster_config = 0x3a00161a;
739 raster_config_1 = 0x0000002e;
740 break;
741 default:
742 fprintf(stderr,
743 "ac: Unknown GPU, using 0 for raster_config\n");
744 raster_config = 0x00000000;
745 raster_config_1 = 0x00000000;
746 break;
747 }
748
749 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
750 * This decreases performance by up to 50% when the RB is the bottleneck.
751 */
752 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
753 raster_config = 0x00000000;
754
755 /* Fiji: Old kernels have incorrect tiling config. This decreases
756 * RB performance by 25%. (it disables 1 RB in the second packer)
757 */
758 if (info->family == CHIP_FIJI &&
759 info->cik_macrotile_mode_array[0] == 0x000000e8) {
760 raster_config = 0x16000012;
761 raster_config_1 = 0x0000002a;
762 }
763
764 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
765 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
766
767 /* I don't know how to calculate this, though this is probably a good guess. */
768 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
769
770 *raster_config_p = raster_config;
771 *raster_config_1_p = raster_config_1;
772 if (se_tile_repeat_p)
773 *se_tile_repeat_p = se_tile_repeat;
774 }
775
776 void
777 ac_get_harvested_configs(struct radeon_info *info,
778 unsigned raster_config,
779 unsigned *cik_raster_config_1_p,
780 unsigned *raster_config_se)
781 {
782 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
783 unsigned num_se = MAX2(info->max_se, 1);
784 unsigned rb_mask = info->enabled_rb_mask;
785 unsigned num_rb = MIN2(info->num_render_backends, 16);
786 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
787 unsigned rb_per_se = num_rb / num_se;
788 unsigned se_mask[4];
789 unsigned se;
790
791 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
792 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
793 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
794 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
795
796 assert(num_se == 1 || num_se == 2 || num_se == 4);
797 assert(sh_per_se == 1 || sh_per_se == 2);
798 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
799
800
801 if (info->chip_class >= GFX7) {
802 unsigned raster_config_1 = *cik_raster_config_1_p;
803 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
804 (!se_mask[2] && !se_mask[3]))) {
805 raster_config_1 &= C_028354_SE_PAIR_MAP;
806
807 if (!se_mask[0] && !se_mask[1]) {
808 raster_config_1 |=
809 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
810 } else {
811 raster_config_1 |=
812 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
813 }
814 *cik_raster_config_1_p = raster_config_1;
815 }
816 }
817
818 for (se = 0; se < num_se; se++) {
819 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
820 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
821 int idx = (se / 2) * 2;
822
823 raster_config_se[se] = raster_config;
824 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
825 raster_config_se[se] &= C_028350_SE_MAP;
826
827 if (!se_mask[idx]) {
828 raster_config_se[se] |=
829 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
830 } else {
831 raster_config_se[se] |=
832 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
833 }
834 }
835
836 pkr0_mask &= rb_mask;
837 pkr1_mask &= rb_mask;
838 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
839 raster_config_se[se] &= C_028350_PKR_MAP;
840
841 if (!pkr0_mask) {
842 raster_config_se[se] |=
843 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
844 } else {
845 raster_config_se[se] |=
846 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
847 }
848 }
849
850 if (rb_per_se >= 2) {
851 unsigned rb0_mask = 1 << (se * rb_per_se);
852 unsigned rb1_mask = rb0_mask << 1;
853
854 rb0_mask &= rb_mask;
855 rb1_mask &= rb_mask;
856 if (!rb0_mask || !rb1_mask) {
857 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
858
859 if (!rb0_mask) {
860 raster_config_se[se] |=
861 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
862 } else {
863 raster_config_se[se] |=
864 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
865 }
866 }
867
868 if (rb_per_se > 2) {
869 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
870 rb1_mask = rb0_mask << 1;
871 rb0_mask &= rb_mask;
872 rb1_mask &= rb_mask;
873 if (!rb0_mask || !rb1_mask) {
874 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
875
876 if (!rb0_mask) {
877 raster_config_se[se] |=
878 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
879 } else {
880 raster_config_se[se] |=
881 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
882 }
883 }
884 }
885 }
886 }
887 }