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ac: add cpdma_prefetch_writes_memory to ac_gpu_info
[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "sid.h"
28
29 #include "util/macros.h"
30 #include "util/u_math.h"
31
32 #include <stdio.h>
33
34 #include <xf86drm.h>
35 #include <amdgpu_drm.h>
36
37 #include <amdgpu.h>
38
39 #define CIK_TILE_MODE_COLOR_2D 14
40
41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
42 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
56
57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
58 {
59 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
60
61 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
62 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
63 return 2;
64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
68 return 4;
69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
76 return 8;
77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
79 return 16;
80 default:
81 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
82 assert(!"this should never occur");
83 return 2;
84 }
85 }
86
87 static bool has_syncobj(int fd)
88 {
89 uint64_t value;
90 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
91 return false;
92 return value ? true : false;
93 }
94
95 bool ac_query_gpu_info(int fd, void *dev_p,
96 struct radeon_info *info,
97 struct amdgpu_gpu_info *amdinfo)
98 {
99 struct drm_amdgpu_info_device device_info = {};
100 struct amdgpu_buffer_size_alignments alignment_info = {};
101 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
102 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
103 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
104 struct amdgpu_gds_resource_info gds = {};
105 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
106 int r, i, j;
107 amdgpu_device_handle dev = dev_p;
108 drmDevicePtr devinfo;
109
110 /* Get PCI info. */
111 r = drmGetDevice2(fd, 0, &devinfo);
112 if (r) {
113 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
114 return false;
115 }
116 info->pci_domain = devinfo->businfo.pci->domain;
117 info->pci_bus = devinfo->businfo.pci->bus;
118 info->pci_dev = devinfo->businfo.pci->dev;
119 info->pci_func = devinfo->businfo.pci->func;
120 drmFreeDevice(&devinfo);
121
122 assert(info->drm_major == 3);
123 info->is_amdgpu = true;
124
125 /* Query hardware and driver information. */
126 r = amdgpu_query_gpu_info(dev, amdinfo);
127 if (r) {
128 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
129 return false;
130 }
131
132 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
133 &device_info);
134 if (r) {
135 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
136 return false;
137 }
138
139 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
140 if (r) {
141 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
142 return false;
143 }
144
145 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
146 if (r) {
147 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
148 return false;
149 }
150
151 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
152 if (r) {
153 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
154 return false;
155 }
156
157 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
158 if (r) {
159 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
160 return false;
161 }
162
163 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
164 if (r) {
165 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
166 return false;
167 }
168
169 if (info->drm_minor >= 17) {
170 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
171 if (r) {
172 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
173 return false;
174 }
175 }
176
177 if (info->drm_minor >= 17) {
178 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
179 if (r) {
180 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
181 return false;
182 }
183 }
184
185 if (info->drm_minor >= 17) {
186 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
187 if (r) {
188 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
189 return false;
190 }
191 }
192
193 if (info->drm_minor >= 27) {
194 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
195 if (r) {
196 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
197 return false;
198 }
199 }
200
201 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
202 &info->me_fw_version,
203 &info->me_fw_feature);
204 if (r) {
205 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
206 return false;
207 }
208
209 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
210 &info->pfp_fw_version,
211 &info->pfp_fw_feature);
212 if (r) {
213 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
214 return false;
215 }
216
217 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
218 &info->ce_fw_version,
219 &info->ce_fw_feature);
220 if (r) {
221 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
222 return false;
223 }
224
225 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
226 &uvd_version, &uvd_feature);
227 if (r) {
228 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
229 return false;
230 }
231
232 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
233 if (r) {
234 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
235 return false;
236 }
237
238 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
239 &vce_version, &vce_feature);
240 if (r) {
241 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
242 return false;
243 }
244
245 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
246 if (r) {
247 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
248 return false;
249 }
250
251 r = amdgpu_query_gds_info(dev, &gds);
252 if (r) {
253 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
254 return false;
255 }
256
257 if (info->drm_minor >= 9) {
258 struct drm_amdgpu_memory_info meminfo = {};
259
260 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
261 if (r) {
262 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
263 return false;
264 }
265
266 /* Note: usable_heap_size values can be random and can't be relied on. */
267 info->gart_size = meminfo.gtt.total_heap_size;
268 info->vram_size = meminfo.vram.total_heap_size;
269 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
270 } else {
271 /* This is a deprecated interface, which reports usable sizes
272 * (total minus pinned), but the pinned size computation is
273 * buggy, so the values returned from these functions can be
274 * random.
275 */
276 struct amdgpu_heap_info vram, vram_vis, gtt;
277
278 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
279 if (r) {
280 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
281 return false;
282 }
283
284 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
285 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
286 &vram_vis);
287 if (r) {
288 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
289 return false;
290 }
291
292 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
293 if (r) {
294 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
295 return false;
296 }
297
298 info->gart_size = gtt.heap_size;
299 info->vram_size = vram.heap_size;
300 info->vram_vis_size = vram_vis.heap_size;
301 }
302
303 /* Set chip identification. */
304 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
305 info->vce_harvest_config = amdinfo->vce_harvest_config;
306
307 switch (info->pci_id) {
308 #define CHIPSET(pci_id, cfamily) \
309 case pci_id: \
310 info->family = CHIP_##cfamily; \
311 info->name = #cfamily; \
312 break;
313 #include "pci_ids/radeonsi_pci_ids.h"
314 #undef CHIPSET
315
316 default:
317 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
318 return false;
319 }
320
321 /* Raven2 uses the same PCI IDs as Raven1, but different revision IDs. */
322 if (info->family == CHIP_RAVEN && amdinfo->chip_rev >= 0x8) {
323 info->family = CHIP_RAVEN2;
324 info->name = "RAVEN2";
325 }
326
327 if (info->family >= CHIP_NAVI10)
328 info->chip_class = GFX10;
329 else if (info->family >= CHIP_VEGA10)
330 info->chip_class = GFX9;
331 else if (info->family >= CHIP_TONGA)
332 info->chip_class = GFX8;
333 else if (info->family >= CHIP_BONAIRE)
334 info->chip_class = GFX7;
335 else if (info->family >= CHIP_TAHITI)
336 info->chip_class = GFX6;
337 else {
338 fprintf(stderr, "amdgpu: Unknown family.\n");
339 return false;
340 }
341
342 info->family_id = amdinfo->family_id;
343 info->chip_external_rev = amdinfo->chip_external_rev;
344 info->marketing_name = amdgpu_get_marketing_name(dev);
345 info->is_pro_graphics = info->marketing_name &&
346 (!strcmp(info->marketing_name, "Pro") ||
347 !strcmp(info->marketing_name, "PRO") ||
348 !strcmp(info->marketing_name, "Frontier"));
349
350 /* Set which chips have dedicated VRAM. */
351 info->has_dedicated_vram =
352 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
353
354 /* The kernel can split large buffers in VRAM but not in GTT, so large
355 * allocations can fail or cause buffer movement failures in the kernel.
356 */
357 if (info->has_dedicated_vram)
358 info->max_alloc_size = info->vram_size * 0.8;
359 else
360 info->max_alloc_size = info->gart_size * 0.7;
361
362 /* Set hardware information. */
363 info->gds_size = gds.gds_total_size;
364 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
365 /* convert the shader clock from KHz to MHz */
366 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
367 info->num_tcc_blocks = device_info.num_tcc_blocks;
368 info->max_se = amdinfo->num_shader_engines;
369 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
370 info->has_hw_decode =
371 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
372 (vcn_jpeg.available_rings != 0);
373 info->uvd_fw_version =
374 uvd.available_rings ? uvd_version : 0;
375 info->vce_fw_version =
376 vce.available_rings ? vce_version : 0;
377 info->uvd_enc_supported =
378 uvd_enc.available_rings ? true : false;
379 info->has_userptr = true;
380 info->has_syncobj = has_syncobj(fd);
381 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
382 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
383 info->has_ctx_priority = info->drm_minor >= 22;
384 info->has_local_buffers = info->drm_minor >= 20;
385 info->kernel_flushes_hdp_before_ib = true;
386 info->htile_cmask_support_1d_tiling = true;
387 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
388 info->has_bo_metadata = true;
389 info->has_gpu_reset_status_query = true;
390 info->has_eqaa_surface_allocator = true;
391 info->has_format_bc1_through_bc7 = true;
392 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
393 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
394 info->drm_minor >= 2;
395 info->has_indirect_compute_dispatch = true;
396 /* GFX6 doesn't support unaligned loads. */
397 info->has_unaligned_shader_loads = info->chip_class != GFX6;
398 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
399 * these faults are mitigated in software.
400 * Disable sparse mappings on GFX9 due to hangs.
401 */
402 info->has_sparse_vm_mappings =
403 info->chip_class >= GFX7 && info->chip_class <= GFX8 &&
404 info->drm_minor >= 13;
405 info->has_2d_tiling = true;
406 info->has_read_registers_query = true;
407 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
408
409 info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
410 info->num_render_backends = amdinfo->rb_pipes;
411 /* The value returned by the kernel driver was wrong. */
412 if (info->family == CHIP_KAVERI)
413 info->num_render_backends = 2;
414
415 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
416 if (!info->clock_crystal_freq) {
417 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
418 info->clock_crystal_freq = 1;
419 }
420 if (info->chip_class >= GFX10) {
421 info->tcc_cache_line_size = 128;
422 } else {
423 info->tcc_cache_line_size = 64;
424 }
425 info->gb_addr_config = amdinfo->gb_addr_cfg;
426 if (info->chip_class == GFX9) {
427 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
428 info->pipe_interleave_bytes =
429 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
430 } else {
431 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
432 info->pipe_interleave_bytes =
433 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
434 }
435 info->r600_has_virtual_memory = true;
436
437 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
438 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
439
440 info->has_graphics = gfx.available_rings > 0;
441 info->num_sdma_rings = util_bitcount(dma.available_rings);
442 info->num_compute_rings = util_bitcount(compute.available_rings);
443
444 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
445 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
446 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
447 */
448 info->has_clear_state = info->chip_class >= GFX7;
449
450 info->has_distributed_tess = info->chip_class >= GFX8 &&
451 info->max_se >= 2;
452
453 info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
454 info->family == CHIP_RENOIR ||
455 info->chip_class >= GFX10;
456
457 info->has_rbplus = info->family == CHIP_STONEY ||
458 info->chip_class >= GFX9;
459
460 info->has_out_of_order_rast = info->chip_class >= GFX8 &&
461 info->max_se >= 2;
462
463 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
464 info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
465 (info->chip_class >= GFX8 &&
466 info->me_fw_feature >= 41);
467
468 info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
469
470 /* Get the number of good compute units. */
471 info->num_good_compute_units = 0;
472 for (i = 0; i < info->max_se; i++)
473 for (j = 0; j < info->max_sh_per_se; j++)
474 info->num_good_compute_units +=
475 util_bitcount(amdinfo->cu_bitmap[i][j]);
476 info->num_good_cu_per_sh = info->num_good_compute_units /
477 (info->max_se * info->max_sh_per_se);
478
479 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
480 sizeof(amdinfo->gb_tile_mode));
481 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
482
483 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
484 sizeof(amdinfo->gb_macro_tile_mode));
485
486 info->pte_fragment_size = alignment_info.size_local;
487 info->gart_page_size = alignment_info.size_remote;
488
489 if (info->chip_class == GFX6)
490 info->gfx_ib_pad_with_type2 = true;
491
492 unsigned ib_align = 0;
493 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
494 ib_align = MAX2(ib_align, compute.ib_start_alignment);
495 ib_align = MAX2(ib_align, dma.ib_start_alignment);
496 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
497 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
498 ib_align = MAX2(ib_align, vce.ib_start_alignment);
499 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
500 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
501 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
502 assert(ib_align);
503 info->ib_start_alignment = ib_align;
504
505 if (info->drm_minor >= 31 &&
506 (info->family == CHIP_RAVEN ||
507 info->family == CHIP_RAVEN2 ||
508 info->family == CHIP_RENOIR)) {
509 if (info->num_render_backends == 1)
510 info->use_display_dcc_unaligned = true;
511 else
512 info->use_display_dcc_with_retile_blit = true;
513 }
514
515 info->has_gds_ordered_append = info->chip_class >= GFX7 &&
516 info->drm_minor >= 29;
517 return true;
518 }
519
520 void ac_compute_driver_uuid(char *uuid, size_t size)
521 {
522 char amd_uuid[] = "AMD-MESA-DRV";
523
524 assert(size >= sizeof(amd_uuid));
525
526 memset(uuid, 0, size);
527 strncpy(uuid, amd_uuid, size);
528 }
529
530 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
531 {
532 uint32_t *uint_uuid = (uint32_t*)uuid;
533
534 assert(size >= sizeof(uint32_t)*4);
535
536 /**
537 * Use the device info directly instead of using a sha1. GL/VK UUIDs
538 * are 16 byte vs 20 byte for sha1, and the truncation that would be
539 * required would get rid of part of the little entropy we have.
540 * */
541 memset(uuid, 0, size);
542 uint_uuid[0] = info->pci_domain;
543 uint_uuid[1] = info->pci_bus;
544 uint_uuid[2] = info->pci_dev;
545 uint_uuid[3] = info->pci_func;
546 }
547
548 void ac_print_gpu_info(struct radeon_info *info)
549 {
550 printf("Device info:\n");
551 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
552 info->pci_domain, info->pci_bus,
553 info->pci_dev, info->pci_func);
554 printf(" pci_id = 0x%x\n", info->pci_id);
555 printf(" family = %i\n", info->family);
556 printf(" chip_class = %i\n", info->chip_class);
557 printf(" chip_external_rev = %i\n", info->chip_external_rev);
558 printf(" num_compute_rings = %u\n", info->num_compute_rings);
559 printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
560 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
561 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
562
563 printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
564 printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
565
566 printf("Memory info:\n");
567 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
568 printf(" gart_page_size = %u\n", info->gart_page_size);
569 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
570 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
571 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
572 printf(" gds_size = %u kB\n", info->gds_size / 1024);
573 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
574 printf(" max_alloc_size = %i MB\n",
575 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
576 printf(" min_alloc_size = %u\n", info->min_alloc_size);
577 printf(" address32_hi = %u\n", info->address32_hi);
578 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
579
580 printf("CP info:\n");
581 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
582 printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
583 printf(" me_fw_version = %i\n", info->me_fw_version);
584 printf(" me_fw_feature = %i\n", info->me_fw_feature);
585 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
586 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
587 printf(" ce_fw_version = %i\n", info->ce_fw_version);
588 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
589
590 printf("Multimedia info:\n");
591 printf(" has_hw_decode = %u\n", info->has_hw_decode);
592 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
593 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
594 printf(" vce_fw_version = %u\n", info->vce_fw_version);
595 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
596
597 printf("Kernel & winsys capabilities:\n");
598 printf(" drm = %i.%i.%i\n", info->drm_major,
599 info->drm_minor, info->drm_patchlevel);
600 printf(" has_userptr = %i\n", info->has_userptr);
601 printf(" has_syncobj = %u\n", info->has_syncobj);
602 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
603 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
604 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
605 printf(" has_local_buffers = %u\n", info->has_local_buffers);
606 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
607 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
608 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
609 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
610 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
611 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
612 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
613 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
614 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
615 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
616 printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
617 printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
618 printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
619 printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
620 printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
621
622 printf("Shader core info:\n");
623 printf(" max_shader_clock = %i\n", info->max_shader_clock);
624 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
625 printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh);
626 printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
627 printf(" max_se = %i\n", info->max_se);
628 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
629
630 printf("Render backend info:\n");
631 printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
632 printf(" num_render_backends = %i\n", info->num_render_backends);
633 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
634 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
635 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
636 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
637
638 printf("GB_ADDR_CONFIG:\n");
639 if (info->chip_class >= GFX9) {
640 printf(" num_pipes = %u\n",
641 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
642 printf(" pipe_interleave_size = %u\n",
643 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
644 printf(" max_compressed_frags = %u\n",
645 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
646 printf(" bank_interleave_size = %u\n",
647 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
648 printf(" num_banks = %u\n",
649 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
650 printf(" shader_engine_tile_size = %u\n",
651 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
652 printf(" num_shader_engines = %u\n",
653 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
654 printf(" num_gpus = %u (raw)\n",
655 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
656 printf(" multi_gpu_tile_size = %u (raw)\n",
657 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
658 printf(" num_rb_per_se = %u\n",
659 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
660 printf(" row_size = %u\n",
661 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
662 printf(" num_lower_pipes = %u (raw)\n",
663 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
664 printf(" se_enable = %u (raw)\n",
665 G_0098F8_SE_ENABLE(info->gb_addr_config));
666 } else {
667 printf(" num_pipes = %u\n",
668 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
669 printf(" pipe_interleave_size = %u\n",
670 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
671 printf(" bank_interleave_size = %u\n",
672 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
673 printf(" num_shader_engines = %u\n",
674 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
675 printf(" shader_engine_tile_size = %u\n",
676 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
677 printf(" num_gpus = %u (raw)\n",
678 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
679 printf(" multi_gpu_tile_size = %u (raw)\n",
680 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
681 printf(" row_size = %u\n",
682 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
683 printf(" num_lower_pipes = %u (raw)\n",
684 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
685 }
686 }
687
688 int
689 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
690 {
691 if (chip_class >= GFX9)
692 return -1;
693
694 switch (family) {
695 case CHIP_OLAND:
696 case CHIP_HAINAN:
697 case CHIP_KAVERI:
698 case CHIP_KABINI:
699 case CHIP_ICELAND:
700 case CHIP_CARRIZO:
701 case CHIP_STONEY:
702 return 16;
703 case CHIP_TAHITI:
704 case CHIP_PITCAIRN:
705 case CHIP_VERDE:
706 case CHIP_BONAIRE:
707 case CHIP_HAWAII:
708 case CHIP_TONGA:
709 case CHIP_FIJI:
710 case CHIP_POLARIS10:
711 case CHIP_POLARIS11:
712 case CHIP_POLARIS12:
713 case CHIP_VEGAM:
714 return 32;
715 default:
716 unreachable("Unknown GPU");
717 }
718 }
719
720 void
721 ac_get_raster_config(struct radeon_info *info,
722 uint32_t *raster_config_p,
723 uint32_t *raster_config_1_p,
724 uint32_t *se_tile_repeat_p)
725 {
726 unsigned raster_config, raster_config_1, se_tile_repeat;
727
728 switch (info->family) {
729 /* 1 SE / 1 RB */
730 case CHIP_HAINAN:
731 case CHIP_KABINI:
732 case CHIP_STONEY:
733 raster_config = 0x00000000;
734 raster_config_1 = 0x00000000;
735 break;
736 /* 1 SE / 4 RBs */
737 case CHIP_VERDE:
738 raster_config = 0x0000124a;
739 raster_config_1 = 0x00000000;
740 break;
741 /* 1 SE / 2 RBs (Oland is special) */
742 case CHIP_OLAND:
743 raster_config = 0x00000082;
744 raster_config_1 = 0x00000000;
745 break;
746 /* 1 SE / 2 RBs */
747 case CHIP_KAVERI:
748 case CHIP_ICELAND:
749 case CHIP_CARRIZO:
750 raster_config = 0x00000002;
751 raster_config_1 = 0x00000000;
752 break;
753 /* 2 SEs / 4 RBs */
754 case CHIP_BONAIRE:
755 case CHIP_POLARIS11:
756 case CHIP_POLARIS12:
757 raster_config = 0x16000012;
758 raster_config_1 = 0x00000000;
759 break;
760 /* 2 SEs / 8 RBs */
761 case CHIP_TAHITI:
762 case CHIP_PITCAIRN:
763 raster_config = 0x2a00126a;
764 raster_config_1 = 0x00000000;
765 break;
766 /* 4 SEs / 8 RBs */
767 case CHIP_TONGA:
768 case CHIP_POLARIS10:
769 raster_config = 0x16000012;
770 raster_config_1 = 0x0000002a;
771 break;
772 /* 4 SEs / 16 RBs */
773 case CHIP_HAWAII:
774 case CHIP_FIJI:
775 case CHIP_VEGAM:
776 raster_config = 0x3a00161a;
777 raster_config_1 = 0x0000002e;
778 break;
779 default:
780 fprintf(stderr,
781 "ac: Unknown GPU, using 0 for raster_config\n");
782 raster_config = 0x00000000;
783 raster_config_1 = 0x00000000;
784 break;
785 }
786
787 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
788 * This decreases performance by up to 50% when the RB is the bottleneck.
789 */
790 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
791 raster_config = 0x00000000;
792
793 /* Fiji: Old kernels have incorrect tiling config. This decreases
794 * RB performance by 25%. (it disables 1 RB in the second packer)
795 */
796 if (info->family == CHIP_FIJI &&
797 info->cik_macrotile_mode_array[0] == 0x000000e8) {
798 raster_config = 0x16000012;
799 raster_config_1 = 0x0000002a;
800 }
801
802 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
803 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
804
805 /* I don't know how to calculate this, though this is probably a good guess. */
806 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
807
808 *raster_config_p = raster_config;
809 *raster_config_1_p = raster_config_1;
810 if (se_tile_repeat_p)
811 *se_tile_repeat_p = se_tile_repeat;
812 }
813
814 void
815 ac_get_harvested_configs(struct radeon_info *info,
816 unsigned raster_config,
817 unsigned *cik_raster_config_1_p,
818 unsigned *raster_config_se)
819 {
820 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
821 unsigned num_se = MAX2(info->max_se, 1);
822 unsigned rb_mask = info->enabled_rb_mask;
823 unsigned num_rb = MIN2(info->num_render_backends, 16);
824 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
825 unsigned rb_per_se = num_rb / num_se;
826 unsigned se_mask[4];
827 unsigned se;
828
829 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
830 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
831 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
832 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
833
834 assert(num_se == 1 || num_se == 2 || num_se == 4);
835 assert(sh_per_se == 1 || sh_per_se == 2);
836 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
837
838
839 if (info->chip_class >= GFX7) {
840 unsigned raster_config_1 = *cik_raster_config_1_p;
841 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
842 (!se_mask[2] && !se_mask[3]))) {
843 raster_config_1 &= C_028354_SE_PAIR_MAP;
844
845 if (!se_mask[0] && !se_mask[1]) {
846 raster_config_1 |=
847 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
848 } else {
849 raster_config_1 |=
850 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
851 }
852 *cik_raster_config_1_p = raster_config_1;
853 }
854 }
855
856 for (se = 0; se < num_se; se++) {
857 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
858 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
859 int idx = (se / 2) * 2;
860
861 raster_config_se[se] = raster_config;
862 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
863 raster_config_se[se] &= C_028350_SE_MAP;
864
865 if (!se_mask[idx]) {
866 raster_config_se[se] |=
867 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
868 } else {
869 raster_config_se[se] |=
870 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
871 }
872 }
873
874 pkr0_mask &= rb_mask;
875 pkr1_mask &= rb_mask;
876 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
877 raster_config_se[se] &= C_028350_PKR_MAP;
878
879 if (!pkr0_mask) {
880 raster_config_se[se] |=
881 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
882 } else {
883 raster_config_se[se] |=
884 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
885 }
886 }
887
888 if (rb_per_se >= 2) {
889 unsigned rb0_mask = 1 << (se * rb_per_se);
890 unsigned rb1_mask = rb0_mask << 1;
891
892 rb0_mask &= rb_mask;
893 rb1_mask &= rb_mask;
894 if (!rb0_mask || !rb1_mask) {
895 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
896
897 if (!rb0_mask) {
898 raster_config_se[se] |=
899 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
900 } else {
901 raster_config_se[se] |=
902 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
903 }
904 }
905
906 if (rb_per_se > 2) {
907 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
908 rb1_mask = rb0_mask << 1;
909 rb0_mask &= rb_mask;
910 rb1_mask &= rb_mask;
911 if (!rb0_mask || !rb1_mask) {
912 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
913
914 if (!rb0_mask) {
915 raster_config_se[se] |=
916 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
917 } else {
918 raster_config_se[se] |=
919 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
920 }
921 }
922 }
923 }
924 }
925 }
926
927 unsigned ac_get_compute_resource_limits(struct radeon_info *info,
928 unsigned waves_per_threadgroup,
929 unsigned max_waves_per_sh,
930 unsigned threadgroups_per_cu)
931 {
932 unsigned compute_resource_limits =
933 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
934
935 if (info->chip_class >= GFX7) {
936 unsigned num_cu_per_se = info->num_good_compute_units /
937 info->max_se;
938
939 /* Force even distribution on all SIMDs in CU if the workgroup
940 * size is 64. This has shown some good improvements if # of CUs
941 * per SE is not a multiple of 4.
942 */
943 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
944 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
945
946 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
947 compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
948 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
949 } else {
950 /* GFX6 */
951 if (max_waves_per_sh) {
952 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
953 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
954 }
955 }
956 return compute_resource_limits;
957 }