src/amd/common/ac_gpu_info.c

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #include "ac_gpu_info.h"
  27 #include "sid.h"
  28 #include "gfx9d.h"
  29
  30 #include "util/u_math.h"
  31
  32 #include <stdio.h>
  33
  34 #include <xf86drm.h>
  35 #include <amdgpu_drm.h>
  36
  37 #include <amdgpu.h>
  38
  39 #define CIK_TILE_MODE_COLOR_2D                  14
  40
  41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  42 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  43 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  44 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  45 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  46 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  47 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  48 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  54 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  55 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  56
  57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  58 {
  59    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  60
  61    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  62    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  63        return 2;
  64    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  65    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  66    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  67    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  68        return 4;
  69    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  70    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  71    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  72    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  73    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  74    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  75    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  76        return 8;
  77    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  78    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  79        return 16;
  80    default:
  81        fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
  82        assert(!"this should never occur");
  83        return 2;
  84    }
  85 }
  86
  87 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
  88                        struct radeon_info *info,
  89                        struct amdgpu_gpu_info *amdinfo)
  90 {
  91         struct amdgpu_buffer_size_alignments alignment_info = {};
  92         struct amdgpu_heap_info vram, vram_vis, gtt;
  93         struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, vce = {}, vcn_dec = {};
  94         uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
  95         uint32_t unused_feature;
  96         int r, i, j;
  97         drmDevicePtr devinfo;
  98
  99         /* Get PCI info. */
 100         r = drmGetDevice2(fd, 0, &devinfo);
 101         if (r) {
 102                 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
 103                 return false;
 104         }
 105         info->pci_domain = devinfo->businfo.pci->domain;
 106         info->pci_bus = devinfo->businfo.pci->bus;
 107         info->pci_dev = devinfo->businfo.pci->dev;
 108         info->pci_func = devinfo->businfo.pci->func;
 109         drmFreeDevice(&devinfo);
 110
 111         /* Query hardware and driver information. */
 112         r = amdgpu_query_gpu_info(dev, amdinfo);
 113         if (r) {
 114                 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 115                 return false;
 116         }
 117
 118         r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
 119         if (r) {
 120                 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 121                 return false;
 122         }
 123
 124         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 125         if (r) {
 126                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 127                 return false;
 128         }
 129
 130         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
 131                                 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 132                                 &vram_vis);
 133         if (r) {
 134                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
 135                 return false;
 136         }
 137
 138         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 139         if (r) {
 140                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 141                 return false;
 142         }
 143
 144         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
 145         if (r) {
 146                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 147                 return false;
 148         }
 149
 150         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
 151         if (r) {
 152                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
 153                 return false;
 154         }
 155
 156         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 157         if (r) {
 158                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 159                 return false;
 160         }
 161
 162         if (info->drm_major == 3 && info->drm_minor >= 17) {
 163                 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
 164                 if (r) {
 165                         fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
 166                         return false;
 167                 }
 168         }
 169
 170         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
 171                                         &info->me_fw_version, &unused_feature);
 172         if (r) {
 173                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
 174                 return false;
 175         }
 176
 177         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
 178                                         &info->pfp_fw_version, &unused_feature);
 179         if (r) {
 180                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
 181                 return false;
 182         }
 183
 184         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
 185                                         &info->ce_fw_version, &unused_feature);
 186         if (r) {
 187                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
 188                 return false;
 189         }
 190
 191         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
 192                                         &uvd_version, &uvd_feature);
 193         if (r) {
 194                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
 195                 return false;
 196         }
 197
 198         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
 199         if (r) {
 200                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 201                 return false;
 202         }
 203
 204         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
 205                                         &vce_version, &vce_feature);
 206         if (r) {
 207                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 208                 return false;
 209         }
 210
 211         /* Set chip identification. */
 212         info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
 213         info->vce_harvest_config = amdinfo->vce_harvest_config;
 214
 215         switch (info->pci_id) {
 216 #define CHIPSET(pci_id, name, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
 217 #include "pci_ids/radeonsi_pci_ids.h"
 218 #undef CHIPSET
 219
 220         default:
 221                 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 222                 return false;
 223         }
 224
 225         if (info->family >= CHIP_VEGA10)
 226                 info->chip_class = GFX9;
 227         else if (info->family >= CHIP_TONGA)
 228                 info->chip_class = VI;
 229         else if (info->family >= CHIP_BONAIRE)
 230                 info->chip_class = CIK;
 231         else if (info->family >= CHIP_TAHITI)
 232                 info->chip_class = SI;
 233         else {
 234                 fprintf(stderr, "amdgpu: Unknown family.\n");
 235                 return false;
 236         }
 237
 238         /* Set which chips have dedicated VRAM. */
 239         info->has_dedicated_vram =
 240                 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
 241
 242         /* Set hardware information. */
 243         info->gart_size = gtt.heap_size;
 244         info->vram_size = vram.heap_size;
 245         info->vram_vis_size = vram_vis.heap_size;
 246         /* The kernel can split large buffers in VRAM but not in GTT, so large
 247          * allocations can fail or cause buffer movement failures in the kernel.
 248          */
 249         info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 0.7);
 250         /* convert the shader clock from KHz to MHz */
 251         info->max_shader_clock = amdinfo->max_engine_clk / 1000;
 252         info->max_se = amdinfo->num_shader_engines;
 253         info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
 254         info->has_hw_decode =
 255                 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
 256         info->uvd_fw_version =
 257                 uvd.available_rings ? uvd_version : 0;
 258         info->vce_fw_version =
 259                 vce.available_rings ? vce_version : 0;
 260         info->has_userptr = true;
 261         info->num_render_backends = amdinfo->rb_pipes;
 262         info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 263         if (!info->clock_crystal_freq) {
 264                 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
 265                 info->clock_crystal_freq = 1;
 266         }
 267         info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 268         if (info->chip_class == GFX9) {
 269                 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
 270                 info->pipe_interleave_bytes =
 271                         256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
 272         } else {
 273                 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
 274                 info->pipe_interleave_bytes =
 275                         256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
 276         }
 277         info->has_virtual_memory = true;
 278
 279         assert(util_is_power_of_two(dma.available_rings + 1));
 280         assert(util_is_power_of_two(compute.available_rings + 1));
 281
 282         info->num_sdma_rings = util_bitcount(dma.available_rings);
 283         info->num_compute_rings = util_bitcount(compute.available_rings);
 284
 285         /* Get the number of good compute units. */
 286         info->num_good_compute_units = 0;
 287         for (i = 0; i < info->max_se; i++)
 288                 for (j = 0; j < info->max_sh_per_se; j++)
 289                         info->num_good_compute_units +=
 290                                 util_bitcount(amdinfo->cu_bitmap[i][j]);
 291
 292         memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
 293                 sizeof(amdinfo->gb_tile_mode));
 294         info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
 295
 296         memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
 297                 sizeof(amdinfo->gb_macro_tile_mode));
 298
 299         info->pte_fragment_size = alignment_info.size_local;
 300         info->gart_page_size = alignment_info.size_remote;
 301
 302         if (info->chip_class == SI)
 303                 info->gfx_ib_pad_with_type2 = TRUE;
 304
 305         return true;
 306 }
 307