2 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
26 #include "ac_gpu_info.h"
30 #include "util/u_math.h"
35 #include <amdgpu_drm.h>
39 #define CIK_TILE_MODE_COLOR_2D 14
41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
42 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info
*info
)
59 unsigned mode2d
= info
->gb_tile_mode
[CIK_TILE_MODE_COLOR_2D
];
61 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d
)) {
62 case CIK__PIPE_CONFIG__ADDR_SURF_P2
:
64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16
:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16
:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32
:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32
:
69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16
:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16
:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16
:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16
:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16
:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32
:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32
:
77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16
:
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16
:
81 fprintf(stderr
, "Invalid CIK pipe configuration, assuming P2\n");
82 assert(!"this should never occur");
87 static bool has_syncobj(int fd
)
90 if (drmGetCap(fd
, DRM_CAP_SYNCOBJ
, &value
))
92 return value
? true : false;
95 bool ac_query_gpu_info(int fd
, amdgpu_device_handle dev
,
96 struct radeon_info
*info
,
97 struct amdgpu_gpu_info
*amdinfo
)
99 struct amdgpu_buffer_size_alignments alignment_info
= {};
100 struct amdgpu_heap_info vram
, vram_vis
, gtt
;
101 struct drm_amdgpu_info_hw_ip dma
= {}, compute
= {}, uvd
= {};
102 struct drm_amdgpu_info_hw_ip uvd_enc
= {}, vce
= {}, vcn_dec
= {};
103 struct drm_amdgpu_info_hw_ip vcn_enc
= {}, gfx
= {};
104 struct amdgpu_gds_resource_info gds
= {};
105 uint32_t vce_version
= 0, vce_feature
= 0, uvd_version
= 0, uvd_feature
= 0;
107 drmDevicePtr devinfo
;
110 r
= drmGetDevice2(fd
, 0, &devinfo
);
112 fprintf(stderr
, "amdgpu: drmGetDevice2 failed.\n");
115 info
->pci_domain
= devinfo
->businfo
.pci
->domain
;
116 info
->pci_bus
= devinfo
->businfo
.pci
->bus
;
117 info
->pci_dev
= devinfo
->businfo
.pci
->dev
;
118 info
->pci_func
= devinfo
->businfo
.pci
->func
;
119 drmFreeDevice(&devinfo
);
121 /* Query hardware and driver information. */
122 r
= amdgpu_query_gpu_info(dev
, amdinfo
);
124 fprintf(stderr
, "amdgpu: amdgpu_query_gpu_info failed.\n");
128 r
= amdgpu_query_buffer_size_alignment(dev
, &alignment_info
);
130 fprintf(stderr
, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
134 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_VRAM
, 0, &vram
);
136 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
140 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_VRAM
,
141 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
,
144 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
148 r
= amdgpu_query_heap_info(dev
, AMDGPU_GEM_DOMAIN_GTT
, 0, >t
);
150 fprintf(stderr
, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
154 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_DMA
, 0, &dma
);
156 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
160 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_GFX
, 0, &gfx
);
162 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
166 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_COMPUTE
, 0, &compute
);
168 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
172 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_UVD
, 0, &uvd
);
174 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
178 if (info
->drm_major
== 3 && info
->drm_minor
>= 17) {
179 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_UVD_ENC
, 0, &uvd_enc
);
181 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
186 if (info
->drm_major
== 3 && info
->drm_minor
>= 17) {
187 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCN_DEC
, 0, &vcn_dec
);
189 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
194 if (info
->drm_major
== 3 && info
->drm_minor
>= 17) {
195 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCN_ENC
, 0, &vcn_enc
);
197 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
202 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_ME
, 0, 0,
203 &info
->me_fw_version
,
204 &info
->me_fw_feature
);
206 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
210 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_PFP
, 0, 0,
211 &info
->pfp_fw_version
,
212 &info
->pfp_fw_feature
);
214 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
218 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_GFX_CE
, 0, 0,
219 &info
->ce_fw_version
,
220 &info
->ce_fw_feature
);
222 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
226 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_UVD
, 0, 0,
227 &uvd_version
, &uvd_feature
);
229 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
233 r
= amdgpu_query_hw_ip_info(dev
, AMDGPU_HW_IP_VCE
, 0, &vce
);
235 fprintf(stderr
, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
239 r
= amdgpu_query_firmware_version(dev
, AMDGPU_INFO_FW_VCE
, 0, 0,
240 &vce_version
, &vce_feature
);
242 fprintf(stderr
, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
246 r
= amdgpu_query_sw_info(dev
, amdgpu_sw_info_address32_hi
, &info
->address32_hi
);
248 fprintf(stderr
, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
252 r
= amdgpu_query_gds_info(dev
, &gds
);
254 fprintf(stderr
, "amdgpu: amdgpu_query_gds_info failed.\n");
258 /* Set chip identification. */
259 info
->pci_id
= amdinfo
->asic_id
; /* TODO: is this correct? */
260 info
->vce_harvest_config
= amdinfo
->vce_harvest_config
;
262 switch (info
->pci_id
) {
263 #define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
264 #include "pci_ids/radeonsi_pci_ids.h"
268 fprintf(stderr
, "amdgpu: Invalid PCI ID.\n");
272 if (info
->family
>= CHIP_VEGA10
)
273 info
->chip_class
= GFX9
;
274 else if (info
->family
>= CHIP_TONGA
)
275 info
->chip_class
= VI
;
276 else if (info
->family
>= CHIP_BONAIRE
)
277 info
->chip_class
= CIK
;
278 else if (info
->family
>= CHIP_TAHITI
)
279 info
->chip_class
= SI
;
281 fprintf(stderr
, "amdgpu: Unknown family.\n");
285 /* Set which chips have dedicated VRAM. */
286 info
->has_dedicated_vram
=
287 !(amdinfo
->ids_flags
& AMDGPU_IDS_FLAGS_FUSION
);
289 /* Set hardware information. */
290 info
->gart_size
= gtt
.heap_size
;
291 info
->vram_size
= vram
.heap_size
;
292 info
->vram_vis_size
= vram_vis
.heap_size
;
293 info
->gds_size
= gds
.gds_total_size
;
294 info
->gds_gfx_partition_size
= gds
.gds_gfx_partition_size
;
295 /* The kernel can split large buffers in VRAM but not in GTT, so large
296 * allocations can fail or cause buffer movement failures in the kernel.
298 info
->max_alloc_size
= MIN2(info
->vram_size
* 0.9, info
->gart_size
* 0.7);
299 /* convert the shader clock from KHz to MHz */
300 info
->max_shader_clock
= amdinfo
->max_engine_clk
/ 1000;
301 info
->max_se
= amdinfo
->num_shader_engines
;
302 info
->max_sh_per_se
= amdinfo
->num_shader_arrays_per_engine
;
303 info
->has_hw_decode
=
304 (uvd
.available_rings
!= 0) || (vcn_dec
.available_rings
!= 0);
305 info
->uvd_fw_version
=
306 uvd
.available_rings
? uvd_version
: 0;
307 info
->vce_fw_version
=
308 vce
.available_rings
? vce_version
: 0;
309 info
->uvd_enc_supported
=
310 uvd_enc
.available_rings
? true : false;
311 info
->has_userptr
= true;
312 info
->has_syncobj
= has_syncobj(fd
);
313 info
->has_syncobj_wait_for_submit
= info
->has_syncobj
&& info
->drm_minor
>= 20;
314 info
->has_fence_to_handle
= info
->has_syncobj
&& info
->drm_minor
>= 21;
315 info
->has_ctx_priority
= info
->drm_minor
>= 22;
316 /* TODO: Enable this once the kernel handles it efficiently. */
317 info
->has_local_buffers
= info
->drm_minor
>= 20 &&
318 !info
->has_dedicated_vram
;
319 info
->kernel_flushes_hdp_before_ib
= true;
320 info
->htile_cmask_support_1d_tiling
= true;
322 info
->num_render_backends
= amdinfo
->rb_pipes
;
323 /* The value returned by the kernel driver was wrong. */
324 if (info
->family
== CHIP_KAVERI
)
325 info
->num_render_backends
= 2;
327 info
->clock_crystal_freq
= amdinfo
->gpu_counter_freq
;
328 if (!info
->clock_crystal_freq
) {
329 fprintf(stderr
, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
330 info
->clock_crystal_freq
= 1;
332 info
->tcc_cache_line_size
= 64; /* TC L2 line size on GCN */
333 info
->gb_addr_config
= amdinfo
->gb_addr_cfg
;
334 if (info
->chip_class
== GFX9
) {
335 info
->num_tile_pipes
= 1 << G_0098F8_NUM_PIPES(amdinfo
->gb_addr_cfg
);
336 info
->pipe_interleave_bytes
=
337 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo
->gb_addr_cfg
);
339 info
->num_tile_pipes
= cik_get_num_tile_pipes(amdinfo
);
340 info
->pipe_interleave_bytes
=
341 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo
->gb_addr_cfg
);
343 info
->r600_has_virtual_memory
= true;
345 assert(util_is_power_of_two_or_zero(dma
.available_rings
+ 1));
346 assert(util_is_power_of_two_or_zero(compute
.available_rings
+ 1));
348 info
->num_sdma_rings
= util_bitcount(dma
.available_rings
);
349 info
->num_compute_rings
= util_bitcount(compute
.available_rings
);
351 /* Get the number of good compute units. */
352 info
->num_good_compute_units
= 0;
353 for (i
= 0; i
< info
->max_se
; i
++)
354 for (j
= 0; j
< info
->max_sh_per_se
; j
++)
355 info
->num_good_compute_units
+=
356 util_bitcount(amdinfo
->cu_bitmap
[i
][j
]);
358 memcpy(info
->si_tile_mode_array
, amdinfo
->gb_tile_mode
,
359 sizeof(amdinfo
->gb_tile_mode
));
360 info
->enabled_rb_mask
= amdinfo
->enabled_rb_pipes_mask
;
362 memcpy(info
->cik_macrotile_mode_array
, amdinfo
->gb_macro_tile_mode
,
363 sizeof(amdinfo
->gb_macro_tile_mode
));
365 info
->pte_fragment_size
= alignment_info
.size_local
;
366 info
->gart_page_size
= alignment_info
.size_remote
;
368 if (info
->chip_class
== SI
)
369 info
->gfx_ib_pad_with_type2
= TRUE
;
371 unsigned ib_align
= 0;
372 ib_align
= MAX2(ib_align
, gfx
.ib_start_alignment
);
373 ib_align
= MAX2(ib_align
, compute
.ib_start_alignment
);
374 ib_align
= MAX2(ib_align
, dma
.ib_start_alignment
);
375 ib_align
= MAX2(ib_align
, uvd
.ib_start_alignment
);
376 ib_align
= MAX2(ib_align
, uvd_enc
.ib_start_alignment
);
377 ib_align
= MAX2(ib_align
, vce
.ib_start_alignment
);
378 ib_align
= MAX2(ib_align
, vcn_dec
.ib_start_alignment
);
379 ib_align
= MAX2(ib_align
, vcn_enc
.ib_start_alignment
);
381 info
->ib_start_alignment
= ib_align
;
386 void ac_compute_driver_uuid(char *uuid
, size_t size
)
388 char amd_uuid
[] = "AMD-MESA-DRV";
390 assert(size
>= sizeof(amd_uuid
));
392 memset(uuid
, 0, size
);
393 strncpy(uuid
, amd_uuid
, size
);
396 void ac_compute_device_uuid(struct radeon_info
*info
, char *uuid
, size_t size
)
398 uint32_t *uint_uuid
= (uint32_t*)uuid
;
400 assert(size
>= sizeof(uint32_t)*4);
403 * Use the device info directly instead of using a sha1. GL/VK UUIDs
404 * are 16 byte vs 20 byte for sha1, and the truncation that would be
405 * required would get rid of part of the little entropy we have.
407 memset(uuid
, 0, size
);
408 uint_uuid
[0] = info
->pci_domain
;
409 uint_uuid
[1] = info
->pci_bus
;
410 uint_uuid
[2] = info
->pci_dev
;
411 uint_uuid
[3] = info
->pci_func
;
414 void ac_print_gpu_info(struct radeon_info
*info
)
416 printf("Device info:\n");
417 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
418 info
->pci_domain
, info
->pci_bus
,
419 info
->pci_dev
, info
->pci_func
);
420 printf(" pci_id = 0x%x\n", info
->pci_id
);
421 printf(" family = %i\n", info
->family
);
422 printf(" chip_class = %i\n", info
->chip_class
);
423 printf(" num_compute_rings = %u\n", info
->num_compute_rings
);
424 printf(" num_sdma_rings = %i\n", info
->num_sdma_rings
);
425 printf(" clock_crystal_freq = %i\n", info
->clock_crystal_freq
);
426 printf(" tcc_cache_line_size = %u\n", info
->tcc_cache_line_size
);
428 printf("Memory info:\n");
429 printf(" pte_fragment_size = %u\n", info
->pte_fragment_size
);
430 printf(" gart_page_size = %u\n", info
->gart_page_size
);
431 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info
->gart_size
, 1024*1024));
432 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info
->vram_size
, 1024*1024));
433 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info
->vram_vis_size
, 1024*1024));
434 printf(" gds_size = %u kB\n", info
->gds_size
/ 1024);
435 printf(" gds_gfx_partition_size = %u kB\n", info
->gds_gfx_partition_size
/ 1024);
436 printf(" max_alloc_size = %i MB\n",
437 (int)DIV_ROUND_UP(info
->max_alloc_size
, 1024*1024));
438 printf(" min_alloc_size = %u\n", info
->min_alloc_size
);
439 printf(" address32_hi = %u\n", info
->address32_hi
);
440 printf(" has_dedicated_vram = %u\n", info
->has_dedicated_vram
);
442 printf("CP info:\n");
443 printf(" gfx_ib_pad_with_type2 = %i\n", info
->gfx_ib_pad_with_type2
);
444 printf(" ib_start_alignment = %u\n", info
->ib_start_alignment
);
445 printf(" me_fw_version = %i\n", info
->me_fw_version
);
446 printf(" me_fw_feature = %i\n", info
->me_fw_feature
);
447 printf(" pfp_fw_version = %i\n", info
->pfp_fw_version
);
448 printf(" pfp_fw_feature = %i\n", info
->pfp_fw_feature
);
449 printf(" ce_fw_version = %i\n", info
->ce_fw_version
);
450 printf(" ce_fw_feature = %i\n", info
->ce_fw_feature
);
452 printf("Multimedia info:\n");
453 printf(" has_hw_decode = %u\n", info
->has_hw_decode
);
454 printf(" uvd_enc_supported = %u\n", info
->uvd_enc_supported
);
455 printf(" uvd_fw_version = %u\n", info
->uvd_fw_version
);
456 printf(" vce_fw_version = %u\n", info
->vce_fw_version
);
457 printf(" vce_harvest_config = %i\n", info
->vce_harvest_config
);
459 printf("Kernel info:\n");
460 printf(" drm = %i.%i.%i\n", info
->drm_major
,
461 info
->drm_minor
, info
->drm_patchlevel
);
462 printf(" has_userptr = %i\n", info
->has_userptr
);
463 printf(" has_syncobj = %u\n", info
->has_syncobj
);
464 printf(" has_syncobj_wait_for_submit = %u\n", info
->has_syncobj_wait_for_submit
);
465 printf(" has_fence_to_handle = %u\n", info
->has_fence_to_handle
);
466 printf(" has_ctx_priority = %u\n", info
->has_ctx_priority
);
467 printf(" has_local_buffers = %u\n", info
->has_local_buffers
);
468 printf(" kernel_flushes_hdp_before_ib = %u\n", info
->kernel_flushes_hdp_before_ib
);
469 printf(" htile_cmask_support_1d_tiling = %u\n", info
->htile_cmask_support_1d_tiling
);
471 printf("Shader core info:\n");
472 printf(" max_shader_clock = %i\n", info
->max_shader_clock
);
473 printf(" num_good_compute_units = %i\n", info
->num_good_compute_units
);
474 printf(" max_se = %i\n", info
->max_se
);
475 printf(" max_sh_per_se = %i\n", info
->max_sh_per_se
);
477 printf("Render backend info:\n");
478 printf(" num_render_backends = %i\n", info
->num_render_backends
);
479 printf(" num_tile_pipes = %i\n", info
->num_tile_pipes
);
480 printf(" pipe_interleave_bytes = %i\n", info
->pipe_interleave_bytes
);
481 printf(" enabled_rb_mask = 0x%x\n", info
->enabled_rb_mask
);
482 printf(" max_alignment = %u\n", (unsigned)info
->max_alignment
);
484 printf("GB_ADDR_CONFIG:\n");
485 if (info
->chip_class
>= GFX9
) {
486 printf(" num_pipes = %u\n",
487 1 << G_0098F8_NUM_PIPES(info
->gb_addr_config
));
488 printf(" pipe_interleave_size = %u\n",
489 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info
->gb_addr_config
));
490 printf(" max_compressed_frags = %u\n",
491 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info
->gb_addr_config
));
492 printf(" bank_interleave_size = %u\n",
493 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info
->gb_addr_config
));
494 printf(" num_banks = %u\n",
495 1 << G_0098F8_NUM_BANKS(info
->gb_addr_config
));
496 printf(" shader_engine_tile_size = %u\n",
497 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info
->gb_addr_config
));
498 printf(" num_shader_engines = %u\n",
499 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info
->gb_addr_config
));
500 printf(" num_gpus = %u (raw)\n",
501 G_0098F8_NUM_GPUS_GFX9(info
->gb_addr_config
));
502 printf(" multi_gpu_tile_size = %u (raw)\n",
503 G_0098F8_MULTI_GPU_TILE_SIZE(info
->gb_addr_config
));
504 printf(" num_rb_per_se = %u\n",
505 1 << G_0098F8_NUM_RB_PER_SE(info
->gb_addr_config
));
506 printf(" row_size = %u\n",
507 1024 << G_0098F8_ROW_SIZE(info
->gb_addr_config
));
508 printf(" num_lower_pipes = %u (raw)\n",
509 G_0098F8_NUM_LOWER_PIPES(info
->gb_addr_config
));
510 printf(" se_enable = %u (raw)\n",
511 G_0098F8_SE_ENABLE(info
->gb_addr_config
));
513 printf(" num_pipes = %u\n",
514 1 << G_0098F8_NUM_PIPES(info
->gb_addr_config
));
515 printf(" pipe_interleave_size = %u\n",
516 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info
->gb_addr_config
));
517 printf(" bank_interleave_size = %u\n",
518 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info
->gb_addr_config
));
519 printf(" num_shader_engines = %u\n",
520 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info
->gb_addr_config
));
521 printf(" shader_engine_tile_size = %u\n",
522 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info
->gb_addr_config
));
523 printf(" num_gpus = %u (raw)\n",
524 G_0098F8_NUM_GPUS_GFX6(info
->gb_addr_config
));
525 printf(" multi_gpu_tile_size = %u (raw)\n",
526 G_0098F8_MULTI_GPU_TILE_SIZE(info
->gb_addr_config
));
527 printf(" row_size = %u\n",
528 1024 << G_0098F8_ROW_SIZE(info
->gb_addr_config
));
529 printf(" num_lower_pipes = %u (raw)\n",
530 G_0098F8_NUM_LOWER_PIPES(info
->gb_addr_config
));
535 ac_get_gs_table_depth(enum chip_class chip_class
, enum radeon_family family
)
537 if (chip_class
>= GFX9
)
563 unreachable("Unknown GPU");
568 ac_get_raster_config(struct radeon_info
*info
,
569 uint32_t *raster_config_p
,
570 uint32_t *raster_config_1_p
)
572 unsigned raster_config
, raster_config_1
;
574 switch (info
->family
) {
580 raster_config
= 0x00000000;
581 raster_config_1
= 0x00000000;
585 raster_config
= 0x0000124a;
586 raster_config_1
= 0x00000000;
588 /* 1 SE / 2 RBs (Oland is special) */
590 raster_config
= 0x00000082;
591 raster_config_1
= 0x00000000;
597 raster_config
= 0x00000002;
598 raster_config_1
= 0x00000000;
604 raster_config
= 0x16000012;
605 raster_config_1
= 0x00000000;
610 raster_config
= 0x2a00126a;
611 raster_config_1
= 0x00000000;
616 raster_config
= 0x16000012;
617 raster_config_1
= 0x0000002a;
623 raster_config
= 0x3a00161a;
624 raster_config_1
= 0x0000002e;
628 "ac: Unknown GPU, using 0 for raster_config\n");
629 raster_config
= 0x00000000;
630 raster_config_1
= 0x00000000;
634 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
635 * This decreases performance by up to 50% when the RB is the bottleneck.
637 if (info
->family
== CHIP_KAVERI
&& info
->drm_major
== 2)
638 raster_config
= 0x00000000;
640 /* Fiji: Old kernels have incorrect tiling config. This decreases
641 * RB performance by 25%. (it disables 1 RB in the second packer)
643 if (info
->family
== CHIP_FIJI
&&
644 info
->cik_macrotile_mode_array
[0] == 0x000000e8) {
645 raster_config
= 0x16000012;
646 raster_config_1
= 0x0000002a;
649 *raster_config_p
= raster_config
;
650 *raster_config_1_p
= raster_config_1
;
654 ac_get_harvested_configs(struct radeon_info
*info
,
655 unsigned raster_config
,
656 unsigned *cik_raster_config_1_p
,
657 unsigned *raster_config_se
)
659 unsigned sh_per_se
= MAX2(info
->max_sh_per_se
, 1);
660 unsigned num_se
= MAX2(info
->max_se
, 1);
661 unsigned rb_mask
= info
->enabled_rb_mask
;
662 unsigned num_rb
= MIN2(info
->num_render_backends
, 16);
663 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
664 unsigned rb_per_se
= num_rb
/ num_se
;
668 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
669 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
670 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
671 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
673 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
674 assert(sh_per_se
== 1 || sh_per_se
== 2);
675 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
678 if (info
->chip_class
>= CIK
) {
679 unsigned raster_config_1
= *cik_raster_config_1_p
;
680 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
681 (!se_mask
[2] && !se_mask
[3]))) {
682 raster_config_1
&= C_028354_SE_PAIR_MAP
;
684 if (!se_mask
[0] && !se_mask
[1]) {
686 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
689 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
691 *cik_raster_config_1_p
= raster_config_1
;
695 for (se
= 0; se
< num_se
; se
++) {
696 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
697 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
698 int idx
= (se
/ 2) * 2;
700 raster_config_se
[se
] = raster_config
;
701 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
702 raster_config_se
[se
] &= C_028350_SE_MAP
;
705 raster_config_se
[se
] |=
706 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
708 raster_config_se
[se
] |=
709 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
713 pkr0_mask
&= rb_mask
;
714 pkr1_mask
&= rb_mask
;
715 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
716 raster_config_se
[se
] &= C_028350_PKR_MAP
;
719 raster_config_se
[se
] |=
720 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
722 raster_config_se
[se
] |=
723 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
727 if (rb_per_se
>= 2) {
728 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
729 unsigned rb1_mask
= rb0_mask
<< 1;
733 if (!rb0_mask
|| !rb1_mask
) {
734 raster_config_se
[se
] &= C_028350_RB_MAP_PKR0
;
737 raster_config_se
[se
] |=
738 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
740 raster_config_se
[se
] |=
741 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
746 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
747 rb1_mask
= rb0_mask
<< 1;
750 if (!rb0_mask
|| !rb1_mask
) {
751 raster_config_se
[se
] &= C_028350_RB_MAP_PKR1
;
754 raster_config_se
[se
] |=
755 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
757 raster_config_se
[se
] |=
758 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);