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ac: add radeon_info::tcc_harvested
[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "addrlib/src/amdgpu_asic_addr.h"
28 #include "sid.h"
29
30 #include "util/macros.h"
31 #include "util/u_math.h"
32
33 #include <stdio.h>
34
35 #include <xf86drm.h>
36 #include <amdgpu_drm.h>
37
38 #include <amdgpu.h>
39
40 #define CIK_TILE_MODE_COLOR_2D 14
41
42 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
56 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
57
58 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
59 {
60 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
61
62 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
63 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
64 return 2;
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
68 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
69 return 4;
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
76 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
77 return 8;
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
79 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
80 return 16;
81 default:
82 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
83 assert(!"this should never occur");
84 return 2;
85 }
86 }
87
88 static bool has_syncobj(int fd)
89 {
90 uint64_t value;
91 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
92 return false;
93 return value ? true : false;
94 }
95
96 static uint64_t fix_vram_size(uint64_t size)
97 {
98 /* The VRAM size is underreported, so we need to fix it, because
99 * it's used to compute the number of memory modules for harvesting.
100 */
101 return align64(size, 256*1024*1024);
102 }
103
104 bool ac_query_gpu_info(int fd, void *dev_p,
105 struct radeon_info *info,
106 struct amdgpu_gpu_info *amdinfo)
107 {
108 struct drm_amdgpu_info_device device_info = {};
109 struct amdgpu_buffer_size_alignments alignment_info = {};
110 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
111 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
112 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
113 struct amdgpu_gds_resource_info gds = {};
114 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
115 int r, i, j;
116 amdgpu_device_handle dev = dev_p;
117 drmDevicePtr devinfo;
118
119 /* Get PCI info. */
120 r = drmGetDevice2(fd, 0, &devinfo);
121 if (r) {
122 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
123 return false;
124 }
125 info->pci_domain = devinfo->businfo.pci->domain;
126 info->pci_bus = devinfo->businfo.pci->bus;
127 info->pci_dev = devinfo->businfo.pci->dev;
128 info->pci_func = devinfo->businfo.pci->func;
129 drmFreeDevice(&devinfo);
130
131 assert(info->drm_major == 3);
132 info->is_amdgpu = true;
133
134 /* Query hardware and driver information. */
135 r = amdgpu_query_gpu_info(dev, amdinfo);
136 if (r) {
137 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
138 return false;
139 }
140
141 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
142 &device_info);
143 if (r) {
144 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
145 return false;
146 }
147
148 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
149 if (r) {
150 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
151 return false;
152 }
153
154 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
155 if (r) {
156 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
157 return false;
158 }
159
160 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
161 if (r) {
162 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
163 return false;
164 }
165
166 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
167 if (r) {
168 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
169 return false;
170 }
171
172 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
173 if (r) {
174 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
175 return false;
176 }
177
178 if (info->drm_minor >= 17) {
179 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
180 if (r) {
181 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
182 return false;
183 }
184 }
185
186 if (info->drm_minor >= 17) {
187 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
188 if (r) {
189 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
190 return false;
191 }
192 }
193
194 if (info->drm_minor >= 17) {
195 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
196 if (r) {
197 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
198 return false;
199 }
200 }
201
202 if (info->drm_minor >= 27) {
203 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
204 if (r) {
205 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
206 return false;
207 }
208 }
209
210 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
211 &info->me_fw_version,
212 &info->me_fw_feature);
213 if (r) {
214 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
215 return false;
216 }
217
218 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
219 &info->pfp_fw_version,
220 &info->pfp_fw_feature);
221 if (r) {
222 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
223 return false;
224 }
225
226 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
227 &info->ce_fw_version,
228 &info->ce_fw_feature);
229 if (r) {
230 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
231 return false;
232 }
233
234 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
235 &uvd_version, &uvd_feature);
236 if (r) {
237 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
238 return false;
239 }
240
241 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
242 if (r) {
243 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
244 return false;
245 }
246
247 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
248 &vce_version, &vce_feature);
249 if (r) {
250 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
251 return false;
252 }
253
254 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
255 if (r) {
256 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
257 return false;
258 }
259
260 r = amdgpu_query_gds_info(dev, &gds);
261 if (r) {
262 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
263 return false;
264 }
265
266 if (info->drm_minor >= 9) {
267 struct drm_amdgpu_memory_info meminfo = {};
268
269 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
270 if (r) {
271 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
272 return false;
273 }
274
275 /* Note: usable_heap_size values can be random and can't be relied on. */
276 info->gart_size = meminfo.gtt.total_heap_size;
277 info->vram_size = fix_vram_size(meminfo.vram.total_heap_size);
278 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
279 } else {
280 /* This is a deprecated interface, which reports usable sizes
281 * (total minus pinned), but the pinned size computation is
282 * buggy, so the values returned from these functions can be
283 * random.
284 */
285 struct amdgpu_heap_info vram, vram_vis, gtt;
286
287 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
288 if (r) {
289 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
290 return false;
291 }
292
293 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
294 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
295 &vram_vis);
296 if (r) {
297 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
298 return false;
299 }
300
301 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
302 if (r) {
303 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
304 return false;
305 }
306
307 info->gart_size = gtt.heap_size;
308 info->vram_size = fix_vram_size(vram.heap_size);
309 info->vram_vis_size = vram_vis.heap_size;
310 }
311
312 /* Set chip identification. */
313 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
314 info->vce_harvest_config = amdinfo->vce_harvest_config;
315
316 #define identify_chip2(asic, chipname) \
317 if (ASICREV_IS(amdinfo->chip_external_rev, asic)) { \
318 info->family = CHIP_##chipname; \
319 info->name = #chipname; \
320 }
321 #define identify_chip(chipname) identify_chip2(chipname, chipname)
322
323 switch (amdinfo->family_id) {
324 case AMDGPU_FAMILY_SI:
325 identify_chip(TAHITI);
326 identify_chip(PITCAIRN);
327 identify_chip2(CAPEVERDE, VERDE);
328 identify_chip(OLAND);
329 identify_chip(HAINAN);
330 break;
331 case AMDGPU_FAMILY_CI:
332 identify_chip(BONAIRE);
333 identify_chip(HAWAII);
334 break;
335 case AMDGPU_FAMILY_KV:
336 identify_chip2(SPECTRE, KAVERI);
337 identify_chip2(SPOOKY, KAVERI);
338 identify_chip2(KALINDI, KABINI);
339 identify_chip2(GODAVARI, KABINI);
340 break;
341 case AMDGPU_FAMILY_VI:
342 identify_chip(ICELAND);
343 identify_chip(TONGA);
344 identify_chip(FIJI);
345 identify_chip(POLARIS10);
346 identify_chip(POLARIS11);
347 identify_chip(POLARIS12);
348 identify_chip(VEGAM);
349 break;
350 case AMDGPU_FAMILY_CZ:
351 identify_chip(CARRIZO);
352 identify_chip(STONEY);
353 break;
354 case AMDGPU_FAMILY_AI:
355 identify_chip(VEGA10);
356 identify_chip(VEGA12);
357 identify_chip(VEGA20);
358 identify_chip(ARCTURUS);
359 break;
360 case AMDGPU_FAMILY_RV:
361 identify_chip(RAVEN);
362 identify_chip(RAVEN2);
363 identify_chip(RENOIR);
364 break;
365 case AMDGPU_FAMILY_NV:
366 identify_chip(NAVI10);
367 identify_chip(NAVI12);
368 identify_chip(NAVI14);
369 break;
370 }
371
372 if (!info->name) {
373 fprintf(stderr, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
374 amdinfo->family_id, amdinfo->chip_external_rev);
375 return false;
376 }
377
378 if (info->family >= CHIP_NAVI10)
379 info->chip_class = GFX10;
380 else if (info->family >= CHIP_VEGA10)
381 info->chip_class = GFX9;
382 else if (info->family >= CHIP_TONGA)
383 info->chip_class = GFX8;
384 else if (info->family >= CHIP_BONAIRE)
385 info->chip_class = GFX7;
386 else if (info->family >= CHIP_TAHITI)
387 info->chip_class = GFX6;
388 else {
389 fprintf(stderr, "amdgpu: Unknown family.\n");
390 return false;
391 }
392
393 info->family_id = amdinfo->family_id;
394 info->chip_external_rev = amdinfo->chip_external_rev;
395 info->marketing_name = amdgpu_get_marketing_name(dev);
396 info->is_pro_graphics = info->marketing_name &&
397 (!strcmp(info->marketing_name, "Pro") ||
398 !strcmp(info->marketing_name, "PRO") ||
399 !strcmp(info->marketing_name, "Frontier"));
400
401 /* Set which chips have dedicated VRAM. */
402 info->has_dedicated_vram =
403 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
404
405 /* The kernel can split large buffers in VRAM but not in GTT, so large
406 * allocations can fail or cause buffer movement failures in the kernel.
407 */
408 if (info->has_dedicated_vram)
409 info->max_alloc_size = info->vram_size * 0.8;
410 else
411 info->max_alloc_size = info->gart_size * 0.7;
412
413 /* Set hardware information. */
414 info->gds_size = gds.gds_total_size;
415 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
416 /* convert the shader clock from KHz to MHz */
417 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
418 info->num_tcc_blocks = device_info.num_tcc_blocks;
419 info->max_se = amdinfo->num_shader_engines;
420 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
421 info->has_hw_decode =
422 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
423 (vcn_jpeg.available_rings != 0);
424 info->uvd_fw_version =
425 uvd.available_rings ? uvd_version : 0;
426 info->vce_fw_version =
427 vce.available_rings ? vce_version : 0;
428 info->uvd_enc_supported =
429 uvd_enc.available_rings ? true : false;
430 info->has_userptr = true;
431 info->has_syncobj = has_syncobj(fd);
432 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
433 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
434 info->has_ctx_priority = info->drm_minor >= 22;
435 info->has_local_buffers = info->drm_minor >= 20;
436 info->kernel_flushes_hdp_before_ib = true;
437 info->htile_cmask_support_1d_tiling = true;
438 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
439 info->has_bo_metadata = true;
440 info->has_gpu_reset_status_query = true;
441 info->has_eqaa_surface_allocator = true;
442 info->has_format_bc1_through_bc7 = true;
443 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
444 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
445 info->drm_minor >= 2;
446 info->has_indirect_compute_dispatch = true;
447 /* GFX6 doesn't support unaligned loads. */
448 info->has_unaligned_shader_loads = info->chip_class != GFX6;
449 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
450 * these faults are mitigated in software.
451 * Disable sparse mappings on GFX9 due to hangs.
452 */
453 info->has_sparse_vm_mappings =
454 info->chip_class >= GFX7 && info->chip_class <= GFX8 &&
455 info->drm_minor >= 13;
456 info->has_2d_tiling = true;
457 info->has_read_registers_query = true;
458 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
459
460 info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
461 info->num_render_backends = amdinfo->rb_pipes;
462 /* The value returned by the kernel driver was wrong. */
463 if (info->family == CHIP_KAVERI)
464 info->num_render_backends = 2;
465
466 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
467 if (!info->clock_crystal_freq) {
468 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
469 info->clock_crystal_freq = 1;
470 }
471 if (info->chip_class >= GFX10) {
472 info->tcc_cache_line_size = 128;
473 /* This is a hack, but it's all we can do without a kernel upgrade. */
474 info->tcc_harvested =
475 (info->vram_size / info->num_tcc_blocks) != 512*1024*1024;
476 } else {
477 info->tcc_cache_line_size = 64;
478 }
479 info->gb_addr_config = amdinfo->gb_addr_cfg;
480 if (info->chip_class == GFX9) {
481 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
482 info->pipe_interleave_bytes =
483 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
484 } else {
485 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
486 info->pipe_interleave_bytes =
487 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
488 }
489 info->r600_has_virtual_memory = true;
490
491 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
492 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
493
494 info->has_graphics = gfx.available_rings > 0;
495 info->num_sdma_rings = util_bitcount(dma.available_rings);
496 info->num_compute_rings = util_bitcount(compute.available_rings);
497
498 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
499 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
500 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
501 */
502 info->has_clear_state = info->chip_class >= GFX7;
503
504 info->has_distributed_tess = info->chip_class >= GFX8 &&
505 info->max_se >= 2;
506
507 info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
508 info->family == CHIP_RENOIR ||
509 info->chip_class >= GFX10;
510
511 info->has_rbplus = info->family == CHIP_STONEY ||
512 info->chip_class >= GFX9;
513
514 /* Some chips have RB+ registers, but don't support RB+. Those must
515 * always disable it.
516 */
517 info->rbplus_allowed = info->has_rbplus &&
518 (info->family == CHIP_STONEY ||
519 info->family == CHIP_VEGA12 ||
520 info->family == CHIP_RAVEN ||
521 info->family == CHIP_RAVEN2 ||
522 info->family == CHIP_RENOIR);
523
524 info->has_out_of_order_rast = info->chip_class >= GFX8 &&
525 info->max_se >= 2;
526
527 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
528 info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
529 (info->chip_class >= GFX8 &&
530 info->me_fw_feature >= 41);
531
532 info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
533
534 info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 ||
535 info->family == CHIP_RAVEN;
536
537 info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 &&
538 info->chip_class <= GFX9;
539
540 info->has_msaa_sample_loc_bug = (info->family >= CHIP_POLARIS10 &&
541 info->family <= CHIP_POLARIS12) ||
542 info->family == CHIP_VEGA10 ||
543 info->family == CHIP_RAVEN;
544
545 info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 ||
546 info->family == CHIP_RAVEN;
547
548 /* Get the number of good compute units. */
549 info->num_good_compute_units = 0;
550 for (i = 0; i < info->max_se; i++)
551 for (j = 0; j < info->max_sh_per_se; j++)
552 info->num_good_compute_units +=
553 util_bitcount(amdinfo->cu_bitmap[i][j]);
554 info->num_good_cu_per_sh = info->num_good_compute_units /
555 (info->max_se * info->max_sh_per_se);
556
557 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
558 sizeof(amdinfo->gb_tile_mode));
559 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
560
561 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
562 sizeof(amdinfo->gb_macro_tile_mode));
563
564 info->pte_fragment_size = alignment_info.size_local;
565 info->gart_page_size = alignment_info.size_remote;
566
567 if (info->chip_class == GFX6)
568 info->gfx_ib_pad_with_type2 = true;
569
570 unsigned ib_align = 0;
571 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
572 ib_align = MAX2(ib_align, compute.ib_start_alignment);
573 ib_align = MAX2(ib_align, dma.ib_start_alignment);
574 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
575 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
576 ib_align = MAX2(ib_align, vce.ib_start_alignment);
577 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
578 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
579 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
580 assert(ib_align);
581 info->ib_start_alignment = ib_align;
582
583 if (info->drm_minor >= 31 &&
584 (info->family == CHIP_RAVEN ||
585 info->family == CHIP_RAVEN2 ||
586 info->family == CHIP_RENOIR)) {
587 if (info->num_render_backends == 1)
588 info->use_display_dcc_unaligned = true;
589 else
590 info->use_display_dcc_with_retile_blit = true;
591 }
592
593 info->has_gds_ordered_append = info->chip_class >= GFX7 &&
594 info->drm_minor >= 29;
595
596 if (info->chip_class >= GFX9) {
597 unsigned pc_lines = 0;
598
599 switch (info->family) {
600 case CHIP_VEGA10:
601 case CHIP_VEGA12:
602 case CHIP_VEGA20:
603 pc_lines = 2048;
604 break;
605 case CHIP_RAVEN:
606 case CHIP_RAVEN2:
607 case CHIP_RENOIR:
608 case CHIP_NAVI10:
609 case CHIP_NAVI12:
610 pc_lines = 1024;
611 break;
612 case CHIP_NAVI14:
613 pc_lines = 512;
614 break;
615 default:
616 assert(0);
617 }
618
619 if (info->chip_class >= GFX10) {
620 info->pbb_max_alloc_count = pc_lines / 3;
621 } else {
622 info->pbb_max_alloc_count =
623 MIN2(128, pc_lines / (4 * info->max_se));
624 }
625 }
626
627 if (info->chip_class >= GFX10) {
628 switch (info->family) {
629 case CHIP_NAVI10:
630 case CHIP_NAVI12:
631 info->num_sdp_interfaces = 16;
632 break;
633 case CHIP_NAVI14:
634 info->num_sdp_interfaces = 8;
635 break;
636 default:
637 assert(0);
638 }
639 }
640
641 info->max_wave64_per_simd = info->family >= CHIP_POLARIS10 &&
642 info->family <= CHIP_VEGAM ? 8 : 10;
643
644 /* The number is per SIMD. There is enough SGPRs for the maximum number
645 * of Wave32, which is double the number for Wave64.
646 */
647 if (info->chip_class >= GFX10)
648 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2;
649 else if (info->chip_class >= GFX8)
650 info->num_physical_sgprs_per_simd = 800;
651 else
652 info->num_physical_sgprs_per_simd = 512;
653
654 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
655 return true;
656 }
657
658 void ac_compute_driver_uuid(char *uuid, size_t size)
659 {
660 char amd_uuid[] = "AMD-MESA-DRV";
661
662 assert(size >= sizeof(amd_uuid));
663
664 memset(uuid, 0, size);
665 strncpy(uuid, amd_uuid, size);
666 }
667
668 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
669 {
670 uint32_t *uint_uuid = (uint32_t*)uuid;
671
672 assert(size >= sizeof(uint32_t)*4);
673
674 /**
675 * Use the device info directly instead of using a sha1. GL/VK UUIDs
676 * are 16 byte vs 20 byte for sha1, and the truncation that would be
677 * required would get rid of part of the little entropy we have.
678 * */
679 memset(uuid, 0, size);
680 uint_uuid[0] = info->pci_domain;
681 uint_uuid[1] = info->pci_bus;
682 uint_uuid[2] = info->pci_dev;
683 uint_uuid[3] = info->pci_func;
684 }
685
686 void ac_print_gpu_info(struct radeon_info *info)
687 {
688 printf("Device info:\n");
689 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
690 info->pci_domain, info->pci_bus,
691 info->pci_dev, info->pci_func);
692 printf(" pci_id = 0x%x\n", info->pci_id);
693 printf(" family = %i\n", info->family);
694 printf(" chip_class = %i\n", info->chip_class);
695 printf(" chip_external_rev = %i\n", info->chip_external_rev);
696 printf(" num_compute_rings = %u\n", info->num_compute_rings);
697 printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
698 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
699 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
700 printf(" tcc_harvested = %u\n", info->tcc_harvested);
701
702 printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
703 printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
704
705 printf("Memory info:\n");
706 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
707 printf(" gart_page_size = %u\n", info->gart_page_size);
708 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
709 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
710 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
711 printf(" gds_size = %u kB\n", info->gds_size / 1024);
712 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
713 printf(" max_alloc_size = %i MB\n",
714 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
715 printf(" min_alloc_size = %u\n", info->min_alloc_size);
716 printf(" address32_hi = %u\n", info->address32_hi);
717 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
718
719 printf("CP info:\n");
720 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
721 printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
722 printf(" me_fw_version = %i\n", info->me_fw_version);
723 printf(" me_fw_feature = %i\n", info->me_fw_feature);
724 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
725 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
726 printf(" ce_fw_version = %i\n", info->ce_fw_version);
727 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
728
729 printf("Multimedia info:\n");
730 printf(" has_hw_decode = %u\n", info->has_hw_decode);
731 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
732 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
733 printf(" vce_fw_version = %u\n", info->vce_fw_version);
734 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
735
736 printf("Kernel & winsys capabilities:\n");
737 printf(" drm = %i.%i.%i\n", info->drm_major,
738 info->drm_minor, info->drm_patchlevel);
739 printf(" has_userptr = %i\n", info->has_userptr);
740 printf(" has_syncobj = %u\n", info->has_syncobj);
741 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
742 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
743 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
744 printf(" has_local_buffers = %u\n", info->has_local_buffers);
745 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
746 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
747 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
748 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
749 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
750 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
751 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
752 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
753 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
754 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
755 printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
756 printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
757 printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
758 printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
759 printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
760
761 printf("Shader core info:\n");
762 printf(" max_shader_clock = %i\n", info->max_shader_clock);
763 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
764 printf(" num_good_cu_per_sh = %i\n", info->num_good_cu_per_sh);
765 printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
766 printf(" max_se = %i\n", info->max_se);
767 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
768
769 printf("Render backend info:\n");
770 printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
771 printf(" num_render_backends = %i\n", info->num_render_backends);
772 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
773 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
774 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
775 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
776
777 printf("GB_ADDR_CONFIG:\n");
778 if (info->chip_class >= GFX9) {
779 printf(" num_pipes = %u\n",
780 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
781 printf(" pipe_interleave_size = %u\n",
782 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
783 printf(" max_compressed_frags = %u\n",
784 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
785 printf(" bank_interleave_size = %u\n",
786 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
787 printf(" num_banks = %u\n",
788 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
789 printf(" shader_engine_tile_size = %u\n",
790 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
791 printf(" num_shader_engines = %u\n",
792 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
793 printf(" num_gpus = %u (raw)\n",
794 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
795 printf(" multi_gpu_tile_size = %u (raw)\n",
796 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
797 printf(" num_rb_per_se = %u\n",
798 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
799 printf(" row_size = %u\n",
800 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
801 printf(" num_lower_pipes = %u (raw)\n",
802 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
803 printf(" se_enable = %u (raw)\n",
804 G_0098F8_SE_ENABLE(info->gb_addr_config));
805 } else {
806 printf(" num_pipes = %u\n",
807 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
808 printf(" pipe_interleave_size = %u\n",
809 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
810 printf(" bank_interleave_size = %u\n",
811 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
812 printf(" num_shader_engines = %u\n",
813 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
814 printf(" shader_engine_tile_size = %u\n",
815 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
816 printf(" num_gpus = %u (raw)\n",
817 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
818 printf(" multi_gpu_tile_size = %u (raw)\n",
819 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
820 printf(" row_size = %u\n",
821 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
822 printf(" num_lower_pipes = %u (raw)\n",
823 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
824 }
825 }
826
827 int
828 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
829 {
830 if (chip_class >= GFX9)
831 return -1;
832
833 switch (family) {
834 case CHIP_OLAND:
835 case CHIP_HAINAN:
836 case CHIP_KAVERI:
837 case CHIP_KABINI:
838 case CHIP_ICELAND:
839 case CHIP_CARRIZO:
840 case CHIP_STONEY:
841 return 16;
842 case CHIP_TAHITI:
843 case CHIP_PITCAIRN:
844 case CHIP_VERDE:
845 case CHIP_BONAIRE:
846 case CHIP_HAWAII:
847 case CHIP_TONGA:
848 case CHIP_FIJI:
849 case CHIP_POLARIS10:
850 case CHIP_POLARIS11:
851 case CHIP_POLARIS12:
852 case CHIP_VEGAM:
853 return 32;
854 default:
855 unreachable("Unknown GPU");
856 }
857 }
858
859 void
860 ac_get_raster_config(struct radeon_info *info,
861 uint32_t *raster_config_p,
862 uint32_t *raster_config_1_p,
863 uint32_t *se_tile_repeat_p)
864 {
865 unsigned raster_config, raster_config_1, se_tile_repeat;
866
867 switch (info->family) {
868 /* 1 SE / 1 RB */
869 case CHIP_HAINAN:
870 case CHIP_KABINI:
871 case CHIP_STONEY:
872 raster_config = 0x00000000;
873 raster_config_1 = 0x00000000;
874 break;
875 /* 1 SE / 4 RBs */
876 case CHIP_VERDE:
877 raster_config = 0x0000124a;
878 raster_config_1 = 0x00000000;
879 break;
880 /* 1 SE / 2 RBs (Oland is special) */
881 case CHIP_OLAND:
882 raster_config = 0x00000082;
883 raster_config_1 = 0x00000000;
884 break;
885 /* 1 SE / 2 RBs */
886 case CHIP_KAVERI:
887 case CHIP_ICELAND:
888 case CHIP_CARRIZO:
889 raster_config = 0x00000002;
890 raster_config_1 = 0x00000000;
891 break;
892 /* 2 SEs / 4 RBs */
893 case CHIP_BONAIRE:
894 case CHIP_POLARIS11:
895 case CHIP_POLARIS12:
896 raster_config = 0x16000012;
897 raster_config_1 = 0x00000000;
898 break;
899 /* 2 SEs / 8 RBs */
900 case CHIP_TAHITI:
901 case CHIP_PITCAIRN:
902 raster_config = 0x2a00126a;
903 raster_config_1 = 0x00000000;
904 break;
905 /* 4 SEs / 8 RBs */
906 case CHIP_TONGA:
907 case CHIP_POLARIS10:
908 raster_config = 0x16000012;
909 raster_config_1 = 0x0000002a;
910 break;
911 /* 4 SEs / 16 RBs */
912 case CHIP_HAWAII:
913 case CHIP_FIJI:
914 case CHIP_VEGAM:
915 raster_config = 0x3a00161a;
916 raster_config_1 = 0x0000002e;
917 break;
918 default:
919 fprintf(stderr,
920 "ac: Unknown GPU, using 0 for raster_config\n");
921 raster_config = 0x00000000;
922 raster_config_1 = 0x00000000;
923 break;
924 }
925
926 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
927 * This decreases performance by up to 50% when the RB is the bottleneck.
928 */
929 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
930 raster_config = 0x00000000;
931
932 /* Fiji: Old kernels have incorrect tiling config. This decreases
933 * RB performance by 25%. (it disables 1 RB in the second packer)
934 */
935 if (info->family == CHIP_FIJI &&
936 info->cik_macrotile_mode_array[0] == 0x000000e8) {
937 raster_config = 0x16000012;
938 raster_config_1 = 0x0000002a;
939 }
940
941 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
942 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
943
944 /* I don't know how to calculate this, though this is probably a good guess. */
945 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
946
947 *raster_config_p = raster_config;
948 *raster_config_1_p = raster_config_1;
949 if (se_tile_repeat_p)
950 *se_tile_repeat_p = se_tile_repeat;
951 }
952
953 void
954 ac_get_harvested_configs(struct radeon_info *info,
955 unsigned raster_config,
956 unsigned *cik_raster_config_1_p,
957 unsigned *raster_config_se)
958 {
959 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
960 unsigned num_se = MAX2(info->max_se, 1);
961 unsigned rb_mask = info->enabled_rb_mask;
962 unsigned num_rb = MIN2(info->num_render_backends, 16);
963 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
964 unsigned rb_per_se = num_rb / num_se;
965 unsigned se_mask[4];
966 unsigned se;
967
968 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
969 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
970 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
971 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
972
973 assert(num_se == 1 || num_se == 2 || num_se == 4);
974 assert(sh_per_se == 1 || sh_per_se == 2);
975 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
976
977
978 if (info->chip_class >= GFX7) {
979 unsigned raster_config_1 = *cik_raster_config_1_p;
980 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
981 (!se_mask[2] && !se_mask[3]))) {
982 raster_config_1 &= C_028354_SE_PAIR_MAP;
983
984 if (!se_mask[0] && !se_mask[1]) {
985 raster_config_1 |=
986 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
987 } else {
988 raster_config_1 |=
989 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
990 }
991 *cik_raster_config_1_p = raster_config_1;
992 }
993 }
994
995 for (se = 0; se < num_se; se++) {
996 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
997 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
998 int idx = (se / 2) * 2;
999
1000 raster_config_se[se] = raster_config;
1001 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1002 raster_config_se[se] &= C_028350_SE_MAP;
1003
1004 if (!se_mask[idx]) {
1005 raster_config_se[se] |=
1006 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
1007 } else {
1008 raster_config_se[se] |=
1009 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
1010 }
1011 }
1012
1013 pkr0_mask &= rb_mask;
1014 pkr1_mask &= rb_mask;
1015 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1016 raster_config_se[se] &= C_028350_PKR_MAP;
1017
1018 if (!pkr0_mask) {
1019 raster_config_se[se] |=
1020 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
1021 } else {
1022 raster_config_se[se] |=
1023 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
1024 }
1025 }
1026
1027 if (rb_per_se >= 2) {
1028 unsigned rb0_mask = 1 << (se * rb_per_se);
1029 unsigned rb1_mask = rb0_mask << 1;
1030
1031 rb0_mask &= rb_mask;
1032 rb1_mask &= rb_mask;
1033 if (!rb0_mask || !rb1_mask) {
1034 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
1035
1036 if (!rb0_mask) {
1037 raster_config_se[se] |=
1038 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
1039 } else {
1040 raster_config_se[se] |=
1041 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
1042 }
1043 }
1044
1045 if (rb_per_se > 2) {
1046 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1047 rb1_mask = rb0_mask << 1;
1048 rb0_mask &= rb_mask;
1049 rb1_mask &= rb_mask;
1050 if (!rb0_mask || !rb1_mask) {
1051 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
1052
1053 if (!rb0_mask) {
1054 raster_config_se[se] |=
1055 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
1056 } else {
1057 raster_config_se[se] |=
1058 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
1059 }
1060 }
1061 }
1062 }
1063 }
1064 }
1065
1066 unsigned ac_get_compute_resource_limits(struct radeon_info *info,
1067 unsigned waves_per_threadgroup,
1068 unsigned max_waves_per_sh,
1069 unsigned threadgroups_per_cu)
1070 {
1071 unsigned compute_resource_limits =
1072 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
1073
1074 if (info->chip_class >= GFX7) {
1075 unsigned num_cu_per_se = info->num_good_compute_units /
1076 info->max_se;
1077
1078 /* Force even distribution on all SIMDs in CU if the workgroup
1079 * size is 64. This has shown some good improvements if # of CUs
1080 * per SE is not a multiple of 4.
1081 */
1082 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
1083 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
1084
1085 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
1086 compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
1087 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
1088 } else {
1089 /* GFX6 */
1090 if (max_waves_per_sh) {
1091 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
1092 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
1093 }
1094 }
1095 return compute_resource_limits;
1096 }