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ac/gpu_info: add has_sparse_vm_mappings
[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "sid.h"
28 #include "gfx9d.h"
29
30 #include "util/u_math.h"
31
32 #include <stdio.h>
33
34 #include <xf86drm.h>
35 #include <amdgpu_drm.h>
36
37 #include <amdgpu.h>
38
39 #define CIK_TILE_MODE_COLOR_2D 14
40
41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
42 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
56
57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
58 {
59 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
60
61 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
62 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
63 return 2;
64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
68 return 4;
69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
76 return 8;
77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
79 return 16;
80 default:
81 fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
82 assert(!"this should never occur");
83 return 2;
84 }
85 }
86
87 static bool has_syncobj(int fd)
88 {
89 uint64_t value;
90 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
91 return false;
92 return value ? true : false;
93 }
94
95 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
96 struct radeon_info *info,
97 struct amdgpu_gpu_info *amdinfo)
98 {
99 struct amdgpu_buffer_size_alignments alignment_info = {};
100 struct amdgpu_heap_info vram, vram_vis, gtt;
101 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
102 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
103 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
104 struct amdgpu_gds_resource_info gds = {};
105 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
106 int r, i, j;
107 drmDevicePtr devinfo;
108
109 /* Get PCI info. */
110 r = drmGetDevice2(fd, 0, &devinfo);
111 if (r) {
112 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
113 return false;
114 }
115 info->pci_domain = devinfo->businfo.pci->domain;
116 info->pci_bus = devinfo->businfo.pci->bus;
117 info->pci_dev = devinfo->businfo.pci->dev;
118 info->pci_func = devinfo->businfo.pci->func;
119 drmFreeDevice(&devinfo);
120
121 /* Query hardware and driver information. */
122 r = amdgpu_query_gpu_info(dev, amdinfo);
123 if (r) {
124 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
125 return false;
126 }
127
128 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
129 if (r) {
130 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
131 return false;
132 }
133
134 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
135 if (r) {
136 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
137 return false;
138 }
139
140 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
141 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
142 &vram_vis);
143 if (r) {
144 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
145 return false;
146 }
147
148 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
149 if (r) {
150 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
151 return false;
152 }
153
154 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
155 if (r) {
156 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
157 return false;
158 }
159
160 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
161 if (r) {
162 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
163 return false;
164 }
165
166 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
167 if (r) {
168 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
169 return false;
170 }
171
172 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
173 if (r) {
174 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
175 return false;
176 }
177
178 if (info->drm_major == 3 && info->drm_minor >= 17) {
179 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
180 if (r) {
181 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
182 return false;
183 }
184 }
185
186 if (info->drm_major == 3 && info->drm_minor >= 17) {
187 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
188 if (r) {
189 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
190 return false;
191 }
192 }
193
194 if (info->drm_major == 3 && info->drm_minor >= 17) {
195 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
196 if (r) {
197 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
198 return false;
199 }
200 }
201
202 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
203 &info->me_fw_version,
204 &info->me_fw_feature);
205 if (r) {
206 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
207 return false;
208 }
209
210 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
211 &info->pfp_fw_version,
212 &info->pfp_fw_feature);
213 if (r) {
214 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
215 return false;
216 }
217
218 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
219 &info->ce_fw_version,
220 &info->ce_fw_feature);
221 if (r) {
222 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
223 return false;
224 }
225
226 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
227 &uvd_version, &uvd_feature);
228 if (r) {
229 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
230 return false;
231 }
232
233 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
234 if (r) {
235 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
236 return false;
237 }
238
239 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
240 &vce_version, &vce_feature);
241 if (r) {
242 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
243 return false;
244 }
245
246 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
247 if (r) {
248 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
249 return false;
250 }
251
252 r = amdgpu_query_gds_info(dev, &gds);
253 if (r) {
254 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
255 return false;
256 }
257
258 /* Set chip identification. */
259 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
260 info->vce_harvest_config = amdinfo->vce_harvest_config;
261
262 switch (info->pci_id) {
263 #define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
264 #include "pci_ids/radeonsi_pci_ids.h"
265 #undef CHIPSET
266
267 default:
268 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
269 return false;
270 }
271
272 if (info->family >= CHIP_VEGA10)
273 info->chip_class = GFX9;
274 else if (info->family >= CHIP_TONGA)
275 info->chip_class = VI;
276 else if (info->family >= CHIP_BONAIRE)
277 info->chip_class = CIK;
278 else if (info->family >= CHIP_TAHITI)
279 info->chip_class = SI;
280 else {
281 fprintf(stderr, "amdgpu: Unknown family.\n");
282 return false;
283 }
284
285 /* Set which chips have dedicated VRAM. */
286 info->has_dedicated_vram =
287 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
288
289 /* Set hardware information. */
290 info->gart_size = gtt.heap_size;
291 info->vram_size = vram.heap_size;
292 info->vram_vis_size = vram_vis.heap_size;
293 info->gds_size = gds.gds_total_size;
294 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
295 /* The kernel can split large buffers in VRAM but not in GTT, so large
296 * allocations can fail or cause buffer movement failures in the kernel.
297 */
298 info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 0.7);
299 /* convert the shader clock from KHz to MHz */
300 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
301 info->max_se = amdinfo->num_shader_engines;
302 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
303 info->has_hw_decode =
304 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
305 info->uvd_fw_version =
306 uvd.available_rings ? uvd_version : 0;
307 info->vce_fw_version =
308 vce.available_rings ? vce_version : 0;
309 info->uvd_enc_supported =
310 uvd_enc.available_rings ? true : false;
311 info->has_userptr = true;
312 info->has_syncobj = has_syncobj(fd);
313 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
314 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
315 info->has_ctx_priority = info->drm_minor >= 22;
316 /* TODO: Enable this once the kernel handles it efficiently. */
317 info->has_local_buffers = info->drm_minor >= 20 &&
318 !info->has_dedicated_vram;
319 info->kernel_flushes_hdp_before_ib = true;
320 info->htile_cmask_support_1d_tiling = true;
321 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
322 info->has_bo_metadata = true;
323 info->has_gpu_reset_status_query = true;
324 info->has_gpu_reset_counter_query = false;
325 info->has_eqaa_surface_allocator = true;
326 info->has_format_bc1_through_bc7 = true;
327 /* DRM 3.1.0 doesn't flush TC for VI correctly. */
328 info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
329 info->drm_minor >= 2;
330 info->has_indirect_compute_dispatch = true;
331 /* SI doesn't support unaligned loads. */
332 info->has_unaligned_shader_loads = info->chip_class != SI;
333 /* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once
334 * these faults are mitigated in software.
335 * Disable sparse mappings on GFX9 due to hangs.
336 */
337 info->has_sparse_vm_mappings =
338 info->chip_class >= CIK && info->chip_class <= VI &&
339 info->drm_minor >= 13;
340
341 info->num_render_backends = amdinfo->rb_pipes;
342 /* The value returned by the kernel driver was wrong. */
343 if (info->family == CHIP_KAVERI)
344 info->num_render_backends = 2;
345
346 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
347 if (!info->clock_crystal_freq) {
348 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
349 info->clock_crystal_freq = 1;
350 }
351 info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
352 info->gb_addr_config = amdinfo->gb_addr_cfg;
353 if (info->chip_class == GFX9) {
354 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
355 info->pipe_interleave_bytes =
356 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
357 } else {
358 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
359 info->pipe_interleave_bytes =
360 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
361 }
362 info->r600_has_virtual_memory = true;
363
364 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
365 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
366
367 info->num_sdma_rings = util_bitcount(dma.available_rings);
368 info->num_compute_rings = util_bitcount(compute.available_rings);
369
370 /* Get the number of good compute units. */
371 info->num_good_compute_units = 0;
372 for (i = 0; i < info->max_se; i++)
373 for (j = 0; j < info->max_sh_per_se; j++)
374 info->num_good_compute_units +=
375 util_bitcount(amdinfo->cu_bitmap[i][j]);
376
377 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
378 sizeof(amdinfo->gb_tile_mode));
379 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
380
381 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
382 sizeof(amdinfo->gb_macro_tile_mode));
383
384 info->pte_fragment_size = alignment_info.size_local;
385 info->gart_page_size = alignment_info.size_remote;
386
387 if (info->chip_class == SI)
388 info->gfx_ib_pad_with_type2 = TRUE;
389
390 unsigned ib_align = 0;
391 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
392 ib_align = MAX2(ib_align, compute.ib_start_alignment);
393 ib_align = MAX2(ib_align, dma.ib_start_alignment);
394 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
395 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
396 ib_align = MAX2(ib_align, vce.ib_start_alignment);
397 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
398 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
399 assert(ib_align);
400 info->ib_start_alignment = ib_align;
401
402 return true;
403 }
404
405 void ac_compute_driver_uuid(char *uuid, size_t size)
406 {
407 char amd_uuid[] = "AMD-MESA-DRV";
408
409 assert(size >= sizeof(amd_uuid));
410
411 memset(uuid, 0, size);
412 strncpy(uuid, amd_uuid, size);
413 }
414
415 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
416 {
417 uint32_t *uint_uuid = (uint32_t*)uuid;
418
419 assert(size >= sizeof(uint32_t)*4);
420
421 /**
422 * Use the device info directly instead of using a sha1. GL/VK UUIDs
423 * are 16 byte vs 20 byte for sha1, and the truncation that would be
424 * required would get rid of part of the little entropy we have.
425 * */
426 memset(uuid, 0, size);
427 uint_uuid[0] = info->pci_domain;
428 uint_uuid[1] = info->pci_bus;
429 uint_uuid[2] = info->pci_dev;
430 uint_uuid[3] = info->pci_func;
431 }
432
433 void ac_print_gpu_info(struct radeon_info *info)
434 {
435 printf("Device info:\n");
436 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
437 info->pci_domain, info->pci_bus,
438 info->pci_dev, info->pci_func);
439 printf(" pci_id = 0x%x\n", info->pci_id);
440 printf(" family = %i\n", info->family);
441 printf(" chip_class = %i\n", info->chip_class);
442 printf(" num_compute_rings = %u\n", info->num_compute_rings);
443 printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
444 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
445 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
446
447 printf("Memory info:\n");
448 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
449 printf(" gart_page_size = %u\n", info->gart_page_size);
450 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
451 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
452 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
453 printf(" gds_size = %u kB\n", info->gds_size / 1024);
454 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
455 printf(" max_alloc_size = %i MB\n",
456 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
457 printf(" min_alloc_size = %u\n", info->min_alloc_size);
458 printf(" address32_hi = %u\n", info->address32_hi);
459 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
460
461 printf("CP info:\n");
462 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
463 printf(" ib_start_alignment = %u\n", info->ib_start_alignment);
464 printf(" me_fw_version = %i\n", info->me_fw_version);
465 printf(" me_fw_feature = %i\n", info->me_fw_feature);
466 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
467 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
468 printf(" ce_fw_version = %i\n", info->ce_fw_version);
469 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
470
471 printf("Multimedia info:\n");
472 printf(" has_hw_decode = %u\n", info->has_hw_decode);
473 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
474 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
475 printf(" vce_fw_version = %u\n", info->vce_fw_version);
476 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
477
478 printf("Kernel & winsys capabilities:\n");
479 printf(" drm = %i.%i.%i\n", info->drm_major,
480 info->drm_minor, info->drm_patchlevel);
481 printf(" has_userptr = %i\n", info->has_userptr);
482 printf(" has_syncobj = %u\n", info->has_syncobj);
483 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
484 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
485 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
486 printf(" has_local_buffers = %u\n", info->has_local_buffers);
487 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
488 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
489 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
490 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
491 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
492 printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
493 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
494 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
495 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
496 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
497 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
498 printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
499
500 printf("Shader core info:\n");
501 printf(" max_shader_clock = %i\n", info->max_shader_clock);
502 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
503 printf(" max_se = %i\n", info->max_se);
504 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
505
506 printf("Render backend info:\n");
507 printf(" num_render_backends = %i\n", info->num_render_backends);
508 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
509 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
510 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
511 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
512
513 printf("GB_ADDR_CONFIG:\n");
514 if (info->chip_class >= GFX9) {
515 printf(" num_pipes = %u\n",
516 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
517 printf(" pipe_interleave_size = %u\n",
518 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
519 printf(" max_compressed_frags = %u\n",
520 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
521 printf(" bank_interleave_size = %u\n",
522 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
523 printf(" num_banks = %u\n",
524 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
525 printf(" shader_engine_tile_size = %u\n",
526 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
527 printf(" num_shader_engines = %u\n",
528 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
529 printf(" num_gpus = %u (raw)\n",
530 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
531 printf(" multi_gpu_tile_size = %u (raw)\n",
532 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
533 printf(" num_rb_per_se = %u\n",
534 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
535 printf(" row_size = %u\n",
536 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
537 printf(" num_lower_pipes = %u (raw)\n",
538 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
539 printf(" se_enable = %u (raw)\n",
540 G_0098F8_SE_ENABLE(info->gb_addr_config));
541 } else {
542 printf(" num_pipes = %u\n",
543 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
544 printf(" pipe_interleave_size = %u\n",
545 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
546 printf(" bank_interleave_size = %u\n",
547 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
548 printf(" num_shader_engines = %u\n",
549 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
550 printf(" shader_engine_tile_size = %u\n",
551 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
552 printf(" num_gpus = %u (raw)\n",
553 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
554 printf(" multi_gpu_tile_size = %u (raw)\n",
555 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
556 printf(" row_size = %u\n",
557 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
558 printf(" num_lower_pipes = %u (raw)\n",
559 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
560 }
561 }
562
563 int
564 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
565 {
566 if (chip_class >= GFX9)
567 return -1;
568
569 switch (family) {
570 case CHIP_OLAND:
571 case CHIP_HAINAN:
572 case CHIP_KAVERI:
573 case CHIP_KABINI:
574 case CHIP_MULLINS:
575 case CHIP_ICELAND:
576 case CHIP_CARRIZO:
577 case CHIP_STONEY:
578 return 16;
579 case CHIP_TAHITI:
580 case CHIP_PITCAIRN:
581 case CHIP_VERDE:
582 case CHIP_BONAIRE:
583 case CHIP_HAWAII:
584 case CHIP_TONGA:
585 case CHIP_FIJI:
586 case CHIP_POLARIS10:
587 case CHIP_POLARIS11:
588 case CHIP_POLARIS12:
589 case CHIP_VEGAM:
590 return 32;
591 default:
592 unreachable("Unknown GPU");
593 }
594 }
595
596 void
597 ac_get_raster_config(struct radeon_info *info,
598 uint32_t *raster_config_p,
599 uint32_t *raster_config_1_p)
600 {
601 unsigned raster_config, raster_config_1;
602
603 switch (info->family) {
604 /* 1 SE / 1 RB */
605 case CHIP_HAINAN:
606 case CHIP_KABINI:
607 case CHIP_MULLINS:
608 case CHIP_STONEY:
609 raster_config = 0x00000000;
610 raster_config_1 = 0x00000000;
611 break;
612 /* 1 SE / 4 RBs */
613 case CHIP_VERDE:
614 raster_config = 0x0000124a;
615 raster_config_1 = 0x00000000;
616 break;
617 /* 1 SE / 2 RBs (Oland is special) */
618 case CHIP_OLAND:
619 raster_config = 0x00000082;
620 raster_config_1 = 0x00000000;
621 break;
622 /* 1 SE / 2 RBs */
623 case CHIP_KAVERI:
624 case CHIP_ICELAND:
625 case CHIP_CARRIZO:
626 raster_config = 0x00000002;
627 raster_config_1 = 0x00000000;
628 break;
629 /* 2 SEs / 4 RBs */
630 case CHIP_BONAIRE:
631 case CHIP_POLARIS11:
632 case CHIP_POLARIS12:
633 raster_config = 0x16000012;
634 raster_config_1 = 0x00000000;
635 break;
636 /* 2 SEs / 8 RBs */
637 case CHIP_TAHITI:
638 case CHIP_PITCAIRN:
639 raster_config = 0x2a00126a;
640 raster_config_1 = 0x00000000;
641 break;
642 /* 4 SEs / 8 RBs */
643 case CHIP_TONGA:
644 case CHIP_POLARIS10:
645 raster_config = 0x16000012;
646 raster_config_1 = 0x0000002a;
647 break;
648 /* 4 SEs / 16 RBs */
649 case CHIP_HAWAII:
650 case CHIP_FIJI:
651 case CHIP_VEGAM:
652 raster_config = 0x3a00161a;
653 raster_config_1 = 0x0000002e;
654 break;
655 default:
656 fprintf(stderr,
657 "ac: Unknown GPU, using 0 for raster_config\n");
658 raster_config = 0x00000000;
659 raster_config_1 = 0x00000000;
660 break;
661 }
662
663 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
664 * This decreases performance by up to 50% when the RB is the bottleneck.
665 */
666 if (info->family == CHIP_KAVERI && info->drm_major == 2)
667 raster_config = 0x00000000;
668
669 /* Fiji: Old kernels have incorrect tiling config. This decreases
670 * RB performance by 25%. (it disables 1 RB in the second packer)
671 */
672 if (info->family == CHIP_FIJI &&
673 info->cik_macrotile_mode_array[0] == 0x000000e8) {
674 raster_config = 0x16000012;
675 raster_config_1 = 0x0000002a;
676 }
677
678 *raster_config_p = raster_config;
679 *raster_config_1_p = raster_config_1;
680 }
681
682 void
683 ac_get_harvested_configs(struct radeon_info *info,
684 unsigned raster_config,
685 unsigned *cik_raster_config_1_p,
686 unsigned *raster_config_se)
687 {
688 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
689 unsigned num_se = MAX2(info->max_se, 1);
690 unsigned rb_mask = info->enabled_rb_mask;
691 unsigned num_rb = MIN2(info->num_render_backends, 16);
692 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
693 unsigned rb_per_se = num_rb / num_se;
694 unsigned se_mask[4];
695 unsigned se;
696
697 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
698 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
699 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
700 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
701
702 assert(num_se == 1 || num_se == 2 || num_se == 4);
703 assert(sh_per_se == 1 || sh_per_se == 2);
704 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
705
706
707 if (info->chip_class >= CIK) {
708 unsigned raster_config_1 = *cik_raster_config_1_p;
709 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
710 (!se_mask[2] && !se_mask[3]))) {
711 raster_config_1 &= C_028354_SE_PAIR_MAP;
712
713 if (!se_mask[0] && !se_mask[1]) {
714 raster_config_1 |=
715 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
716 } else {
717 raster_config_1 |=
718 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
719 }
720 *cik_raster_config_1_p = raster_config_1;
721 }
722 }
723
724 for (se = 0; se < num_se; se++) {
725 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
726 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
727 int idx = (se / 2) * 2;
728
729 raster_config_se[se] = raster_config;
730 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
731 raster_config_se[se] &= C_028350_SE_MAP;
732
733 if (!se_mask[idx]) {
734 raster_config_se[se] |=
735 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
736 } else {
737 raster_config_se[se] |=
738 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
739 }
740 }
741
742 pkr0_mask &= rb_mask;
743 pkr1_mask &= rb_mask;
744 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
745 raster_config_se[se] &= C_028350_PKR_MAP;
746
747 if (!pkr0_mask) {
748 raster_config_se[se] |=
749 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
750 } else {
751 raster_config_se[se] |=
752 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
753 }
754 }
755
756 if (rb_per_se >= 2) {
757 unsigned rb0_mask = 1 << (se * rb_per_se);
758 unsigned rb1_mask = rb0_mask << 1;
759
760 rb0_mask &= rb_mask;
761 rb1_mask &= rb_mask;
762 if (!rb0_mask || !rb1_mask) {
763 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
764
765 if (!rb0_mask) {
766 raster_config_se[se] |=
767 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
768 } else {
769 raster_config_se[se] |=
770 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
771 }
772 }
773
774 if (rb_per_se > 2) {
775 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
776 rb1_mask = rb0_mask << 1;
777 rb0_mask &= rb_mask;
778 rb1_mask &= rb_mask;
779 if (!rb0_mask || !rb1_mask) {
780 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
781
782 if (!rb0_mask) {
783 raster_config_se[se] |=
784 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
785 } else {
786 raster_config_se[se] |=
787 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
788 }
789 }
790 }
791 }
792 }
793 }