src/amd/common/ac_gpu_info.c

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #include "ac_gpu_info.h"
  27 #include "sid.h"
  28 #include "gfx9d.h"
  29
  30 #include "util/u_math.h"
  31
  32 #include <stdio.h>
  33
  34 #include <xf86drm.h>
  35 #include <amdgpu_drm.h>
  36
  37 #include <amdgpu.h>
  38
  39 #define CIK_TILE_MODE_COLOR_2D                  14
  40
  41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  42 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  43 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  44 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  45 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  46 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  47 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  48 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  54 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  55 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  56
  57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  58 {
  59    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  60
  61    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  62    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  63        return 2;
  64    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  65    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  66    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  67    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  68        return 4;
  69    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  70    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  71    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  72    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  73    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  74    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  75    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  76        return 8;
  77    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  78    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  79        return 16;
  80    default:
  81        fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
  82        assert(!"this should never occur");
  83        return 2;
  84    }
  85 }
  86
  87 static bool has_syncobj(int fd)
  88 {
  89         uint64_t value;
  90         if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
  91                 return false;
  92         return value ? true : false;
  93 }
  94
  95 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
  96                        struct radeon_info *info,
  97                        struct amdgpu_gpu_info *amdinfo)
  98 {
  99         struct amdgpu_buffer_size_alignments alignment_info = {};
 100         struct amdgpu_heap_info vram, vram_vis, gtt;
 101         struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
 102         struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
 103         struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
 104         struct amdgpu_gds_resource_info gds = {};
 105         uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
 106         int r, i, j;
 107         drmDevicePtr devinfo;
 108
 109         /* Get PCI info. */
 110         r = drmGetDevice2(fd, 0, &devinfo);
 111         if (r) {
 112                 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
 113                 return false;
 114         }
 115         info->pci_domain = devinfo->businfo.pci->domain;
 116         info->pci_bus = devinfo->businfo.pci->bus;
 117         info->pci_dev = devinfo->businfo.pci->dev;
 118         info->pci_func = devinfo->businfo.pci->func;
 119         drmFreeDevice(&devinfo);
 120
 121         /* Query hardware and driver information. */
 122         r = amdgpu_query_gpu_info(dev, amdinfo);
 123         if (r) {
 124                 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 125                 return false;
 126         }
 127
 128         r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
 129         if (r) {
 130                 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 131                 return false;
 132         }
 133
 134         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 135         if (r) {
 136                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 137                 return false;
 138         }
 139
 140         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
 141                                 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 142                                 &vram_vis);
 143         if (r) {
 144                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
 145                 return false;
 146         }
 147
 148         r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 149         if (r) {
 150                 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 151                 return false;
 152         }
 153
 154         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
 155         if (r) {
 156                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 157                 return false;
 158         }
 159
 160         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
 161         if (r) {
 162                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
 163                 return false;
 164         }
 165
 166         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
 167         if (r) {
 168                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
 169                 return false;
 170         }
 171
 172         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 173         if (r) {
 174                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 175                 return false;
 176         }
 177
 178         if (info->drm_major == 3 && info->drm_minor >= 17) {
 179                 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
 180                 if (r) {
 181                         fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
 182                         return false;
 183                 }
 184         }
 185
 186         if (info->drm_major == 3 && info->drm_minor >= 17) {
 187                 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
 188                 if (r) {
 189                         fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
 190                         return false;
 191                 }
 192         }
 193
 194         if (info->drm_major == 3 && info->drm_minor >= 17) {
 195                 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
 196                 if (r) {
 197                         fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
 198                         return false;
 199                 }
 200         }
 201
 202         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
 203                                         &info->me_fw_version,
 204                                         &info->me_fw_feature);
 205         if (r) {
 206                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
 207                 return false;
 208         }
 209
 210         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
 211                                         &info->pfp_fw_version,
 212                                         &info->pfp_fw_feature);
 213         if (r) {
 214                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
 215                 return false;
 216         }
 217
 218         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
 219                                         &info->ce_fw_version,
 220                                         &info->ce_fw_feature);
 221         if (r) {
 222                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
 223                 return false;
 224         }
 225
 226         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
 227                                         &uvd_version, &uvd_feature);
 228         if (r) {
 229                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
 230                 return false;
 231         }
 232
 233         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
 234         if (r) {
 235                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 236                 return false;
 237         }
 238
 239         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
 240                                         &vce_version, &vce_feature);
 241         if (r) {
 242                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 243                 return false;
 244         }
 245
 246         r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
 247         if (r) {
 248                 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
 249                 return false;
 250         }
 251
 252         r = amdgpu_query_gds_info(dev, &gds);
 253         if (r) {
 254                 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
 255                 return false;
 256         }
 257
 258         /* Set chip identification. */
 259         info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
 260         info->vce_harvest_config = amdinfo->vce_harvest_config;
 261
 262         switch (info->pci_id) {
 263 #define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily; break;
 264 #include "pci_ids/radeonsi_pci_ids.h"
 265 #undef CHIPSET
 266
 267         default:
 268                 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 269                 return false;
 270         }
 271
 272         if (info->family >= CHIP_VEGA10)
 273                 info->chip_class = GFX9;
 274         else if (info->family >= CHIP_TONGA)
 275                 info->chip_class = VI;
 276         else if (info->family >= CHIP_BONAIRE)
 277                 info->chip_class = CIK;
 278         else if (info->family >= CHIP_TAHITI)
 279                 info->chip_class = SI;
 280         else {
 281                 fprintf(stderr, "amdgpu: Unknown family.\n");
 282                 return false;
 283         }
 284
 285         /* Set which chips have dedicated VRAM. */
 286         info->has_dedicated_vram =
 287                 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
 288
 289         /* Set hardware information. */
 290         info->gart_size = gtt.heap_size;
 291         info->vram_size = vram.heap_size;
 292         info->vram_vis_size = vram_vis.heap_size;
 293         info->gds_size = gds.gds_total_size;
 294         info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
 295         /* The kernel can split large buffers in VRAM but not in GTT, so large
 296          * allocations can fail or cause buffer movement failures in the kernel.
 297          */
 298         info->max_alloc_size = MIN2(info->vram_size * 0.9, info->gart_size * 0.7);
 299         /* convert the shader clock from KHz to MHz */
 300         info->max_shader_clock = amdinfo->max_engine_clk / 1000;
 301         info->max_se = amdinfo->num_shader_engines;
 302         info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
 303         info->has_hw_decode =
 304                 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
 305         info->uvd_fw_version =
 306                 uvd.available_rings ? uvd_version : 0;
 307         info->vce_fw_version =
 308                 vce.available_rings ? vce_version : 0;
 309         info->uvd_enc_supported =
 310                 uvd_enc.available_rings ? true : false;
 311         info->has_userptr = true;
 312         info->has_syncobj = has_syncobj(fd);
 313         info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
 314         info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
 315         info->has_ctx_priority = info->drm_minor >= 22;
 316         info->num_render_backends = amdinfo->rb_pipes;
 317         info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 318         if (!info->clock_crystal_freq) {
 319                 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
 320                 info->clock_crystal_freq = 1;
 321         }
 322         info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 323         if (info->chip_class == GFX9) {
 324                 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
 325                 info->pipe_interleave_bytes =
 326                         256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
 327         } else {
 328                 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
 329                 info->pipe_interleave_bytes =
 330                         256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
 331         }
 332         info->has_virtual_memory = true;
 333
 334         assert(util_is_power_of_two(dma.available_rings + 1));
 335         assert(util_is_power_of_two(compute.available_rings + 1));
 336
 337         info->num_sdma_rings = util_bitcount(dma.available_rings);
 338         info->num_compute_rings = util_bitcount(compute.available_rings);
 339
 340         /* Get the number of good compute units. */
 341         info->num_good_compute_units = 0;
 342         for (i = 0; i < info->max_se; i++)
 343                 for (j = 0; j < info->max_sh_per_se; j++)
 344                         info->num_good_compute_units +=
 345                                 util_bitcount(amdinfo->cu_bitmap[i][j]);
 346
 347         memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
 348                 sizeof(amdinfo->gb_tile_mode));
 349         info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
 350
 351         memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
 352                 sizeof(amdinfo->gb_macro_tile_mode));
 353
 354         info->pte_fragment_size = alignment_info.size_local;
 355         info->gart_page_size = alignment_info.size_remote;
 356
 357         if (info->chip_class == SI)
 358                 info->gfx_ib_pad_with_type2 = TRUE;
 359
 360         unsigned ib_align = 0;
 361         ib_align = MAX2(ib_align, gfx.ib_start_alignment);
 362         ib_align = MAX2(ib_align, compute.ib_start_alignment);
 363         ib_align = MAX2(ib_align, dma.ib_start_alignment);
 364         ib_align = MAX2(ib_align, uvd.ib_start_alignment);
 365         ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
 366         ib_align = MAX2(ib_align, vce.ib_start_alignment);
 367         ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
 368         ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
 369        assert(ib_align);
 370         info->ib_start_alignment = ib_align;
 371
 372         return true;
 373 }
 374
 375 void ac_compute_driver_uuid(char *uuid, size_t size)
 376 {
 377         char amd_uuid[] = "AMD-MESA-DRV";
 378
 379         assert(size >= sizeof(amd_uuid));
 380
 381         memset(uuid, 0, size);
 382         strncpy(uuid, amd_uuid, size);
 383 }
 384
 385 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
 386 {
 387         uint32_t *uint_uuid = (uint32_t*)uuid;
 388
 389         assert(size >= sizeof(uint32_t)*4);
 390
 391         /**
 392          * Use the device info directly instead of using a sha1. GL/VK UUIDs
 393          * are 16 byte vs 20 byte for sha1, and the truncation that would be
 394          * required would get rid of part of the little entropy we have.
 395          * */
 396         memset(uuid, 0, size);
 397         uint_uuid[0] = info->pci_domain;
 398         uint_uuid[1] = info->pci_bus;
 399         uint_uuid[2] = info->pci_dev;
 400         uint_uuid[3] = info->pci_func;
 401 }
 402
 403 void ac_print_gpu_info(struct radeon_info *info)
 404 {
 405         printf("pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
 406                info->pci_domain, info->pci_bus,
 407                info->pci_dev, info->pci_func);
 408         printf("pci_id = 0x%x\n", info->pci_id);
 409         printf("family = %i\n", info->family);
 410         printf("chip_class = %i\n", info->chip_class);
 411         printf("pte_fragment_size = %u\n", info->pte_fragment_size);
 412         printf("gart_page_size = %u\n", info->gart_page_size);
 413         printf("gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
 414         printf("vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
 415         printf("vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
 416         printf("gds_size = %u kB\n", info->gds_size / 1024);
 417         printf("gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
 418         printf("max_alloc_size = %i MB\n",
 419                (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
 420         printf("min_alloc_size = %u\n", info->min_alloc_size);
 421         printf("address32_hi = %u\n", info->address32_hi);
 422         printf("has_dedicated_vram = %u\n", info->has_dedicated_vram);
 423         printf("has_virtual_memory = %i\n", info->has_virtual_memory);
 424         printf("gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
 425         printf("has_hw_decode = %u\n", info->has_hw_decode);
 426        printf("ib_start_alignment = %u\n", info->ib_start_alignment);
 427         printf("num_sdma_rings = %i\n", info->num_sdma_rings);
 428         printf("num_compute_rings = %u\n", info->num_compute_rings);
 429         printf("uvd_fw_version = %u\n", info->uvd_fw_version);
 430         printf("vce_fw_version = %u\n", info->vce_fw_version);
 431         printf("me_fw_version = %i\n", info->me_fw_version);
 432         printf("me_fw_feature = %i\n", info->me_fw_feature);
 433         printf("pfp_fw_version = %i\n", info->pfp_fw_version);
 434         printf("pfp_fw_feature = %i\n", info->pfp_fw_feature);
 435         printf("ce_fw_version = %i\n", info->ce_fw_version);
 436         printf("ce_fw_feature = %i\n", info->ce_fw_feature);
 437         printf("vce_harvest_config = %i\n", info->vce_harvest_config);
 438         printf("clock_crystal_freq = %i\n", info->clock_crystal_freq);
 439         printf("tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
 440         printf("drm = %i.%i.%i\n", info->drm_major,
 441                info->drm_minor, info->drm_patchlevel);
 442         printf("has_userptr = %i\n", info->has_userptr);
 443         printf("has_syncobj = %u\n", info->has_syncobj);
 444         printf("has_fence_to_handle = %u\n", info->has_fence_to_handle);
 445
 446         printf("r600_max_quad_pipes = %i\n", info->r600_max_quad_pipes);
 447         printf("max_shader_clock = %i\n", info->max_shader_clock);
 448         printf("num_good_compute_units = %i\n", info->num_good_compute_units);
 449         printf("max_se = %i\n", info->max_se);
 450         printf("max_sh_per_se = %i\n", info->max_sh_per_se);
 451
 452         printf("r600_gb_backend_map = %i\n", info->r600_gb_backend_map);
 453         printf("r600_gb_backend_map_valid = %i\n", info->r600_gb_backend_map_valid);
 454         printf("r600_num_banks = %i\n", info->r600_num_banks);
 455         printf("num_render_backends = %i\n", info->num_render_backends);
 456         printf("num_tile_pipes = %i\n", info->num_tile_pipes);
 457         printf("pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
 458         printf("enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
 459         printf("max_alignment = %u\n", (unsigned)info->max_alignment);
 460 }