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amd: Add detection of timeline semaphore support.
[mesa.git] / src / amd / common / ac_gpu_info.c
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27 #include "addrlib/src/amdgpu_asic_addr.h"
28 #include "sid.h"
29
30 #include "util/macros.h"
31 #include "util/u_math.h"
32
33 #include <stdio.h>
34
35 #include <xf86drm.h>
36 #include "drm-uapi/amdgpu_drm.h"
37
38 #include <amdgpu.h>
39
40 #define CIK_TILE_MODE_COLOR_2D 14
41
42 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
55 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
56 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
57
58 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
59 {
60 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
61
62 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
63 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
64 return 2;
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
67 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
68 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
69 return 4;
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
75 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
76 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
77 return 8;
78 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
79 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
80 return 16;
81 default:
82 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
83 assert(!"this should never occur");
84 return 2;
85 }
86 }
87
88 static bool has_syncobj(int fd)
89 {
90 uint64_t value;
91 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
92 return false;
93 return value ? true : false;
94 }
95
96 static bool has_timeline_syncobj(int fd)
97 {
98 uint64_t value;
99 if (drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &value))
100 return false;
101 return value ? true : false;
102 }
103
104 static uint64_t fix_vram_size(uint64_t size)
105 {
106 /* The VRAM size is underreported, so we need to fix it, because
107 * it's used to compute the number of memory modules for harvesting.
108 */
109 return align64(size, 256*1024*1024);
110 }
111
112 static uint32_t
113 get_l2_cache_size(enum radeon_family family)
114 {
115 switch (family) {
116 case CHIP_KABINI:
117 case CHIP_STONEY:
118 return 128 * 1024;
119 case CHIP_OLAND:
120 case CHIP_HAINAN:
121 case CHIP_ICELAND:
122 return 256 * 1024;
123 case CHIP_PITCAIRN:
124 case CHIP_VERDE:
125 case CHIP_BONAIRE:
126 case CHIP_KAVERI:
127 case CHIP_POLARIS12:
128 case CHIP_CARRIZO:
129 return 512 * 1024;
130 case CHIP_TAHITI:
131 case CHIP_TONGA:
132 return 768 * 1024;
133 break;
134 case CHIP_HAWAII:
135 case CHIP_POLARIS11:
136 return 1024 * 1024;
137 case CHIP_FIJI:
138 case CHIP_POLARIS10:
139 return 2048 * 1024;
140 break;
141 default:
142 return 4096 * 1024;
143 }
144 }
145
146 bool ac_query_gpu_info(int fd, void *dev_p,
147 struct radeon_info *info,
148 struct amdgpu_gpu_info *amdinfo)
149 {
150 struct drm_amdgpu_info_device device_info = {};
151 struct amdgpu_buffer_size_alignments alignment_info = {};
152 struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
153 struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_jpeg = {};
154 struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
155 struct amdgpu_gds_resource_info gds = {};
156 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
157 int r, i, j;
158 amdgpu_device_handle dev = dev_p;
159 drmDevicePtr devinfo;
160
161 /* Get PCI info. */
162 r = drmGetDevice2(fd, 0, &devinfo);
163 if (r) {
164 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
165 return false;
166 }
167 info->pci_domain = devinfo->businfo.pci->domain;
168 info->pci_bus = devinfo->businfo.pci->bus;
169 info->pci_dev = devinfo->businfo.pci->dev;
170 info->pci_func = devinfo->businfo.pci->func;
171 drmFreeDevice(&devinfo);
172
173 assert(info->drm_major == 3);
174 info->is_amdgpu = true;
175
176 /* Query hardware and driver information. */
177 r = amdgpu_query_gpu_info(dev, amdinfo);
178 if (r) {
179 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
180 return false;
181 }
182
183 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
184 &device_info);
185 if (r) {
186 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
187 return false;
188 }
189
190 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
191 if (r) {
192 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
193 return false;
194 }
195
196 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
197 if (r) {
198 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
199 return false;
200 }
201
202 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
203 if (r) {
204 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
205 return false;
206 }
207
208 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
209 if (r) {
210 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
211 return false;
212 }
213
214 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
215 if (r) {
216 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
217 return false;
218 }
219
220 if (info->drm_minor >= 17) {
221 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
222 if (r) {
223 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
224 return false;
225 }
226 }
227
228 if (info->drm_minor >= 17) {
229 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
230 if (r) {
231 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
232 return false;
233 }
234 }
235
236 if (info->drm_minor >= 17) {
237 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
238 if (r) {
239 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
240 return false;
241 }
242 }
243
244 if (info->drm_minor >= 27) {
245 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
246 if (r) {
247 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
248 return false;
249 }
250 }
251
252 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
253 &info->me_fw_version,
254 &info->me_fw_feature);
255 if (r) {
256 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
257 return false;
258 }
259
260 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
261 &info->pfp_fw_version,
262 &info->pfp_fw_feature);
263 if (r) {
264 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
265 return false;
266 }
267
268 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
269 &info->ce_fw_version,
270 &info->ce_fw_feature);
271 if (r) {
272 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
273 return false;
274 }
275
276 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
277 &uvd_version, &uvd_feature);
278 if (r) {
279 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
280 return false;
281 }
282
283 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
284 if (r) {
285 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
286 return false;
287 }
288
289 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
290 &vce_version, &vce_feature);
291 if (r) {
292 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
293 return false;
294 }
295
296 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
297 if (r) {
298 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
299 return false;
300 }
301
302 r = amdgpu_query_gds_info(dev, &gds);
303 if (r) {
304 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
305 return false;
306 }
307
308 if (info->drm_minor >= 9) {
309 struct drm_amdgpu_memory_info meminfo = {};
310
311 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
312 if (r) {
313 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
314 return false;
315 }
316
317 /* Note: usable_heap_size values can be random and can't be relied on. */
318 info->gart_size = meminfo.gtt.total_heap_size;
319 info->vram_size = fix_vram_size(meminfo.vram.total_heap_size);
320 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
321 } else {
322 /* This is a deprecated interface, which reports usable sizes
323 * (total minus pinned), but the pinned size computation is
324 * buggy, so the values returned from these functions can be
325 * random.
326 */
327 struct amdgpu_heap_info vram, vram_vis, gtt;
328
329 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
330 if (r) {
331 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
332 return false;
333 }
334
335 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
336 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
337 &vram_vis);
338 if (r) {
339 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
340 return false;
341 }
342
343 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
344 if (r) {
345 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
346 return false;
347 }
348
349 info->gart_size = gtt.heap_size;
350 info->vram_size = fix_vram_size(vram.heap_size);
351 info->vram_vis_size = vram_vis.heap_size;
352 }
353
354 /* Set chip identification. */
355 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
356 info->pci_rev_id = amdinfo->pci_rev_id;
357 info->vce_harvest_config = amdinfo->vce_harvest_config;
358
359 #define identify_chip2(asic, chipname) \
360 if (ASICREV_IS(amdinfo->chip_external_rev, asic)) { \
361 info->family = CHIP_##chipname; \
362 info->name = #chipname; \
363 }
364 #define identify_chip(chipname) identify_chip2(chipname, chipname)
365
366 switch (amdinfo->family_id) {
367 case FAMILY_SI:
368 identify_chip(TAHITI);
369 identify_chip(PITCAIRN);
370 identify_chip2(CAPEVERDE, VERDE);
371 identify_chip(OLAND);
372 identify_chip(HAINAN);
373 break;
374 case FAMILY_CI:
375 identify_chip(BONAIRE);
376 identify_chip(HAWAII);
377 break;
378 case FAMILY_KV:
379 identify_chip2(SPECTRE, KAVERI);
380 identify_chip2(SPOOKY, KAVERI);
381 identify_chip2(KALINDI, KABINI);
382 identify_chip2(GODAVARI, KABINI);
383 break;
384 case FAMILY_VI:
385 identify_chip(ICELAND);
386 identify_chip(TONGA);
387 identify_chip(FIJI);
388 identify_chip(POLARIS10);
389 identify_chip(POLARIS11);
390 identify_chip(POLARIS12);
391 identify_chip(VEGAM);
392 break;
393 case FAMILY_CZ:
394 identify_chip(CARRIZO);
395 identify_chip(STONEY);
396 break;
397 case FAMILY_AI:
398 identify_chip(VEGA10);
399 identify_chip(VEGA12);
400 identify_chip(VEGA20);
401 identify_chip(ARCTURUS);
402 break;
403 case FAMILY_RV:
404 identify_chip(RAVEN);
405 identify_chip(RAVEN2);
406 identify_chip(RENOIR);
407 break;
408 case FAMILY_NV:
409 identify_chip(NAVI10);
410 identify_chip(NAVI12);
411 identify_chip(NAVI14);
412 identify_chip(SIENNA);
413 break;
414 }
415
416 if (!info->name) {
417 fprintf(stderr, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
418 amdinfo->family_id, amdinfo->chip_external_rev);
419 return false;
420 }
421
422 if (info->family >= CHIP_SIENNA)
423 info->chip_class = GFX10_3;
424 else if (info->family >= CHIP_NAVI10)
425 info->chip_class = GFX10;
426 else if (info->family >= CHIP_VEGA10)
427 info->chip_class = GFX9;
428 else if (info->family >= CHIP_TONGA)
429 info->chip_class = GFX8;
430 else if (info->family >= CHIP_BONAIRE)
431 info->chip_class = GFX7;
432 else if (info->family >= CHIP_TAHITI)
433 info->chip_class = GFX6;
434 else {
435 fprintf(stderr, "amdgpu: Unknown family.\n");
436 return false;
437 }
438
439 info->family_id = amdinfo->family_id;
440 info->chip_external_rev = amdinfo->chip_external_rev;
441 info->marketing_name = amdgpu_get_marketing_name(dev);
442 info->is_pro_graphics = info->marketing_name &&
443 (!strcmp(info->marketing_name, "Pro") ||
444 !strcmp(info->marketing_name, "PRO") ||
445 !strcmp(info->marketing_name, "Frontier"));
446
447 /* Set which chips have dedicated VRAM. */
448 info->has_dedicated_vram =
449 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
450
451 /* The kernel can split large buffers in VRAM but not in GTT, so large
452 * allocations can fail or cause buffer movement failures in the kernel.
453 */
454 if (info->has_dedicated_vram)
455 info->max_alloc_size = info->vram_size * 0.8;
456 else
457 info->max_alloc_size = info->gart_size * 0.7;
458
459 info->vram_type = amdinfo->vram_type;
460 info->vram_bit_width = amdinfo->vram_bit_width;
461 info->ce_ram_size = amdinfo->ce_ram_size;
462
463 info->l2_cache_size = get_l2_cache_size(info->family);
464 info->l1_cache_size = 16384;
465
466 /* Set which chips have uncached device memory. */
467 info->has_l2_uncached = info->chip_class >= GFX9;
468
469 /* Set hardware information. */
470 info->gds_size = gds.gds_total_size;
471 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
472 /* convert the shader/memory clocks from KHz to MHz */
473 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
474 info->max_memory_clock = amdinfo->max_memory_clk / 1000;
475 info->num_tcc_blocks = device_info.num_tcc_blocks;
476 info->max_se = amdinfo->num_shader_engines;
477 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
478 info->has_hw_decode =
479 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
480 (vcn_jpeg.available_rings != 0);
481 info->uvd_fw_version =
482 uvd.available_rings ? uvd_version : 0;
483 info->vce_fw_version =
484 vce.available_rings ? vce_version : 0;
485 info->uvd_enc_supported =
486 uvd_enc.available_rings ? true : false;
487 info->has_userptr = true;
488 info->has_syncobj = has_syncobj(fd);
489 info->has_timeline_syncobj = has_timeline_syncobj(fd);
490 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
491 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
492 info->has_ctx_priority = info->drm_minor >= 22;
493 info->has_local_buffers = info->drm_minor >= 20;
494 info->kernel_flushes_hdp_before_ib = true;
495 info->htile_cmask_support_1d_tiling = true;
496 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
497 info->has_bo_metadata = true;
498 info->has_gpu_reset_status_query = true;
499 info->has_eqaa_surface_allocator = true;
500 info->has_format_bc1_through_bc7 = true;
501 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
502 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 ||
503 info->drm_minor >= 2;
504 info->has_indirect_compute_dispatch = true;
505 /* GFX6 doesn't support unaligned loads. */
506 info->has_unaligned_shader_loads = info->chip_class != GFX6;
507 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
508 * these faults are mitigated in software.
509 */
510 info->has_sparse_vm_mappings = info->chip_class >= GFX7 && info->drm_minor >= 13;
511 info->has_2d_tiling = true;
512 info->has_read_registers_query = true;
513 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
514 info->mid_command_buffer_preemption_enabled =
515 amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
516
517 info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
518 info->num_render_backends = amdinfo->rb_pipes;
519 /* The value returned by the kernel driver was wrong. */
520 if (info->family == CHIP_KAVERI)
521 info->num_render_backends = 2;
522
523 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
524 if (!info->clock_crystal_freq) {
525 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
526 info->clock_crystal_freq = 1;
527 }
528 if (info->chip_class >= GFX10) {
529 info->tcc_cache_line_size = 128;
530
531 if (info->drm_minor >= 35) {
532 info->tcc_harvested = device_info.tcc_disabled_mask != 0;
533 } else {
534 /* This is a hack, but it's all we can do without a kernel upgrade. */
535 info->tcc_harvested =
536 (info->vram_size / info->num_tcc_blocks) != 512*1024*1024;
537 }
538 } else {
539 info->tcc_cache_line_size = 64;
540 }
541 info->gb_addr_config = amdinfo->gb_addr_cfg;
542 if (info->chip_class == GFX9) {
543 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
544 info->pipe_interleave_bytes =
545 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
546 } else {
547 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
548 info->pipe_interleave_bytes =
549 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
550 }
551 info->r600_has_virtual_memory = true;
552
553 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
554 * 16KB makes some SIMDs unoccupied).
555 *
556 * LDS is 128KB in WGP mode and 64KB in CU mode. Assume the WGP mode is used.
557 */
558 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024;
559 info->lds_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4;
560
561 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
562 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
563
564 info->has_graphics = gfx.available_rings > 0;
565 info->num_rings[RING_GFX] = util_bitcount(gfx.available_rings);
566 info->num_rings[RING_COMPUTE] = util_bitcount(compute.available_rings);
567 info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);
568 info->num_rings[RING_UVD] = util_bitcount(uvd.available_rings);
569 info->num_rings[RING_VCE] = util_bitcount(vce.available_rings);
570 info->num_rings[RING_UVD_ENC] = util_bitcount(uvd_enc.available_rings);
571 info->num_rings[RING_VCN_DEC] = util_bitcount(vcn_dec.available_rings);
572 info->num_rings[RING_VCN_ENC] = util_bitcount(vcn_enc.available_rings);
573 info->num_rings[RING_VCN_JPEG] = util_bitcount(vcn_jpeg.available_rings);
574
575 /* This is "align_mask" copied from the kernel, maximums of all IP versions. */
576 info->ib_pad_dw_mask[RING_GFX] = 0xff;
577 info->ib_pad_dw_mask[RING_COMPUTE] = 0xff;
578 info->ib_pad_dw_mask[RING_DMA] = 0xf;
579 info->ib_pad_dw_mask[RING_UVD] = 0xf;
580 info->ib_pad_dw_mask[RING_VCE] = 0x3f;
581 info->ib_pad_dw_mask[RING_UVD_ENC] = 0x3f;
582 info->ib_pad_dw_mask[RING_VCN_DEC] = 0xf;
583 info->ib_pad_dw_mask[RING_VCN_ENC] = 0x3f;
584 info->ib_pad_dw_mask[RING_VCN_JPEG] = 0xf;
585
586 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
587 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
588 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
589 */
590 info->has_clear_state = info->chip_class >= GFX7;
591
592 info->has_distributed_tess = info->chip_class >= GFX10 ||
593 (info->chip_class >= GFX8 && info->max_se >= 2);
594
595 info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
596 info->family == CHIP_RENOIR ||
597 info->chip_class >= GFX10;
598
599 info->has_rbplus = info->family == CHIP_STONEY ||
600 info->chip_class >= GFX9;
601
602 /* Some chips have RB+ registers, but don't support RB+. Those must
603 * always disable it.
604 */
605 info->rbplus_allowed = info->has_rbplus &&
606 (info->family == CHIP_STONEY ||
607 info->family == CHIP_VEGA12 ||
608 info->family == CHIP_RAVEN ||
609 info->family == CHIP_RAVEN2 ||
610 info->family == CHIP_RENOIR ||
611 info->chip_class >= GFX10_3);
612
613 info->has_out_of_order_rast = info->chip_class >= GFX8 &&
614 info->chip_class <= GFX9 &&
615 info->max_se >= 2;
616
617 /* Whether chips support double rate packed math instructions. */
618 info->has_packed_math_16bit = info->chip_class >= GFX9;
619
620 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
621 info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
622 (info->chip_class >= GFX8 &&
623 info->me_fw_feature >= 41);
624
625 info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
626
627 info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 ||
628 info->family == CHIP_RAVEN;
629
630 info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 &&
631 info->chip_class <= GFX9;
632
633 info->has_msaa_sample_loc_bug = (info->family >= CHIP_POLARIS10 &&
634 info->family <= CHIP_POLARIS12) ||
635 info->family == CHIP_VEGA10 ||
636 info->family == CHIP_RAVEN;
637
638 info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 ||
639 info->family == CHIP_RAVEN;
640
641 /* Get the number of good compute units. */
642 info->num_good_compute_units = 0;
643 for (i = 0; i < info->max_se; i++) {
644 for (j = 0; j < info->max_sh_per_se; j++) {
645 /*
646 * The cu bitmap in amd gpu info structure is
647 * 4x4 size array, and it's usually suitable for Vega
648 * ASICs which has 4*2 SE/SH layout.
649 * But for Arcturus, SE/SH layout is changed to 8*1.
650 * To mostly reduce the impact, we make it compatible
651 * with current bitmap array as below:
652 * SE4,SH0 --> cu_bitmap[0][1]
653 * SE5,SH0 --> cu_bitmap[1][1]
654 * SE6,SH0 --> cu_bitmap[2][1]
655 * SE7,SH0 --> cu_bitmap[3][1]
656 */
657 info->cu_mask[i%4][j+i/4] = amdinfo->cu_bitmap[i%4][j+i/4];
658 info->num_good_compute_units +=
659 util_bitcount(info->cu_mask[i][j]);
660 }
661 }
662
663 /* On GFX10, only whole WGPs (in units of 2 CUs) can be disabled,
664 * and max - min <= 2.
665 */
666 unsigned cu_group = info->chip_class >= GFX10 ? 2 : 1;
667 info->max_good_cu_per_sa = DIV_ROUND_UP(info->num_good_compute_units,
668 (info->max_se * info->max_sh_per_se * cu_group)) * cu_group;
669 info->min_good_cu_per_sa = (info->num_good_compute_units /
670 (info->max_se * info->max_sh_per_se * cu_group)) * cu_group;
671
672 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
673 sizeof(amdinfo->gb_tile_mode));
674 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
675
676 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
677 sizeof(amdinfo->gb_macro_tile_mode));
678
679 info->pte_fragment_size = alignment_info.size_local;
680 info->gart_page_size = alignment_info.size_remote;
681
682 if (info->chip_class == GFX6)
683 info->gfx_ib_pad_with_type2 = true;
684
685 unsigned ib_align = 0;
686 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
687 ib_align = MAX2(ib_align, gfx.ib_size_alignment);
688 ib_align = MAX2(ib_align, compute.ib_start_alignment);
689 ib_align = MAX2(ib_align, compute.ib_size_alignment);
690 ib_align = MAX2(ib_align, dma.ib_start_alignment);
691 ib_align = MAX2(ib_align, dma.ib_size_alignment);
692 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
693 ib_align = MAX2(ib_align, uvd.ib_size_alignment);
694 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
695 ib_align = MAX2(ib_align, uvd_enc.ib_size_alignment);
696 ib_align = MAX2(ib_align, vce.ib_start_alignment);
697 ib_align = MAX2(ib_align, vce.ib_size_alignment);
698 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
699 ib_align = MAX2(ib_align, vcn_dec.ib_size_alignment);
700 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
701 ib_align = MAX2(ib_align, vcn_enc.ib_size_alignment);
702 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
703 ib_align = MAX2(ib_align, vcn_jpeg.ib_size_alignment);
704 /* GFX10 and maybe GFX9 need this alignment for cache coherency. */
705 if (info->chip_class >= GFX9)
706 ib_align = MAX2(ib_align, info->tcc_cache_line_size);
707 /* The kernel pads gfx and compute IBs to 256 dwords since:
708 * 66f3b2d527154bd258a57c8815004b5964aa1cf5
709 * Do the same.
710 */
711 ib_align = MAX2(ib_align, 1024);
712 info->ib_alignment = ib_align;
713
714 if ((info->drm_minor >= 31 &&
715 (info->family == CHIP_RAVEN ||
716 info->family == CHIP_RAVEN2 ||
717 info->family == CHIP_RENOIR)) ||
718 (info->drm_minor >= 34 &&
719 (info->family == CHIP_NAVI12 ||
720 info->family == CHIP_NAVI14))) {
721 if (info->num_render_backends == 1)
722 info->use_display_dcc_unaligned = true;
723 else
724 info->use_display_dcc_with_retile_blit = true;
725 }
726
727 info->has_gds_ordered_append = info->chip_class >= GFX7 &&
728 info->drm_minor >= 29;
729
730 if (info->chip_class >= GFX9) {
731 unsigned pc_lines = 0;
732
733 switch (info->family) {
734 case CHIP_VEGA10:
735 case CHIP_VEGA12:
736 case CHIP_VEGA20:
737 pc_lines = 2048;
738 break;
739 case CHIP_RAVEN:
740 case CHIP_RAVEN2:
741 case CHIP_RENOIR:
742 case CHIP_NAVI10:
743 case CHIP_NAVI12:
744 case CHIP_SIENNA:
745 pc_lines = 1024;
746 break;
747 case CHIP_NAVI14:
748 pc_lines = 512;
749 break;
750 case CHIP_ARCTURUS:
751 break;
752 default:
753 assert(0);
754 }
755
756 info->pc_lines = pc_lines;
757
758 if (info->chip_class >= GFX10) {
759 info->pbb_max_alloc_count = pc_lines / 3;
760 } else {
761 info->pbb_max_alloc_count =
762 MIN2(128, pc_lines / (4 * info->max_se));
763 }
764 }
765
766 /* The number of SDPs is the same as the number of TCCs for now. */
767 if (info->chip_class >= GFX10)
768 info->num_sdp_interfaces = device_info.num_tcc_blocks;
769
770 if (info->chip_class >= GFX10_3)
771 info->max_wave64_per_simd = 16;
772 else if (info->chip_class == GFX10)
773 info->max_wave64_per_simd = 20;
774 else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
775 info->max_wave64_per_simd = 8;
776 else
777 info->max_wave64_per_simd = 10;
778
779 if (info->chip_class >= GFX10) {
780 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd;
781 info->min_sgpr_alloc = 128;
782 info->sgpr_alloc_granularity = 128;
783 /* Don't use late alloc on small chips. */
784 info->use_late_alloc = info->num_render_backends > 4;
785 } else if (info->chip_class >= GFX8) {
786 info->num_physical_sgprs_per_simd = 800;
787 info->min_sgpr_alloc = 16;
788 info->sgpr_alloc_granularity = 16;
789 info->use_late_alloc = true;
790 } else {
791 info->num_physical_sgprs_per_simd = 512;
792 info->min_sgpr_alloc = 8;
793 info->sgpr_alloc_granularity = 8;
794 /* Potential hang on Kabini: */
795 info->use_late_alloc = info->family != CHIP_KABINI;
796 }
797
798 info->max_sgpr_alloc = info->family == CHIP_TONGA ||
799 info->family == CHIP_ICELAND ? 96 : 104;
800
801 info->min_wave64_vgpr_alloc = 4;
802 info->max_vgpr_alloc = 256;
803 info->wave64_vgpr_alloc_granularity = 4;
804
805 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
806 info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
807
808 return true;
809 }
810
811 void ac_compute_driver_uuid(char *uuid, size_t size)
812 {
813 char amd_uuid[] = "AMD-MESA-DRV";
814
815 assert(size >= sizeof(amd_uuid));
816
817 memset(uuid, 0, size);
818 strncpy(uuid, amd_uuid, size);
819 }
820
821 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
822 {
823 uint32_t *uint_uuid = (uint32_t*)uuid;
824
825 assert(size >= sizeof(uint32_t)*4);
826
827 /**
828 * Use the device info directly instead of using a sha1. GL/VK UUIDs
829 * are 16 byte vs 20 byte for sha1, and the truncation that would be
830 * required would get rid of part of the little entropy we have.
831 * */
832 memset(uuid, 0, size);
833 uint_uuid[0] = info->pci_domain;
834 uint_uuid[1] = info->pci_bus;
835 uint_uuid[2] = info->pci_dev;
836 uint_uuid[3] = info->pci_func;
837 }
838
839 void ac_print_gpu_info(struct radeon_info *info)
840 {
841 printf("Device info:\n");
842 printf(" pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
843 info->pci_domain, info->pci_bus,
844 info->pci_dev, info->pci_func);
845
846 printf(" name = %s\n", info->name);
847 printf(" marketing_name = %s\n", info->marketing_name);
848 printf(" is_pro_graphics = %u\n", info->is_pro_graphics);
849 printf(" pci_id = 0x%x\n", info->pci_id);
850 printf(" pci_rev_id = 0x%x\n", info->pci_rev_id);
851 printf(" family = %i\n", info->family);
852 printf(" chip_class = %i\n", info->chip_class);
853 printf(" family_id = %i\n", info->family_id);
854 printf(" chip_external_rev = %i\n", info->chip_external_rev);
855 printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
856
857 printf("Features:\n");
858 printf(" has_graphics = %i\n", info->has_graphics);
859 printf(" num_rings[RING_GFX] = %i\n", info->num_rings[RING_GFX]);
860 printf(" num_rings[RING_DMA] = %i\n", info->num_rings[RING_DMA]);
861 printf(" num_rings[RING_COMPUTE] = %u\n", info->num_rings[RING_COMPUTE]);
862 printf(" num_rings[RING_UVD] = %i\n", info->num_rings[RING_UVD]);
863 printf(" num_rings[RING_VCE] = %i\n", info->num_rings[RING_VCE]);
864 printf(" num_rings[RING_UVD_ENC] = %i\n", info->num_rings[RING_UVD_ENC]);
865 printf(" num_rings[RING_VCN_DEC] = %i\n", info->num_rings[RING_VCN_DEC]);
866 printf(" num_rings[RING_VCN_ENC] = %i\n", info->num_rings[RING_VCN_ENC]);
867 printf(" num_rings[RING_VCN_JPEG] = %i\n", info->num_rings[RING_VCN_JPEG]);
868 printf(" has_clear_state = %u\n", info->has_clear_state);
869 printf(" has_distributed_tess = %u\n", info->has_distributed_tess);
870 printf(" has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode);
871 printf(" has_rbplus = %u\n", info->has_rbplus);
872 printf(" rbplus_allowed = %u\n", info->rbplus_allowed);
873 printf(" has_load_ctx_reg_pkt = %u\n", info->has_load_ctx_reg_pkt);
874 printf(" has_out_of_order_rast = %u\n", info->has_out_of_order_rast);
875 printf(" cpdma_prefetch_writes_memory = %u\n", info->cpdma_prefetch_writes_memory);
876 printf(" has_gfx9_scissor_bug = %i\n", info->has_gfx9_scissor_bug);
877 printf(" has_tc_compat_zrange_bug = %i\n", info->has_tc_compat_zrange_bug);
878 printf(" has_msaa_sample_loc_bug = %i\n", info->has_msaa_sample_loc_bug);
879 printf(" has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug);
880
881 printf("Display features:\n");
882 printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
883 printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
884
885 printf("Memory info:\n");
886 printf(" pte_fragment_size = %u\n", info->pte_fragment_size);
887 printf(" gart_page_size = %u\n", info->gart_page_size);
888 printf(" gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
889 printf(" vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
890 printf(" vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
891 printf(" vram_type = %i\n", info->vram_type);
892 printf(" vram_bit_width = %i\n", info->vram_bit_width);
893 printf(" gds_size = %u kB\n", info->gds_size / 1024);
894 printf(" gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
895 printf(" max_alloc_size = %i MB\n",
896 (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
897 printf(" min_alloc_size = %u\n", info->min_alloc_size);
898 printf(" address32_hi = %u\n", info->address32_hi);
899 printf(" has_dedicated_vram = %u\n", info->has_dedicated_vram);
900 printf(" num_sdp_interfaces = %u\n", info->num_sdp_interfaces);
901 printf(" num_tcc_blocks = %i\n", info->num_tcc_blocks);
902 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
903 printf(" tcc_harvested = %u\n", info->tcc_harvested);
904 printf(" pc_lines = %u\n", info->pc_lines);
905 printf(" lds_size_per_workgroup = %u\n", info->lds_size_per_workgroup);
906 printf(" lds_granularity = %i\n", info->lds_granularity);
907 printf(" max_memory_clock = %i\n", info->max_memory_clock);
908 printf(" ce_ram_size = %i\n", info->ce_ram_size);
909 printf(" l1_cache_size = %i\n", info->l1_cache_size);
910 printf(" l2_cache_size = %i\n", info->l2_cache_size);
911
912 printf("CP info:\n");
913 printf(" gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
914 printf(" ib_alignment = %u\n", info->ib_alignment);
915 printf(" me_fw_version = %i\n", info->me_fw_version);
916 printf(" me_fw_feature = %i\n", info->me_fw_feature);
917 printf(" pfp_fw_version = %i\n", info->pfp_fw_version);
918 printf(" pfp_fw_feature = %i\n", info->pfp_fw_feature);
919 printf(" ce_fw_version = %i\n", info->ce_fw_version);
920 printf(" ce_fw_feature = %i\n", info->ce_fw_feature);
921
922 printf("Multimedia info:\n");
923 printf(" has_hw_decode = %u\n", info->has_hw_decode);
924 printf(" uvd_enc_supported = %u\n", info->uvd_enc_supported);
925 printf(" uvd_fw_version = %u\n", info->uvd_fw_version);
926 printf(" vce_fw_version = %u\n", info->vce_fw_version);
927 printf(" vce_harvest_config = %i\n", info->vce_harvest_config);
928
929 printf("Kernel & winsys capabilities:\n");
930 printf(" drm = %i.%i.%i\n", info->drm_major,
931 info->drm_minor, info->drm_patchlevel);
932 printf(" has_userptr = %i\n", info->has_userptr);
933 printf(" has_syncobj = %u\n", info->has_syncobj);
934 printf(" has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
935 printf(" has_timeline_syncobj = %u\n", info->has_timeline_syncobj);
936 printf(" has_fence_to_handle = %u\n", info->has_fence_to_handle);
937 printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
938 printf(" has_local_buffers = %u\n", info->has_local_buffers);
939 printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
940 printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
941 printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
942 printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
943 printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
944 printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
945 printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
946 printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
947 printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
948 printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
949 printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
950 printf(" has_2d_tiling = %u\n", info->has_2d_tiling);
951 printf(" has_read_registers_query = %u\n", info->has_read_registers_query);
952 printf(" has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
953 printf(" has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
954 printf(" mid_command_buffer_preemption_enabled = %u\n", info->mid_command_buffer_preemption_enabled);
955
956 printf("Shader core info:\n");
957 printf(" max_shader_clock = %i\n", info->max_shader_clock);
958 printf(" num_good_compute_units = %i\n", info->num_good_compute_units);
959 printf(" max_good_cu_per_sa = %i\n", info->max_good_cu_per_sa);
960 printf(" min_good_cu_per_sa = %i\n", info->min_good_cu_per_sa);
961 printf(" max_se = %i\n", info->max_se);
962 printf(" max_sh_per_se = %i\n", info->max_sh_per_se);
963 printf(" max_wave64_per_simd = %i\n", info->max_wave64_per_simd);
964 printf(" num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd);
965 printf(" num_physical_wave64_vgprs_per_simd = %i\n", info->num_physical_wave64_vgprs_per_simd);
966 printf(" num_simd_per_compute_unit = %i\n", info->num_simd_per_compute_unit);
967 printf(" min_sgpr_alloc = %i\n", info->min_sgpr_alloc);
968 printf(" max_sgpr_alloc = %i\n", info->max_sgpr_alloc);
969 printf(" sgpr_alloc_granularity = %i\n", info->sgpr_alloc_granularity);
970 printf(" min_wave64_vgpr_alloc = %i\n", info->min_wave64_vgpr_alloc);
971 printf(" max_vgpr_alloc = %i\n", info->max_vgpr_alloc);
972 printf(" wave64_vgpr_alloc_granularity = %i\n", info->wave64_vgpr_alloc_granularity);
973
974 printf("Render backend info:\n");
975 printf(" pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
976 printf(" num_render_backends = %i\n", info->num_render_backends);
977 printf(" num_tile_pipes = %i\n", info->num_tile_pipes);
978 printf(" pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
979 printf(" enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
980 printf(" max_alignment = %u\n", (unsigned)info->max_alignment);
981 printf(" pbb_max_alloc_count = %u\n", info->pbb_max_alloc_count);
982
983 printf("GB_ADDR_CONFIG: 0x%08x\n", info->gb_addr_config);
984 if (info->chip_class >= GFX10) {
985 printf(" num_pipes = %u\n",
986 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
987 printf(" pipe_interleave_size = %u\n",
988 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
989 printf(" max_compressed_frags = %u\n",
990 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
991 } else if (info->chip_class == GFX9) {
992 printf(" num_pipes = %u\n",
993 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
994 printf(" pipe_interleave_size = %u\n",
995 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
996 printf(" max_compressed_frags = %u\n",
997 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
998 printf(" bank_interleave_size = %u\n",
999 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1000 printf(" num_banks = %u\n",
1001 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
1002 printf(" shader_engine_tile_size = %u\n",
1003 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1004 printf(" num_shader_engines = %u\n",
1005 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
1006 printf(" num_gpus = %u (raw)\n",
1007 G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
1008 printf(" multi_gpu_tile_size = %u (raw)\n",
1009 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1010 printf(" num_rb_per_se = %u\n",
1011 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
1012 printf(" row_size = %u\n",
1013 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1014 printf(" num_lower_pipes = %u (raw)\n",
1015 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1016 printf(" se_enable = %u (raw)\n",
1017 G_0098F8_SE_ENABLE(info->gb_addr_config));
1018 } else {
1019 printf(" num_pipes = %u\n",
1020 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1021 printf(" pipe_interleave_size = %u\n",
1022 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
1023 printf(" bank_interleave_size = %u\n",
1024 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1025 printf(" num_shader_engines = %u\n",
1026 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
1027 printf(" shader_engine_tile_size = %u\n",
1028 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1029 printf(" num_gpus = %u (raw)\n",
1030 G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
1031 printf(" multi_gpu_tile_size = %u (raw)\n",
1032 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1033 printf(" row_size = %u\n",
1034 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1035 printf(" num_lower_pipes = %u (raw)\n",
1036 G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1037 }
1038 }
1039
1040 int
1041 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
1042 {
1043 if (chip_class >= GFX9)
1044 return -1;
1045
1046 switch (family) {
1047 case CHIP_OLAND:
1048 case CHIP_HAINAN:
1049 case CHIP_KAVERI:
1050 case CHIP_KABINI:
1051 case CHIP_ICELAND:
1052 case CHIP_CARRIZO:
1053 case CHIP_STONEY:
1054 return 16;
1055 case CHIP_TAHITI:
1056 case CHIP_PITCAIRN:
1057 case CHIP_VERDE:
1058 case CHIP_BONAIRE:
1059 case CHIP_HAWAII:
1060 case CHIP_TONGA:
1061 case CHIP_FIJI:
1062 case CHIP_POLARIS10:
1063 case CHIP_POLARIS11:
1064 case CHIP_POLARIS12:
1065 case CHIP_VEGAM:
1066 return 32;
1067 default:
1068 unreachable("Unknown GPU");
1069 }
1070 }
1071
1072 void
1073 ac_get_raster_config(struct radeon_info *info,
1074 uint32_t *raster_config_p,
1075 uint32_t *raster_config_1_p,
1076 uint32_t *se_tile_repeat_p)
1077 {
1078 unsigned raster_config, raster_config_1, se_tile_repeat;
1079
1080 switch (info->family) {
1081 /* 1 SE / 1 RB */
1082 case CHIP_HAINAN:
1083 case CHIP_KABINI:
1084 case CHIP_STONEY:
1085 raster_config = 0x00000000;
1086 raster_config_1 = 0x00000000;
1087 break;
1088 /* 1 SE / 4 RBs */
1089 case CHIP_VERDE:
1090 raster_config = 0x0000124a;
1091 raster_config_1 = 0x00000000;
1092 break;
1093 /* 1 SE / 2 RBs (Oland is special) */
1094 case CHIP_OLAND:
1095 raster_config = 0x00000082;
1096 raster_config_1 = 0x00000000;
1097 break;
1098 /* 1 SE / 2 RBs */
1099 case CHIP_KAVERI:
1100 case CHIP_ICELAND:
1101 case CHIP_CARRIZO:
1102 raster_config = 0x00000002;
1103 raster_config_1 = 0x00000000;
1104 break;
1105 /* 2 SEs / 4 RBs */
1106 case CHIP_BONAIRE:
1107 case CHIP_POLARIS11:
1108 case CHIP_POLARIS12:
1109 raster_config = 0x16000012;
1110 raster_config_1 = 0x00000000;
1111 break;
1112 /* 2 SEs / 8 RBs */
1113 case CHIP_TAHITI:
1114 case CHIP_PITCAIRN:
1115 raster_config = 0x2a00126a;
1116 raster_config_1 = 0x00000000;
1117 break;
1118 /* 4 SEs / 8 RBs */
1119 case CHIP_TONGA:
1120 case CHIP_POLARIS10:
1121 raster_config = 0x16000012;
1122 raster_config_1 = 0x0000002a;
1123 break;
1124 /* 4 SEs / 16 RBs */
1125 case CHIP_HAWAII:
1126 case CHIP_FIJI:
1127 case CHIP_VEGAM:
1128 raster_config = 0x3a00161a;
1129 raster_config_1 = 0x0000002e;
1130 break;
1131 default:
1132 fprintf(stderr,
1133 "ac: Unknown GPU, using 0 for raster_config\n");
1134 raster_config = 0x00000000;
1135 raster_config_1 = 0x00000000;
1136 break;
1137 }
1138
1139 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
1140 * This decreases performance by up to 50% when the RB is the bottleneck.
1141 */
1142 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
1143 raster_config = 0x00000000;
1144
1145 /* Fiji: Old kernels have incorrect tiling config. This decreases
1146 * RB performance by 25%. (it disables 1 RB in the second packer)
1147 */
1148 if (info->family == CHIP_FIJI &&
1149 info->cik_macrotile_mode_array[0] == 0x000000e8) {
1150 raster_config = 0x16000012;
1151 raster_config_1 = 0x0000002a;
1152 }
1153
1154 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
1155 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
1156
1157 /* I don't know how to calculate this, though this is probably a good guess. */
1158 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
1159
1160 *raster_config_p = raster_config;
1161 *raster_config_1_p = raster_config_1;
1162 if (se_tile_repeat_p)
1163 *se_tile_repeat_p = se_tile_repeat;
1164 }
1165
1166 void
1167 ac_get_harvested_configs(struct radeon_info *info,
1168 unsigned raster_config,
1169 unsigned *cik_raster_config_1_p,
1170 unsigned *raster_config_se)
1171 {
1172 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
1173 unsigned num_se = MAX2(info->max_se, 1);
1174 unsigned rb_mask = info->enabled_rb_mask;
1175 unsigned num_rb = MIN2(info->num_render_backends, 16);
1176 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
1177 unsigned rb_per_se = num_rb / num_se;
1178 unsigned se_mask[4];
1179 unsigned se;
1180
1181 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1182 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1183 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1184 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1185
1186 assert(num_se == 1 || num_se == 2 || num_se == 4);
1187 assert(sh_per_se == 1 || sh_per_se == 2);
1188 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
1189
1190
1191 if (info->chip_class >= GFX7) {
1192 unsigned raster_config_1 = *cik_raster_config_1_p;
1193 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
1194 (!se_mask[2] && !se_mask[3]))) {
1195 raster_config_1 &= C_028354_SE_PAIR_MAP;
1196
1197 if (!se_mask[0] && !se_mask[1]) {
1198 raster_config_1 |=
1199 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
1200 } else {
1201 raster_config_1 |=
1202 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
1203 }
1204 *cik_raster_config_1_p = raster_config_1;
1205 }
1206 }
1207
1208 for (se = 0; se < num_se; se++) {
1209 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1210 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1211 int idx = (se / 2) * 2;
1212
1213 raster_config_se[se] = raster_config;
1214 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1215 raster_config_se[se] &= C_028350_SE_MAP;
1216
1217 if (!se_mask[idx]) {
1218 raster_config_se[se] |=
1219 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
1220 } else {
1221 raster_config_se[se] |=
1222 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
1223 }
1224 }
1225
1226 pkr0_mask &= rb_mask;
1227 pkr1_mask &= rb_mask;
1228 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1229 raster_config_se[se] &= C_028350_PKR_MAP;
1230
1231 if (!pkr0_mask) {
1232 raster_config_se[se] |=
1233 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
1234 } else {
1235 raster_config_se[se] |=
1236 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
1237 }
1238 }
1239
1240 if (rb_per_se >= 2) {
1241 unsigned rb0_mask = 1 << (se * rb_per_se);
1242 unsigned rb1_mask = rb0_mask << 1;
1243
1244 rb0_mask &= rb_mask;
1245 rb1_mask &= rb_mask;
1246 if (!rb0_mask || !rb1_mask) {
1247 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
1248
1249 if (!rb0_mask) {
1250 raster_config_se[se] |=
1251 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
1252 } else {
1253 raster_config_se[se] |=
1254 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
1255 }
1256 }
1257
1258 if (rb_per_se > 2) {
1259 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1260 rb1_mask = rb0_mask << 1;
1261 rb0_mask &= rb_mask;
1262 rb1_mask &= rb_mask;
1263 if (!rb0_mask || !rb1_mask) {
1264 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
1265
1266 if (!rb0_mask) {
1267 raster_config_se[se] |=
1268 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
1269 } else {
1270 raster_config_se[se] |=
1271 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
1272 }
1273 }
1274 }
1275 }
1276 }
1277 }
1278
1279 unsigned ac_get_compute_resource_limits(struct radeon_info *info,
1280 unsigned waves_per_threadgroup,
1281 unsigned max_waves_per_sh,
1282 unsigned threadgroups_per_cu)
1283 {
1284 unsigned compute_resource_limits =
1285 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
1286
1287 if (info->chip_class >= GFX7) {
1288 unsigned num_cu_per_se = info->num_good_compute_units /
1289 info->max_se;
1290
1291 /* Force even distribution on all SIMDs in CU if the workgroup
1292 * size is 64. This has shown some good improvements if # of CUs
1293 * per SE is not a multiple of 4.
1294 */
1295 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
1296 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
1297
1298 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
1299 compute_resource_limits |= S_00B854_WAVES_PER_SH(max_waves_per_sh) |
1300 S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
1301 } else {
1302 /* GFX6 */
1303 if (max_waves_per_sh) {
1304 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
1305 compute_resource_limits |= S_00B854_WAVES_PER_SH_SI(limit_div16);
1306 }
1307 }
1308 return compute_resource_limits;
1309 }