10b578a1ef991db7c2baf7f4a02babf1011dd54b
[mesa.git] / src / amd / common / ac_gpu_info.h
1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #ifndef AC_GPU_INFO_H
27 #define AC_GPU_INFO_H
28
29 #include <stddef.h>
30 #include <stdint.h>
31 #include <stdbool.h>
32 #include "amd_family.h"
33
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37
38 struct amdgpu_gpu_info;
39
40 struct radeon_info {
41 /* PCI info: domain:bus:dev:func */
42 uint32_t pci_domain;
43 uint32_t pci_bus;
44 uint32_t pci_dev;
45 uint32_t pci_func;
46
47 /* Device info. */
48 const char *name;
49 const char *marketing_name;
50 bool is_pro_graphics;
51 uint32_t pci_id;
52 enum radeon_family family;
53 enum chip_class chip_class;
54 uint32_t family_id;
55 uint32_t chip_external_rev;
56 bool has_graphics; /* false if the chip is compute-only */
57 uint32_t num_compute_rings;
58 uint32_t num_sdma_rings;
59 uint32_t clock_crystal_freq;
60 uint32_t tcc_cache_line_size;
61 bool has_clear_state;
62 bool has_distributed_tess;
63 bool has_dcc_constant_encode;
64
65 /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
66 /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
67 bool use_display_dcc_unaligned;
68 /* Allocate both aligned and unaligned DCC and use the retile blit. */
69 bool use_display_dcc_with_retile_blit;
70
71 /* Memory info. */
72 uint32_t pte_fragment_size;
73 uint32_t gart_page_size;
74 uint64_t gart_size;
75 uint64_t vram_size;
76 uint64_t vram_vis_size;
77 unsigned gds_size;
78 unsigned gds_gfx_partition_size;
79 uint64_t max_alloc_size;
80 uint32_t min_alloc_size;
81 uint32_t address32_hi;
82 bool has_dedicated_vram;
83 bool r600_has_virtual_memory;
84
85 /* CP info. */
86 bool gfx_ib_pad_with_type2;
87 unsigned ib_start_alignment;
88 uint32_t me_fw_version;
89 uint32_t me_fw_feature;
90 uint32_t pfp_fw_version;
91 uint32_t pfp_fw_feature;
92 uint32_t ce_fw_version;
93 uint32_t ce_fw_feature;
94
95 /* Multimedia info. */
96 bool has_hw_decode;
97 bool uvd_enc_supported;
98 uint32_t uvd_fw_version;
99 uint32_t vce_fw_version;
100 uint32_t vce_harvest_config;
101
102 /* Kernel & winsys capabilities. */
103 uint32_t drm_major; /* version */
104 uint32_t drm_minor;
105 uint32_t drm_patchlevel;
106 bool is_amdgpu;
107 bool has_userptr;
108 bool has_syncobj;
109 bool has_syncobj_wait_for_submit;
110 bool has_fence_to_handle;
111 bool has_ctx_priority;
112 bool has_local_buffers;
113 bool kernel_flushes_hdp_before_ib;
114 bool htile_cmask_support_1d_tiling;
115 bool si_TA_CS_BC_BASE_ADDR_allowed;
116 bool has_bo_metadata;
117 bool has_gpu_reset_status_query;
118 bool has_eqaa_surface_allocator;
119 bool has_format_bc1_through_bc7;
120 bool kernel_flushes_tc_l2_after_ib;
121 bool has_indirect_compute_dispatch;
122 bool has_unaligned_shader_loads;
123 bool has_sparse_vm_mappings;
124 bool has_2d_tiling;
125 bool has_read_registers_query;
126 bool has_gds_ordered_append;
127 bool has_scheduled_fence_dependency;
128
129 /* Shader cores. */
130 uint32_t r600_max_quad_pipes; /* wave size / 16 */
131 uint32_t max_shader_clock;
132 uint32_t num_good_compute_units;
133 uint32_t num_good_cu_per_sh;
134 uint32_t num_tcc_blocks;
135 uint32_t max_se; /* shader engines */
136 uint32_t max_sh_per_se; /* shader arrays per shader engine */
137
138 /* Render backends (color + depth blocks). */
139 uint32_t r300_num_gb_pipes;
140 uint32_t r300_num_z_pipes;
141 uint32_t r600_gb_backend_map; /* R600 harvest config */
142 bool r600_gb_backend_map_valid;
143 uint32_t r600_num_banks;
144 uint32_t gb_addr_config;
145 uint32_t pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */
146 uint32_t num_render_backends;
147 uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */
148 uint32_t pipe_interleave_bytes;
149 uint32_t enabled_rb_mask; /* GCN harvest config */
150 uint64_t max_alignment; /* from addrlib */
151
152 /* Tile modes. */
153 uint32_t si_tile_mode_array[32];
154 uint32_t cik_macrotile_mode_array[16];
155 };
156
157 bool ac_query_gpu_info(int fd, void *dev_p,
158 struct radeon_info *info,
159 struct amdgpu_gpu_info *amdinfo);
160
161 void ac_compute_driver_uuid(char *uuid, size_t size);
162
163 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
164 void ac_print_gpu_info(struct radeon_info *info);
165 int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family);
166 void ac_get_raster_config(struct radeon_info *info,
167 uint32_t *raster_config_p,
168 uint32_t *raster_config_1_p,
169 uint32_t *se_tile_repeat_p);
170 void ac_get_harvested_configs(struct radeon_info *info,
171 unsigned raster_config,
172 unsigned *cik_raster_config_1_p,
173 unsigned *raster_config_se);
174 unsigned ac_get_compute_resource_limits(struct radeon_info *info,
175 unsigned waves_per_threadgroup,
176 unsigned max_waves_per_sh,
177 unsigned threadgroups_per_cu);
178
179 static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
180 {
181
182 switch (family) {
183 /* These always have 8 waves: */
184 case CHIP_POLARIS10:
185 case CHIP_POLARIS11:
186 case CHIP_POLARIS12:
187 case CHIP_VEGAM:
188 return 8;
189 default:
190 return 10;
191 }
192 }
193
194 static inline uint32_t
195 ac_get_num_physical_sgprs(enum chip_class chip_class)
196 {
197 return chip_class >= GFX8 ? 800 : 512;
198 }
199
200 #ifdef __cplusplus
201 }
202 #endif
203
204 #endif /* AC_GPU_INFO_H */