2 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
32 #include "amd_family.h"
38 /* Prior to C11 the following may trigger a typedef redeclaration warning */
39 typedef struct amdgpu_device
*amdgpu_device_handle
;
40 struct amdgpu_gpu_info
;
43 /* PCI info: domain:bus:dev:func */
51 const char *marketing_name
;
54 enum radeon_family family
;
55 enum chip_class chip_class
;
56 uint32_t num_compute_rings
;
57 uint32_t num_sdma_rings
;
58 uint32_t clock_crystal_freq
;
59 uint32_t tcc_cache_line_size
;
61 /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
62 /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
63 bool use_display_dcc_unaligned
;
64 /* Allocate both aligned and unaligned DCC and use the retile blit. */
65 bool use_display_dcc_with_retile_blit
;
68 uint32_t pte_fragment_size
;
69 uint32_t gart_page_size
;
72 uint64_t vram_vis_size
;
74 unsigned gds_gfx_partition_size
;
75 uint64_t max_alloc_size
;
76 uint32_t min_alloc_size
;
77 uint32_t address32_hi
;
78 bool has_dedicated_vram
;
79 bool r600_has_virtual_memory
;
82 bool gfx_ib_pad_with_type2
;
83 unsigned ib_start_alignment
;
84 uint32_t me_fw_version
;
85 uint32_t me_fw_feature
;
86 uint32_t pfp_fw_version
;
87 uint32_t pfp_fw_feature
;
88 uint32_t ce_fw_version
;
89 uint32_t ce_fw_feature
;
91 /* Multimedia info. */
93 bool uvd_enc_supported
;
94 uint32_t uvd_fw_version
;
95 uint32_t vce_fw_version
;
96 uint32_t vce_harvest_config
;
98 /* Kernel & winsys capabilities. */
99 uint32_t drm_major
; /* version */
101 uint32_t drm_patchlevel
;
104 bool has_syncobj_wait_for_submit
;
105 bool has_fence_to_handle
;
106 bool has_ctx_priority
;
107 bool has_local_buffers
;
108 bool kernel_flushes_hdp_before_ib
;
109 bool htile_cmask_support_1d_tiling
;
110 bool si_TA_CS_BC_BASE_ADDR_allowed
;
111 bool has_bo_metadata
;
112 bool has_gpu_reset_status_query
;
113 bool has_eqaa_surface_allocator
;
114 bool has_format_bc1_through_bc7
;
115 bool kernel_flushes_tc_l2_after_ib
;
116 bool has_indirect_compute_dispatch
;
117 bool has_unaligned_shader_loads
;
118 bool has_sparse_vm_mappings
;
120 bool has_read_registers_query
;
121 bool has_gds_ordered_append
;
122 bool has_scheduled_fence_dependency
;
125 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
126 uint32_t max_shader_clock
;
127 uint32_t num_good_compute_units
;
128 uint32_t num_good_cu_per_sh
;
129 uint32_t num_tcc_blocks
;
130 uint32_t max_se
; /* shader engines */
131 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
133 /* Render backends (color + depth blocks). */
134 uint32_t r300_num_gb_pipes
;
135 uint32_t r300_num_z_pipes
;
136 uint32_t r600_gb_backend_map
; /* R600 harvest config */
137 bool r600_gb_backend_map_valid
;
138 uint32_t r600_num_banks
;
139 uint32_t gb_addr_config
;
140 uint32_t num_render_backends
;
141 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
142 uint32_t pipe_interleave_bytes
;
143 uint32_t enabled_rb_mask
; /* GCN harvest config */
144 uint64_t max_alignment
; /* from addrlib */
147 uint32_t si_tile_mode_array
[32];
148 uint32_t cik_macrotile_mode_array
[16];
151 bool ac_query_gpu_info(int fd
, amdgpu_device_handle dev
,
152 struct radeon_info
*info
,
153 struct amdgpu_gpu_info
*amdinfo
);
155 void ac_compute_driver_uuid(char *uuid
, size_t size
);
157 void ac_compute_device_uuid(struct radeon_info
*info
, char *uuid
, size_t size
);
158 void ac_print_gpu_info(struct radeon_info
*info
);
159 int ac_get_gs_table_depth(enum chip_class chip_class
, enum radeon_family family
);
160 void ac_get_raster_config(struct radeon_info
*info
,
161 uint32_t *raster_config_p
,
162 uint32_t *raster_config_1_p
,
163 uint32_t *se_tile_repeat_p
);
164 void ac_get_harvested_configs(struct radeon_info
*info
,
165 unsigned raster_config
,
166 unsigned *cik_raster_config_1_p
,
167 unsigned *raster_config_se
);
169 static inline unsigned ac_get_max_simd_waves(enum radeon_family family
)
173 /* These always have 8 waves: */
184 static inline uint32_t
185 ac_get_num_physical_sgprs(enum chip_class chip_class
)
187 return chip_class
>= GFX8
? 800 : 512;
194 #endif /* AC_GPU_INFO_H */