2 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
29 #include "amd_family.h"
38 /* PCI info: domain:bus:dev:func */
46 enum radeon_family family
;
47 enum chip_class chip_class
;
48 uint32_t pte_fragment_size
;
49 uint32_t gart_page_size
;
52 uint64_t vram_vis_size
;
53 uint64_t max_alloc_size
;
54 uint32_t min_alloc_size
;
55 bool has_dedicated_vram
;
56 bool has_virtual_memory
;
57 bool gfx_ib_pad_with_type2
;
59 uint32_t num_sdma_rings
;
60 uint32_t num_compute_rings
;
61 uint32_t uvd_fw_version
;
62 uint32_t vce_fw_version
;
63 uint32_t me_fw_version
;
64 uint32_t pfp_fw_version
;
65 uint32_t ce_fw_version
;
66 uint32_t vce_harvest_config
;
67 uint32_t clock_crystal_freq
;
68 uint32_t tcc_cache_line_size
;
71 uint32_t drm_major
; /* version */
73 uint32_t drm_patchlevel
;
77 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
78 uint32_t max_shader_clock
;
79 uint32_t num_good_compute_units
;
80 uint32_t max_se
; /* shader engines */
81 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
83 /* Render backends (color + depth blocks). */
84 uint32_t r300_num_gb_pipes
;
85 uint32_t r300_num_z_pipes
;
86 uint32_t r600_gb_backend_map
; /* R600 harvest config */
87 bool r600_gb_backend_map_valid
;
88 uint32_t r600_num_banks
;
89 uint32_t num_render_backends
;
90 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
91 uint32_t pipe_interleave_bytes
;
92 uint32_t enabled_rb_mask
; /* GCN harvest config */
95 uint32_t si_tile_mode_array
[32];
96 uint32_t cik_macrotile_mode_array
[16];
99 bool ac_query_gpu_info(int fd
, amdgpu_device_handle dev
,
100 struct radeon_info
*info
,
101 struct amdgpu_gpu_info
*amdinfo
);
107 #endif /* AC_GPU_INFO_H */