src/amd/common/ac_gpu_info.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_GPU_INFO_H
  27 #define AC_GPU_INFO_H
  28
  29 #include <stddef.h>
  30 #include <stdint.h>
  31 #include <stdbool.h>
  32 #include "amd_family.h"
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 struct amdgpu_gpu_info;
  39
  40 struct radeon_info {
  41         /* PCI info: domain:bus:dev:func */
  42         uint32_t                    pci_domain;
  43         uint32_t                    pci_bus;
  44         uint32_t                    pci_dev;
  45         uint32_t                    pci_func;
  46
  47         /* Device info. */
  48         const char                  *name;
  49         const char                  *marketing_name;
  50         bool                        is_pro_graphics;
  51         uint32_t                    pci_id;
  52         enum radeon_family          family;
  53         enum chip_class             chip_class;
  54         uint32_t                    family_id;
  55         uint32_t                    chip_external_rev;
  56         bool                        has_graphics; /* false if the chip is compute-only */
  57         uint32_t                    num_compute_rings;
  58         uint32_t                    num_sdma_rings;
  59         uint32_t                    clock_crystal_freq;
  60         uint32_t                    tcc_cache_line_size;
  61         bool                        has_clear_state;
  62         bool                        has_distributed_tess;
  63         bool                        has_dcc_constant_encode;
  64         bool                        has_rbplus; /* if RB+ registers exist */
  65         bool                        rbplus_allowed; /* if RB+ is allowed */
  66         bool                        has_load_ctx_reg_pkt;
  67         bool                        has_out_of_order_rast;
  68         bool                        cpdma_prefetch_writes_memory;
  69         uint32_t                    pbb_max_alloc_count;
  70
  71         /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
  72         /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
  73         bool                        use_display_dcc_unaligned;
  74         /* Allocate both aligned and unaligned DCC and use the retile blit. */
  75         bool                        use_display_dcc_with_retile_blit;
  76
  77         /* Memory info. */
  78         uint32_t                    pte_fragment_size;
  79         uint32_t                    gart_page_size;
  80         uint64_t                    gart_size;
  81         uint64_t                    vram_size;
  82         uint64_t                    vram_vis_size;
  83         unsigned                    gds_size;
  84         unsigned                    gds_gfx_partition_size;
  85         uint64_t                    max_alloc_size;
  86         uint32_t                    min_alloc_size;
  87         uint32_t                    address32_hi;
  88         bool                        has_dedicated_vram;
  89         bool                        r600_has_virtual_memory;
  90
  91         /* CP info. */
  92         bool                        gfx_ib_pad_with_type2;
  93         unsigned                    ib_start_alignment;
  94         uint32_t                    me_fw_version;
  95         uint32_t                    me_fw_feature;
  96         uint32_t                    pfp_fw_version;
  97         uint32_t                    pfp_fw_feature;
  98         uint32_t                    ce_fw_version;
  99         uint32_t                    ce_fw_feature;
 100
 101         /* Multimedia info. */
 102         bool                        has_hw_decode;
 103         bool                        uvd_enc_supported;
 104         uint32_t                    uvd_fw_version;
 105         uint32_t                    vce_fw_version;
 106         uint32_t                    vce_harvest_config;
 107
 108         /* Kernel & winsys capabilities. */
 109         uint32_t                    drm_major; /* version */
 110         uint32_t                    drm_minor;
 111         uint32_t                    drm_patchlevel;
 112         bool                        is_amdgpu;
 113         bool                        has_userptr;
 114         bool                        has_syncobj;
 115         bool                        has_syncobj_wait_for_submit;
 116         bool                        has_fence_to_handle;
 117         bool                        has_ctx_priority;
 118         bool                        has_local_buffers;
 119         bool                        kernel_flushes_hdp_before_ib;
 120         bool                        htile_cmask_support_1d_tiling;
 121         bool                        si_TA_CS_BC_BASE_ADDR_allowed;
 122         bool                        has_bo_metadata;
 123         bool                        has_gpu_reset_status_query;
 124         bool                        has_eqaa_surface_allocator;
 125         bool                        has_format_bc1_through_bc7;
 126         bool                        kernel_flushes_tc_l2_after_ib;
 127         bool                        has_indirect_compute_dispatch;
 128         bool                        has_unaligned_shader_loads;
 129         bool                        has_sparse_vm_mappings;
 130         bool                        has_2d_tiling;
 131         bool                        has_read_registers_query;
 132         bool                        has_gds_ordered_append;
 133         bool                        has_scheduled_fence_dependency;
 134
 135         /* Shader cores. */
 136         uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
 137         uint32_t                    max_shader_clock;
 138         uint32_t                    num_good_compute_units;
 139         uint32_t                    num_good_cu_per_sh;
 140         uint32_t                    num_tcc_blocks;
 141         uint32_t                    max_se; /* shader engines */
 142         uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
 143
 144         /* Render backends (color + depth blocks). */
 145         uint32_t                    r300_num_gb_pipes;
 146         uint32_t                    r300_num_z_pipes;
 147         uint32_t                    r600_gb_backend_map; /* R600 harvest config */
 148         bool                        r600_gb_backend_map_valid;
 149         uint32_t                    r600_num_banks;
 150         uint32_t                    gb_addr_config;
 151         uint32_t                    pa_sc_tile_steering_override; /* CLEAR_STATE also sets this */
 152         uint32_t                    num_render_backends;
 153         uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
 154         uint32_t                    pipe_interleave_bytes;
 155         uint32_t                    enabled_rb_mask; /* GCN harvest config */
 156         uint64_t                    max_alignment; /* from addrlib */
 157
 158         /* Tile modes. */
 159         uint32_t                    si_tile_mode_array[32];
 160         uint32_t                    cik_macrotile_mode_array[16];
 161
 162         /* Hardware bugs. */
 163         bool                        has_gfx9_scissor_bug;
 164         bool                        has_tc_compat_zrange_bug;
 165         bool                        has_msaa_sample_loc_bug;
 166         bool                        has_ls_vgpr_init_bug;
 167 };
 168
 169 bool ac_query_gpu_info(int fd, void *dev_p,
 170                        struct radeon_info *info,
 171                        struct amdgpu_gpu_info *amdinfo);
 172
 173 void ac_compute_driver_uuid(char *uuid, size_t size);
 174
 175 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
 176 void ac_print_gpu_info(struct radeon_info *info);
 177 int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family);
 178 void ac_get_raster_config(struct radeon_info *info,
 179                           uint32_t *raster_config_p,
 180                           uint32_t *raster_config_1_p,
 181                           uint32_t *se_tile_repeat_p);
 182 void ac_get_harvested_configs(struct radeon_info *info,
 183                               unsigned raster_config,
 184                               unsigned *cik_raster_config_1_p,
 185                               unsigned *raster_config_se);
 186 unsigned ac_get_compute_resource_limits(struct radeon_info *info,
 187                                         unsigned waves_per_threadgroup,
 188                                         unsigned max_waves_per_sh,
 189                                         unsigned threadgroups_per_cu);
 190
 191 static inline unsigned ac_get_max_wave64_per_simd(enum radeon_family family)
 192 {
 193
 194         switch (family) {
 195         /* These always have 8 waves: */
 196         case CHIP_POLARIS10:
 197         case CHIP_POLARIS11:
 198         case CHIP_POLARIS12:
 199         case CHIP_VEGAM:
 200                 return 8;
 201         default:
 202                 return 10;
 203         }
 204 }
 205
 206 static inline unsigned ac_get_num_physical_vgprs(enum chip_class chip_class,
 207                                                  unsigned wave_size)
 208 {
 209         /* The number is per SIMD. */
 210         if (chip_class >= GFX10)
 211                 return wave_size == 32 ? 1024 : 512;
 212         else
 213                 return 256;
 214 }
 215
 216 static inline uint32_t
 217 ac_get_num_physical_sgprs(const struct radeon_info *info)
 218 {
 219         /* The number is per SIMD. There is enough SGPRs for the maximum number
 220          * of Wave32, which is double the number for Wave64.
 221          */
 222         if (info->chip_class >= GFX10)
 223                 return 128 * ac_get_max_wave64_per_simd(info->family) * 2;
 224
 225         return info->chip_class >= GFX8 ? 800 : 512;
 226 }
 227
 228 #ifdef __cplusplus
 229 }
 230 #endif
 231
 232 #endif /* AC_GPU_INFO_H */