src/amd/common/ac_gpu_info.h

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #ifndef AC_GPU_INFO_H
  27 #define AC_GPU_INFO_H
  28
  29 #include <stddef.h>
  30 #include <stdint.h>
  31 #include <stdbool.h>
  32 #include "amd_family.h"
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 /* Prior to C11 the following may trigger a typedef redeclaration warning */
  39 typedef struct amdgpu_device *amdgpu_device_handle;
  40 struct amdgpu_gpu_info;
  41
  42 struct radeon_info {
  43         /* PCI info: domain:bus:dev:func */
  44         uint32_t                    pci_domain;
  45         uint32_t                    pci_bus;
  46         uint32_t                    pci_dev;
  47         uint32_t                    pci_func;
  48
  49         /* Device info. */
  50         uint32_t                    pci_id;
  51         enum radeon_family          family;
  52         enum chip_class             chip_class;
  53         uint32_t                    pte_fragment_size;
  54         uint32_t                    gart_page_size;
  55         uint64_t                    gart_size;
  56         uint64_t                    vram_size;
  57         uint64_t                    vram_vis_size;
  58         uint64_t                    max_alloc_size;
  59         uint32_t                    min_alloc_size;
  60         bool                        has_dedicated_vram;
  61         bool                        has_virtual_memory;
  62         bool                        gfx_ib_pad_with_type2;
  63         bool                        has_hw_decode;
  64         uint32_t                    num_sdma_rings;
  65         uint32_t                    num_compute_rings;
  66         uint32_t                    uvd_fw_version;
  67         uint32_t                    vce_fw_version;
  68         uint32_t                    me_fw_version;
  69         uint32_t                    pfp_fw_version;
  70         uint32_t                    ce_fw_version;
  71         uint32_t                    vce_harvest_config;
  72         uint32_t                    clock_crystal_freq;
  73         uint32_t                    tcc_cache_line_size;
  74
  75         /* Kernel info. */
  76         uint32_t                    drm_major; /* version */
  77         uint32_t                    drm_minor;
  78         uint32_t                    drm_patchlevel;
  79         bool                        has_userptr;
  80         bool                        has_syncobj;
  81
  82         /* Shader cores. */
  83         uint32_t                    r600_max_quad_pipes; /* wave size / 16 */
  84         uint32_t                    max_shader_clock;
  85         uint32_t                    num_good_compute_units;
  86         uint32_t                    max_se; /* shader engines */
  87         uint32_t                    max_sh_per_se; /* shader arrays per shader engine */
  88
  89         /* Render backends (color + depth blocks). */
  90         uint32_t                    r300_num_gb_pipes;
  91         uint32_t                    r300_num_z_pipes;
  92         uint32_t                    r600_gb_backend_map; /* R600 harvest config */
  93         bool                        r600_gb_backend_map_valid;
  94         uint32_t                    r600_num_banks;
  95         uint32_t                    num_render_backends;
  96         uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
  97         uint32_t                    pipe_interleave_bytes;
  98         uint32_t                    enabled_rb_mask; /* GCN harvest config */
  99         uint32_t                    pa_sc_raster_config[4]; /* per SE */
 100         uint32_t                    pa_sc_raster_config_1;
 101
 102         uint64_t                    max_alignment; /* from addrlib */
 103         /* Tile modes. */
 104         uint32_t                    si_tile_mode_array[32];
 105         uint32_t                    cik_macrotile_mode_array[16];
 106 };
 107
 108 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
 109                        struct radeon_info *info,
 110                        struct amdgpu_gpu_info *amdinfo);
 111
 112 void ac_compute_driver_uuid(char *uuid, size_t size);
 113
 114 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
 115
 116 #ifdef __cplusplus
 117 }
 118 #endif
 119
 120 #endif /* AC_GPU_INFO_H */