2 * Copyright © 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
32 #include "amd_family.h"
38 /* Prior to C11 the following may trigger a typedef redeclaration warning */
39 typedef struct amdgpu_device
*amdgpu_device_handle
;
40 struct amdgpu_gpu_info
;
43 /* PCI info: domain:bus:dev:func */
51 enum radeon_family family
;
52 enum chip_class chip_class
;
53 uint32_t num_compute_rings
;
54 uint32_t num_sdma_rings
;
55 uint32_t clock_crystal_freq
;
56 uint32_t tcc_cache_line_size
;
59 uint32_t pte_fragment_size
;
60 uint32_t gart_page_size
;
63 uint64_t vram_vis_size
;
65 unsigned gds_gfx_partition_size
;
66 uint64_t max_alloc_size
;
67 uint32_t min_alloc_size
;
68 uint32_t address32_hi
;
69 bool has_dedicated_vram
;
70 bool r600_has_virtual_memory
;
73 bool gfx_ib_pad_with_type2
;
74 unsigned ib_start_alignment
;
75 uint32_t me_fw_version
;
76 uint32_t me_fw_feature
;
77 uint32_t pfp_fw_version
;
78 uint32_t pfp_fw_feature
;
79 uint32_t ce_fw_version
;
80 uint32_t ce_fw_feature
;
82 /* Multimedia info. */
84 bool uvd_enc_supported
;
85 uint32_t uvd_fw_version
;
86 uint32_t vce_fw_version
;
87 uint32_t vce_harvest_config
;
90 uint32_t drm_major
; /* version */
92 uint32_t drm_patchlevel
;
95 bool has_syncobj_wait_for_submit
;
96 bool has_fence_to_handle
;
97 bool has_ctx_priority
;
98 bool has_local_buffers
;
101 uint32_t r600_max_quad_pipes
; /* wave size / 16 */
102 uint32_t max_shader_clock
;
103 uint32_t num_good_compute_units
;
104 uint32_t max_se
; /* shader engines */
105 uint32_t max_sh_per_se
; /* shader arrays per shader engine */
107 /* Render backends (color + depth blocks). */
108 uint32_t r300_num_gb_pipes
;
109 uint32_t r300_num_z_pipes
;
110 uint32_t r600_gb_backend_map
; /* R600 harvest config */
111 bool r600_gb_backend_map_valid
;
112 uint32_t r600_num_banks
;
113 uint32_t num_render_backends
;
114 uint32_t num_tile_pipes
; /* pipe count from PIPE_CONFIG */
115 uint32_t pipe_interleave_bytes
;
116 uint32_t enabled_rb_mask
; /* GCN harvest config */
117 uint64_t max_alignment
; /* from addrlib */
120 uint32_t si_tile_mode_array
[32];
121 uint32_t cik_macrotile_mode_array
[16];
124 bool ac_query_gpu_info(int fd
, amdgpu_device_handle dev
,
125 struct radeon_info
*info
,
126 struct amdgpu_gpu_info
*amdinfo
);
128 void ac_compute_driver_uuid(char *uuid
, size_t size
);
130 void ac_compute_device_uuid(struct radeon_info
*info
, char *uuid
, size_t size
);
131 void ac_print_gpu_info(struct radeon_info
*info
);
137 #endif /* AC_GPU_INFO_H */