01852dbff4664f36e238b7efc56cd502ee4af39a
[mesa.git] / src / amd / common / ac_llvm_util.c
1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
22 * of the Software.
23 *
24 */
25 /* based on pieces from si_pipe.c and radeon_llvm_emit.c */
26 #include "ac_llvm_util.h"
27 #include "ac_llvm_build.h"
28 #include "util/bitscan.h"
29 #include <llvm-c/Core.h>
30 #include <llvm-c/Support.h>
31 #include <llvm-c/Transforms/IPO.h>
32 #include <llvm-c/Transforms/Scalar.h>
33 #if HAVE_LLVM >= 0x0700
34 #include <llvm-c/Transforms/Utils.h>
35 #endif
36 #include "c11/threads.h"
37 #include "util/u_math.h"
38
39 #include <assert.h>
40 #include <stdio.h>
41 #include <string.h>
42
43 static void ac_init_llvm_target()
44 {
45 LLVMInitializeAMDGPUTargetInfo();
46 LLVMInitializeAMDGPUTarget();
47 LLVMInitializeAMDGPUTargetMC();
48 LLVMInitializeAMDGPUAsmPrinter();
49
50 /* For inline assembly. */
51 LLVMInitializeAMDGPUAsmParser();
52
53 /* Workaround for bug in llvm 4.0 that causes image intrinsics
54 * to disappear.
55 * https://reviews.llvm.org/D26348
56 *
57 * "mesa" is the prefix for error messages.
58 */
59 const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
60 LLVMParseCommandLineOptions(2, argv, NULL);
61 }
62
63 static once_flag ac_init_llvm_target_once_flag = ONCE_FLAG_INIT;
64
65 void ac_init_llvm_once(void)
66 {
67 call_once(&ac_init_llvm_target_once_flag, ac_init_llvm_target);
68 }
69
70 LLVMTargetRef ac_get_llvm_target(const char *triple)
71 {
72 LLVMTargetRef target = NULL;
73 char *err_message = NULL;
74
75 if (LLVMGetTargetFromTriple(triple, &target, &err_message)) {
76 fprintf(stderr, "Cannot find target for triple %s ", triple);
77 if (err_message) {
78 fprintf(stderr, "%s\n", err_message);
79 }
80 LLVMDisposeMessage(err_message);
81 return NULL;
82 }
83 return target;
84 }
85
86 const char *ac_get_llvm_processor_name(enum radeon_family family)
87 {
88 switch (family) {
89 case CHIP_TAHITI:
90 return "tahiti";
91 case CHIP_PITCAIRN:
92 return "pitcairn";
93 case CHIP_VERDE:
94 return "verde";
95 case CHIP_OLAND:
96 return "oland";
97 case CHIP_HAINAN:
98 return "hainan";
99 case CHIP_BONAIRE:
100 return "bonaire";
101 case CHIP_KABINI:
102 return "kabini";
103 case CHIP_KAVERI:
104 return "kaveri";
105 case CHIP_HAWAII:
106 return "hawaii";
107 case CHIP_MULLINS:
108 return "mullins";
109 case CHIP_TONGA:
110 return "tonga";
111 case CHIP_ICELAND:
112 return "iceland";
113 case CHIP_CARRIZO:
114 return "carrizo";
115 case CHIP_FIJI:
116 return "fiji";
117 case CHIP_STONEY:
118 return "stoney";
119 case CHIP_POLARIS10:
120 return "polaris10";
121 case CHIP_POLARIS11:
122 case CHIP_POLARIS12:
123 case CHIP_VEGAM:
124 return "polaris11";
125 case CHIP_VEGA10:
126 return "gfx900";
127 case CHIP_RAVEN:
128 return "gfx902";
129 case CHIP_VEGA12:
130 return HAVE_LLVM >= 0x0700 ? "gfx904" : "gfx902";
131 default:
132 return "";
133 }
134 }
135
136 LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family,
137 enum ac_target_machine_options tm_options,
138 const char **out_triple)
139 {
140 assert(family >= CHIP_TAHITI);
141 char features[256];
142 const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d" : "amdgcn--";
143 LLVMTargetRef target = ac_get_llvm_target(triple);
144 bool barrier_does_waitcnt = true; /* TODO: not for Vega20 */
145
146 snprintf(features, sizeof(features),
147 "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
148 tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
149 tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
150 tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
151 tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ? ",-promote-alloca" : "",
152 barrier_does_waitcnt ? ",+auto-waitcnt-before-barrier" : "");
153
154 LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
155 target,
156 triple,
157 ac_get_llvm_processor_name(family),
158 features,
159 LLVMCodeGenLevelDefault,
160 LLVMRelocDefault,
161 LLVMCodeModelDefault);
162
163 if (out_triple)
164 *out_triple = triple;
165 return tm;
166 }
167
168 LLVMPassManagerRef ac_create_passmgr(LLVMTargetLibraryInfoRef target_library_info,
169 bool check_ir)
170 {
171 LLVMPassManagerRef passmgr = LLVMCreatePassManager();
172 if (!passmgr)
173 return NULL;
174
175 if (target_library_info)
176 LLVMAddTargetLibraryInfo(target_library_info,
177 passmgr);
178
179 if (check_ir)
180 LLVMAddVerifierPass(passmgr);
181 LLVMAddAlwaysInlinerPass(passmgr);
182 /* This pass should eliminate all the load and store instructions. */
183 LLVMAddPromoteMemoryToRegisterPass(passmgr);
184 LLVMAddScalarReplAggregatesPass(passmgr);
185 LLVMAddLICMPass(passmgr);
186 LLVMAddAggressiveDCEPass(passmgr);
187 LLVMAddCFGSimplificationPass(passmgr);
188 /* This is recommended by the instruction combining pass. */
189 LLVMAddEarlyCSEMemSSAPass(passmgr);
190 LLVMAddInstructionCombiningPass(passmgr);
191 return passmgr;
192 }
193
194 static const char *attr_to_str(enum ac_func_attr attr)
195 {
196 switch (attr) {
197 case AC_FUNC_ATTR_ALWAYSINLINE: return "alwaysinline";
198 case AC_FUNC_ATTR_INREG: return "inreg";
199 case AC_FUNC_ATTR_NOALIAS: return "noalias";
200 case AC_FUNC_ATTR_NOUNWIND: return "nounwind";
201 case AC_FUNC_ATTR_READNONE: return "readnone";
202 case AC_FUNC_ATTR_READONLY: return "readonly";
203 case AC_FUNC_ATTR_WRITEONLY: return "writeonly";
204 case AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY: return "inaccessiblememonly";
205 case AC_FUNC_ATTR_CONVERGENT: return "convergent";
206 default:
207 fprintf(stderr, "Unhandled function attribute: %x\n", attr);
208 return 0;
209 }
210 }
211
212 void
213 ac_add_function_attr(LLVMContextRef ctx, LLVMValueRef function,
214 int attr_idx, enum ac_func_attr attr)
215 {
216 const char *attr_name = attr_to_str(attr);
217 unsigned kind_id = LLVMGetEnumAttributeKindForName(attr_name,
218 strlen(attr_name));
219 LLVMAttributeRef llvm_attr = LLVMCreateEnumAttribute(ctx, kind_id, 0);
220
221 if (LLVMIsAFunction(function))
222 LLVMAddAttributeAtIndex(function, attr_idx, llvm_attr);
223 else
224 LLVMAddCallSiteAttribute(function, attr_idx, llvm_attr);
225 }
226
227 void ac_add_func_attributes(LLVMContextRef ctx, LLVMValueRef function,
228 unsigned attrib_mask)
229 {
230 attrib_mask |= AC_FUNC_ATTR_NOUNWIND;
231 attrib_mask &= ~AC_FUNC_ATTR_LEGACY;
232
233 while (attrib_mask) {
234 enum ac_func_attr attr = 1u << u_bit_scan(&attrib_mask);
235 ac_add_function_attr(ctx, function, -1, attr);
236 }
237 }
238
239 void
240 ac_dump_module(LLVMModuleRef module)
241 {
242 char *str = LLVMPrintModuleToString(module);
243 fprintf(stderr, "%s", str);
244 LLVMDisposeMessage(str);
245 }
246
247 void
248 ac_llvm_add_target_dep_function_attr(LLVMValueRef F,
249 const char *name, unsigned value)
250 {
251 char str[16];
252
253 snprintf(str, sizeof(str), "0x%x", value);
254 LLVMAddTargetDependentFunctionAttr(F, name, str);
255 }
256
257 unsigned
258 ac_count_scratch_private_memory(LLVMValueRef function)
259 {
260 unsigned private_mem_vgprs = 0;
261
262 /* Process all LLVM instructions. */
263 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(function);
264 while (bb) {
265 LLVMValueRef next = LLVMGetFirstInstruction(bb);
266
267 while (next) {
268 LLVMValueRef inst = next;
269 next = LLVMGetNextInstruction(next);
270
271 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
272 continue;
273
274 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
275 /* No idea why LLVM aligns allocas to 4 elements. */
276 unsigned alignment = LLVMGetAlignment(inst);
277 unsigned dw_size = align(ac_get_type_size(type) / 4, alignment);
278 private_mem_vgprs += dw_size;
279 }
280 bb = LLVMGetNextBasicBlock(bb);
281 }
282
283 return private_mem_vgprs;
284 }