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radv/ac: add geom input support to get deref offset.
[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_util.h"
26 #include "ac_binary.h"
27 #include "sid.h"
28 #include "nir/nir.h"
29 #include "../vulkan/radv_descriptor_set.h"
30 #include "util/bitscan.h"
31 #include <llvm-c/Transforms/Scalar.h>
32
33 enum radeon_llvm_calling_convention {
34 RADEON_LLVM_AMDGPU_VS = 87,
35 RADEON_LLVM_AMDGPU_GS = 88,
36 RADEON_LLVM_AMDGPU_PS = 89,
37 RADEON_LLVM_AMDGPU_CS = 90,
38 };
39
40 #define CONST_ADDR_SPACE 2
41 #define LOCAL_ADDR_SPACE 3
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44 #define RADEON_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
45
46 #define SENDMSG_GS 2
47 #define SENDMSG_GS_DONE 3
48
49 #define SENDMSG_GS_OP_NOP (0 << 4)
50 #define SENDMSG_GS_OP_CUT (1 << 4)
51 #define SENDMSG_GS_OP_EMIT (2 << 4)
52 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
53
54 enum desc_type {
55 DESC_IMAGE,
56 DESC_FMASK,
57 DESC_SAMPLER,
58 DESC_BUFFER,
59 };
60
61 struct nir_to_llvm_context {
62 struct ac_llvm_context ac;
63 const struct ac_nir_compiler_options *options;
64 struct ac_shader_variant_info *shader_info;
65
66 LLVMContextRef context;
67 LLVMModuleRef module;
68 LLVMBuilderRef builder;
69 LLVMValueRef main_function;
70
71 struct hash_table *defs;
72 struct hash_table *phis;
73
74 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
75 LLVMValueRef ring_offsets;
76 LLVMValueRef push_constants;
77 LLVMValueRef num_work_groups;
78 LLVMValueRef workgroup_ids;
79 LLVMValueRef local_invocation_ids;
80 LLVMValueRef tg_size;
81
82 LLVMValueRef vertex_buffers;
83 LLVMValueRef base_vertex;
84 LLVMValueRef start_instance;
85 LLVMValueRef vertex_id;
86 LLVMValueRef rel_auto_id;
87 LLVMValueRef vs_prim_id;
88 LLVMValueRef instance_id;
89
90 LLVMValueRef es2gs_offset;
91
92 LLVMValueRef gsvs_ring_stride;
93 LLVMValueRef gsvs_num_entries;
94 LLVMValueRef gs2vs_offset;
95 LLVMValueRef gs_wave_id;
96 LLVMValueRef gs_vtx_offset[6];
97 LLVMValueRef gs_prim_id, gs_invocation_id;
98
99 LLVMValueRef esgs_ring;
100 LLVMValueRef gsvs_ring;
101
102 LLVMValueRef prim_mask;
103 LLVMValueRef sample_positions;
104 LLVMValueRef persp_sample, persp_center, persp_centroid;
105 LLVMValueRef linear_sample, linear_center, linear_centroid;
106 LLVMValueRef front_face;
107 LLVMValueRef ancillary;
108 LLVMValueRef frag_pos[4];
109
110 LLVMBasicBlockRef continue_block;
111 LLVMBasicBlockRef break_block;
112
113 LLVMTypeRef i1;
114 LLVMTypeRef i8;
115 LLVMTypeRef i16;
116 LLVMTypeRef i32;
117 LLVMTypeRef i64;
118 LLVMTypeRef v2i32;
119 LLVMTypeRef v3i32;
120 LLVMTypeRef v4i32;
121 LLVMTypeRef v8i32;
122 LLVMTypeRef f32;
123 LLVMTypeRef f16;
124 LLVMTypeRef v2f32;
125 LLVMTypeRef v4f32;
126 LLVMTypeRef v16i8;
127 LLVMTypeRef voidt;
128
129 LLVMValueRef i32zero;
130 LLVMValueRef i32one;
131 LLVMValueRef f32zero;
132 LLVMValueRef f32one;
133 LLVMValueRef v4f32empty;
134
135 unsigned range_md_kind;
136 unsigned uniform_md_kind;
137 unsigned invariant_load_md_kind;
138 LLVMValueRef empty_md;
139 gl_shader_stage stage;
140
141 LLVMValueRef lds;
142 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
143 LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS * 4];
144
145 LLVMValueRef shared_memory;
146 uint64_t input_mask;
147 uint64_t output_mask;
148 int num_locals;
149 LLVMValueRef *locals;
150 bool has_ddxy;
151 unsigned num_clips;
152 unsigned num_culls;
153
154 bool has_ds_bpermute;
155
156 bool is_gs_copy_shader;
157 LLVMValueRef gs_next_vertex;
158 unsigned gs_max_out_vertices;
159 };
160
161 struct ac_tex_info {
162 LLVMValueRef args[12];
163 int arg_count;
164 LLVMTypeRef dst_type;
165 bool has_offset;
166 };
167
168 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
169 nir_deref_var *deref,
170 enum desc_type desc_type);
171 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
172 {
173 return (index * 4) + chan;
174 }
175
176 static unsigned llvm_get_type_size(LLVMTypeRef type)
177 {
178 LLVMTypeKind kind = LLVMGetTypeKind(type);
179
180 switch (kind) {
181 case LLVMIntegerTypeKind:
182 return LLVMGetIntTypeWidth(type) / 8;
183 case LLVMFloatTypeKind:
184 return 4;
185 case LLVMPointerTypeKind:
186 return 8;
187 case LLVMVectorTypeKind:
188 return LLVMGetVectorSize(type) *
189 llvm_get_type_size(LLVMGetElementType(type));
190 default:
191 assert(0);
192 return 0;
193 }
194 }
195
196 static void set_llvm_calling_convention(LLVMValueRef func,
197 gl_shader_stage stage)
198 {
199 enum radeon_llvm_calling_convention calling_conv;
200
201 switch (stage) {
202 case MESA_SHADER_VERTEX:
203 case MESA_SHADER_TESS_CTRL:
204 case MESA_SHADER_TESS_EVAL:
205 calling_conv = RADEON_LLVM_AMDGPU_VS;
206 break;
207 case MESA_SHADER_GEOMETRY:
208 calling_conv = RADEON_LLVM_AMDGPU_GS;
209 break;
210 case MESA_SHADER_FRAGMENT:
211 calling_conv = RADEON_LLVM_AMDGPU_PS;
212 break;
213 case MESA_SHADER_COMPUTE:
214 calling_conv = RADEON_LLVM_AMDGPU_CS;
215 break;
216 default:
217 unreachable("Unhandle shader type");
218 }
219
220 LLVMSetFunctionCallConv(func, calling_conv);
221 }
222
223 static LLVMValueRef
224 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
225 LLVMBuilderRef builder, LLVMTypeRef *return_types,
226 unsigned num_return_elems, LLVMTypeRef *param_types,
227 unsigned param_count, unsigned array_params_mask,
228 unsigned sgpr_params, bool unsafe_math)
229 {
230 LLVMTypeRef main_function_type, ret_type;
231 LLVMBasicBlockRef main_function_body;
232
233 if (num_return_elems)
234 ret_type = LLVMStructTypeInContext(ctx, return_types,
235 num_return_elems, true);
236 else
237 ret_type = LLVMVoidTypeInContext(ctx);
238
239 /* Setup the function */
240 main_function_type =
241 LLVMFunctionType(ret_type, param_types, param_count, 0);
242 LLVMValueRef main_function =
243 LLVMAddFunction(module, "main", main_function_type);
244 main_function_body =
245 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
246 LLVMPositionBuilderAtEnd(builder, main_function_body);
247
248 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
249 for (unsigned i = 0; i < sgpr_params; ++i) {
250 if (array_params_mask & (1 << i)) {
251 LLVMValueRef P = LLVMGetParam(main_function, i);
252 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_BYVAL);
253 ac_add_attr_dereferenceable(P, UINT64_MAX);
254 }
255 else {
256 ac_add_function_attr(main_function, i + 1, AC_FUNC_ATTR_INREG);
257 }
258 }
259
260 if (unsafe_math) {
261 /* These were copied from some LLVM test. */
262 LLVMAddTargetDependentFunctionAttr(main_function,
263 "less-precise-fpmad",
264 "true");
265 LLVMAddTargetDependentFunctionAttr(main_function,
266 "no-infs-fp-math",
267 "true");
268 LLVMAddTargetDependentFunctionAttr(main_function,
269 "no-nans-fp-math",
270 "true");
271 LLVMAddTargetDependentFunctionAttr(main_function,
272 "unsafe-fp-math",
273 "true");
274 }
275 return main_function;
276 }
277
278 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
279 {
280 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
281 CONST_ADDR_SPACE);
282 }
283
284 static LLVMValueRef get_shared_memory_ptr(struct nir_to_llvm_context *ctx,
285 int idx,
286 LLVMTypeRef type)
287 {
288 LLVMValueRef offset;
289 LLVMValueRef ptr;
290 int addr_space;
291
292 offset = LLVMConstInt(ctx->i32, idx, false);
293
294 ptr = ctx->shared_memory;
295 ptr = LLVMBuildGEP(ctx->builder, ptr, &offset, 1, "");
296 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
297 ptr = LLVMBuildBitCast(ctx->builder, ptr, LLVMPointerType(type, addr_space), "");
298 return ptr;
299 }
300
301 static LLVMValueRef to_integer(struct nir_to_llvm_context *ctx, LLVMValueRef v)
302 {
303 LLVMTypeRef type = LLVMTypeOf(v);
304 if (type == ctx->f32) {
305 return LLVMBuildBitCast(ctx->builder, v, ctx->i32, "");
306 } else if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
307 LLVMTypeRef elem_type = LLVMGetElementType(type);
308 if (elem_type == ctx->f32) {
309 LLVMTypeRef nt = LLVMVectorType(ctx->i32, LLVMGetVectorSize(type));
310 return LLVMBuildBitCast(ctx->builder, v, nt, "");
311 }
312 }
313 return v;
314 }
315
316 static LLVMValueRef to_float(struct nir_to_llvm_context *ctx, LLVMValueRef v)
317 {
318 LLVMTypeRef type = LLVMTypeOf(v);
319 if (type == ctx->i32) {
320 return LLVMBuildBitCast(ctx->builder, v, ctx->f32, "");
321 } else if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
322 LLVMTypeRef elem_type = LLVMGetElementType(type);
323 if (elem_type == ctx->i32) {
324 LLVMTypeRef nt = LLVMVectorType(ctx->f32, LLVMGetVectorSize(type));
325 return LLVMBuildBitCast(ctx->builder, v, nt, "");
326 }
327 }
328 return v;
329 }
330
331 static LLVMValueRef unpack_param(struct nir_to_llvm_context *ctx,
332 LLVMValueRef param, unsigned rshift,
333 unsigned bitwidth)
334 {
335 LLVMValueRef value = param;
336 if (rshift)
337 value = LLVMBuildLShr(ctx->builder, value,
338 LLVMConstInt(ctx->i32, rshift, false), "");
339
340 if (rshift + bitwidth < 32) {
341 unsigned mask = (1 << bitwidth) - 1;
342 value = LLVMBuildAnd(ctx->builder, value,
343 LLVMConstInt(ctx->i32, mask, false), "");
344 }
345 return value;
346 }
347
348 static LLVMValueRef build_gep0(struct nir_to_llvm_context *ctx,
349 LLVMValueRef base_ptr, LLVMValueRef index)
350 {
351 LLVMValueRef indices[2] = {
352 ctx->i32zero,
353 index,
354 };
355 return LLVMBuildGEP(ctx->builder, base_ptr,
356 indices, 2, "");
357 }
358
359 static LLVMValueRef build_indexed_load(struct nir_to_llvm_context *ctx,
360 LLVMValueRef base_ptr, LLVMValueRef index,
361 bool uniform)
362 {
363 LLVMValueRef pointer;
364 pointer = build_gep0(ctx, base_ptr, index);
365 if (uniform)
366 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
367 return LLVMBuildLoad(ctx->builder, pointer, "");
368 }
369
370 static LLVMValueRef build_indexed_load_const(struct nir_to_llvm_context *ctx,
371 LLVMValueRef base_ptr, LLVMValueRef index)
372 {
373 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
374 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
375 return result;
376 }
377
378 static void build_tbuffer_store(struct nir_to_llvm_context *ctx,
379 LLVMValueRef rsrc,
380 LLVMValueRef vdata,
381 unsigned num_channels,
382 LLVMValueRef vaddr,
383 LLVMValueRef soffset,
384 unsigned inst_offset,
385 unsigned dfmt,
386 unsigned nfmt,
387 unsigned offen,
388 unsigned idxen,
389 unsigned glc,
390 unsigned slc,
391 unsigned tfe)
392 {
393 LLVMValueRef args[] = {
394 rsrc,
395 vdata,
396 LLVMConstInt(ctx->i32, num_channels, 0),
397 vaddr,
398 soffset,
399 LLVMConstInt(ctx->i32, inst_offset, 0),
400 LLVMConstInt(ctx->i32, dfmt, 0),
401 LLVMConstInt(ctx->i32, nfmt, 0),
402 LLVMConstInt(ctx->i32, offen, 0),
403 LLVMConstInt(ctx->i32, idxen, 0),
404 LLVMConstInt(ctx->i32, glc, 0),
405 LLVMConstInt(ctx->i32, slc, 0),
406 LLVMConstInt(ctx->i32, tfe, 0)
407 };
408
409 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
410 unsigned func = CLAMP(num_channels, 1, 3) - 1;
411 const char *types[] = {"i32", "v2i32", "v4i32"};
412 char name[256];
413 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
414
415 ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->voidt,
416 args, ARRAY_SIZE(args), 0);
417
418 }
419
420 static void set_userdata_location(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs)
421 {
422 ud_info->sgpr_idx = sgpr_idx;
423 ud_info->num_sgprs = num_sgprs;
424 ud_info->indirect = false;
425 ud_info->indirect_offset = 0;
426 }
427
428 static void set_userdata_location_shader(struct nir_to_llvm_context *ctx,
429 int idx, uint8_t sgpr_idx, uint8_t num_sgprs)
430 {
431 set_userdata_location(&ctx->shader_info->user_sgprs_locs.shader_data[idx], sgpr_idx, num_sgprs);
432 }
433
434 #if 0
435 static void set_userdata_location_indirect(struct ac_userdata_info *ud_info, uint8_t sgpr_idx, uint8_t num_sgprs,
436 uint32_t indirect_offset)
437 {
438 ud_info->sgpr_idx = sgpr_idx;
439 ud_info->num_sgprs = num_sgprs;
440 ud_info->indirect = true;
441 ud_info->indirect_offset = indirect_offset;
442 }
443 #endif
444
445 static void create_function(struct nir_to_llvm_context *ctx)
446 {
447 LLVMTypeRef arg_types[23];
448 unsigned arg_idx = 0;
449 unsigned array_params_mask = 0;
450 unsigned sgpr_count = 0, user_sgpr_count;
451 unsigned i;
452 unsigned num_sets = ctx->options->layout ? ctx->options->layout->num_sets : 0;
453 unsigned user_sgpr_idx;
454 bool need_push_constants;
455 bool need_ring_offsets = false;
456
457 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
458 if (ctx->stage == MESA_SHADER_GEOMETRY ||
459 ctx->stage == MESA_SHADER_VERTEX ||
460 ctx->is_gs_copy_shader)
461 need_ring_offsets = true;
462
463 need_push_constants = true;
464 if (!ctx->options->layout)
465 need_push_constants = false;
466 else if (!ctx->options->layout->push_constant_size &&
467 !ctx->options->layout->dynamic_offset_count)
468 need_push_constants = false;
469
470 if (need_ring_offsets && !ctx->options->supports_spill) {
471 arg_types[arg_idx++] = const_array(ctx->v16i8, 8); /* address of rings */
472 }
473
474 /* 1 for each descriptor set */
475 for (unsigned i = 0; i < num_sets; ++i) {
476 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
477 array_params_mask |= (1 << arg_idx);
478 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
479 }
480 }
481
482 if (need_push_constants) {
483 /* 1 for push constants and dynamic descriptors */
484 array_params_mask |= (1 << arg_idx);
485 arg_types[arg_idx++] = const_array(ctx->i8, 1024 * 1024);
486 }
487
488 switch (ctx->stage) {
489 case MESA_SHADER_COMPUTE:
490 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3); /* grid size */
491 user_sgpr_count = arg_idx;
492 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
493 arg_types[arg_idx++] = ctx->i32;
494 sgpr_count = arg_idx;
495
496 arg_types[arg_idx++] = LLVMVectorType(ctx->i32, 3);
497 break;
498 case MESA_SHADER_VERTEX:
499 if (!ctx->is_gs_copy_shader) {
500 arg_types[arg_idx++] = const_array(ctx->v16i8, 16); /* vertex buffers */
501 arg_types[arg_idx++] = ctx->i32; // base vertex
502 arg_types[arg_idx++] = ctx->i32; // start instance
503 }
504 user_sgpr_count = arg_idx;
505 if (ctx->options->key.vs.as_es)
506 arg_types[arg_idx++] = ctx->i32; //es2gs offset
507 sgpr_count = arg_idx;
508 arg_types[arg_idx++] = ctx->i32; // vertex id
509 if (!ctx->is_gs_copy_shader) {
510 arg_types[arg_idx++] = ctx->i32; // rel auto id
511 arg_types[arg_idx++] = ctx->i32; // vs prim id
512 arg_types[arg_idx++] = ctx->i32; // instance id
513 }
514 break;
515 case MESA_SHADER_GEOMETRY:
516 arg_types[arg_idx++] = ctx->i32; // gsvs stride
517 arg_types[arg_idx++] = ctx->i32; // gsvs num entires
518 user_sgpr_count = arg_idx;
519 arg_types[arg_idx++] = ctx->i32; // gs2vs offset
520 arg_types[arg_idx++] = ctx->i32; // wave id
521 sgpr_count = arg_idx;
522 arg_types[arg_idx++] = ctx->i32; // vtx0
523 arg_types[arg_idx++] = ctx->i32; // vtx1
524 arg_types[arg_idx++] = ctx->i32; // prim id
525 arg_types[arg_idx++] = ctx->i32; // vtx2
526 arg_types[arg_idx++] = ctx->i32; // vtx3
527 arg_types[arg_idx++] = ctx->i32; // vtx4
528 arg_types[arg_idx++] = ctx->i32; // vtx5
529 arg_types[arg_idx++] = ctx->i32; // GS instance id
530 break;
531 case MESA_SHADER_FRAGMENT:
532 arg_types[arg_idx++] = const_array(ctx->f32, 32); /* sample positions */
533 user_sgpr_count = arg_idx;
534 arg_types[arg_idx++] = ctx->i32; /* prim mask */
535 sgpr_count = arg_idx;
536 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */
537 arg_types[arg_idx++] = ctx->v2i32; /* persp center */
538 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */
539 arg_types[arg_idx++] = ctx->v3i32; /* persp pull model */
540 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */
541 arg_types[arg_idx++] = ctx->v2i32; /* linear center */
542 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */
543 arg_types[arg_idx++] = ctx->f32; /* line stipple tex */
544 arg_types[arg_idx++] = ctx->f32; /* pos x float */
545 arg_types[arg_idx++] = ctx->f32; /* pos y float */
546 arg_types[arg_idx++] = ctx->f32; /* pos z float */
547 arg_types[arg_idx++] = ctx->f32; /* pos w float */
548 arg_types[arg_idx++] = ctx->i32; /* front face */
549 arg_types[arg_idx++] = ctx->i32; /* ancillary */
550 arg_types[arg_idx++] = ctx->f32; /* sample coverage */
551 arg_types[arg_idx++] = ctx->i32; /* fixed pt */
552 break;
553 default:
554 unreachable("Shader stage not implemented");
555 }
556
557 ctx->main_function = create_llvm_function(
558 ctx->context, ctx->module, ctx->builder, NULL, 0, arg_types,
559 arg_idx, array_params_mask, sgpr_count, ctx->options->unsafe_math);
560 set_llvm_calling_convention(ctx->main_function, ctx->stage);
561
562 ctx->shader_info->num_input_sgprs = 0;
563 ctx->shader_info->num_input_vgprs = 0;
564
565 ctx->shader_info->num_user_sgprs = ctx->options->supports_spill ? 2 : 0;
566 for (i = 0; i < user_sgpr_count; i++)
567 ctx->shader_info->num_user_sgprs += llvm_get_type_size(arg_types[i]) / 4;
568
569 ctx->shader_info->num_input_sgprs = ctx->shader_info->num_user_sgprs;
570 for (; i < sgpr_count; i++)
571 ctx->shader_info->num_input_sgprs += llvm_get_type_size(arg_types[i]) / 4;
572
573 if (ctx->stage != MESA_SHADER_FRAGMENT)
574 for (; i < arg_idx; ++i)
575 ctx->shader_info->num_input_vgprs += llvm_get_type_size(arg_types[i]) / 4;
576
577 arg_idx = 0;
578 user_sgpr_idx = 0;
579
580 if (ctx->options->supports_spill || need_ring_offsets) {
581 set_userdata_location_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS, user_sgpr_idx, 2);
582 user_sgpr_idx += 2;
583 if (ctx->options->supports_spill) {
584 ctx->ring_offsets = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
585 LLVMPointerType(ctx->i8, CONST_ADDR_SPACE),
586 NULL, 0, AC_FUNC_ATTR_READNONE);
587 ctx->ring_offsets = LLVMBuildBitCast(ctx->builder, ctx->ring_offsets,
588 const_array(ctx->v16i8, 8), "");
589 } else
590 ctx->ring_offsets = LLVMGetParam(ctx->main_function, arg_idx++);
591 }
592
593 for (unsigned i = 0; i < num_sets; ++i) {
594 if (ctx->options->layout->set[i].layout->shader_stages & (1 << ctx->stage)) {
595 set_userdata_location(&ctx->shader_info->user_sgprs_locs.descriptor_sets[i], user_sgpr_idx, 2);
596 user_sgpr_idx += 2;
597 ctx->descriptor_sets[i] =
598 LLVMGetParam(ctx->main_function, arg_idx++);
599 } else
600 ctx->descriptor_sets[i] = NULL;
601 }
602
603 if (need_push_constants) {
604 ctx->push_constants = LLVMGetParam(ctx->main_function, arg_idx++);
605 set_userdata_location_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
606 user_sgpr_idx += 2;
607 }
608
609 switch (ctx->stage) {
610 case MESA_SHADER_COMPUTE:
611 set_userdata_location_shader(ctx, AC_UD_CS_GRID_SIZE, user_sgpr_idx, 3);
612 user_sgpr_idx += 3;
613 ctx->num_work_groups =
614 LLVMGetParam(ctx->main_function, arg_idx++);
615 ctx->workgroup_ids =
616 LLVMGetParam(ctx->main_function, arg_idx++);
617 ctx->tg_size =
618 LLVMGetParam(ctx->main_function, arg_idx++);
619 ctx->local_invocation_ids =
620 LLVMGetParam(ctx->main_function, arg_idx++);
621 break;
622 case MESA_SHADER_VERTEX:
623 if (!ctx->is_gs_copy_shader) {
624 set_userdata_location_shader(ctx, AC_UD_VS_VERTEX_BUFFERS, user_sgpr_idx, 2);
625 user_sgpr_idx += 2;
626 ctx->vertex_buffers = LLVMGetParam(ctx->main_function, arg_idx++);
627 set_userdata_location_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE, user_sgpr_idx, 2);
628 user_sgpr_idx += 2;
629 ctx->base_vertex = LLVMGetParam(ctx->main_function, arg_idx++);
630 ctx->start_instance = LLVMGetParam(ctx->main_function, arg_idx++);
631 }
632 if (ctx->options->key.vs.as_es)
633 ctx->es2gs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
634 ctx->vertex_id = LLVMGetParam(ctx->main_function, arg_idx++);
635 if (!ctx->is_gs_copy_shader) {
636 ctx->rel_auto_id = LLVMGetParam(ctx->main_function, arg_idx++);
637 ctx->vs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
638 ctx->instance_id = LLVMGetParam(ctx->main_function, arg_idx++);
639 }
640 break;
641 case MESA_SHADER_GEOMETRY:
642 set_userdata_location_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES, user_sgpr_idx, 2);
643 user_sgpr_idx += 2;
644 ctx->gsvs_ring_stride = LLVMGetParam(ctx->main_function, arg_idx++);
645 ctx->gsvs_num_entries = LLVMGetParam(ctx->main_function, arg_idx++);
646 ctx->gs2vs_offset = LLVMGetParam(ctx->main_function, arg_idx++);
647 ctx->gs_wave_id = LLVMGetParam(ctx->main_function, arg_idx++);
648 ctx->gs_vtx_offset[0] = LLVMGetParam(ctx->main_function, arg_idx++);
649 ctx->gs_vtx_offset[1] = LLVMGetParam(ctx->main_function, arg_idx++);
650 ctx->gs_prim_id = LLVMGetParam(ctx->main_function, arg_idx++);
651 ctx->gs_vtx_offset[2] = LLVMGetParam(ctx->main_function, arg_idx++);
652 ctx->gs_vtx_offset[3] = LLVMGetParam(ctx->main_function, arg_idx++);
653 ctx->gs_vtx_offset[4] = LLVMGetParam(ctx->main_function, arg_idx++);
654 ctx->gs_vtx_offset[5] = LLVMGetParam(ctx->main_function, arg_idx++);
655 ctx->gs_invocation_id = LLVMGetParam(ctx->main_function, arg_idx++);
656 break;
657 case MESA_SHADER_FRAGMENT:
658 set_userdata_location_shader(ctx, AC_UD_PS_SAMPLE_POS, user_sgpr_idx, 2);
659 user_sgpr_idx += 2;
660 ctx->sample_positions = LLVMGetParam(ctx->main_function, arg_idx++);
661 ctx->prim_mask = LLVMGetParam(ctx->main_function, arg_idx++);
662 ctx->persp_sample = LLVMGetParam(ctx->main_function, arg_idx++);
663 ctx->persp_center = LLVMGetParam(ctx->main_function, arg_idx++);
664 ctx->persp_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
665 arg_idx++;
666 ctx->linear_sample = LLVMGetParam(ctx->main_function, arg_idx++);
667 ctx->linear_center = LLVMGetParam(ctx->main_function, arg_idx++);
668 ctx->linear_centroid = LLVMGetParam(ctx->main_function, arg_idx++);
669 arg_idx++; /* line stipple */
670 ctx->frag_pos[0] = LLVMGetParam(ctx->main_function, arg_idx++);
671 ctx->frag_pos[1] = LLVMGetParam(ctx->main_function, arg_idx++);
672 ctx->frag_pos[2] = LLVMGetParam(ctx->main_function, arg_idx++);
673 ctx->frag_pos[3] = LLVMGetParam(ctx->main_function, arg_idx++);
674 ctx->front_face = LLVMGetParam(ctx->main_function, arg_idx++);
675 ctx->ancillary = LLVMGetParam(ctx->main_function, arg_idx++);
676 break;
677 default:
678 unreachable("Shader stage not implemented");
679 }
680 }
681
682 static void setup_types(struct nir_to_llvm_context *ctx)
683 {
684 LLVMValueRef args[4];
685
686 ctx->voidt = LLVMVoidTypeInContext(ctx->context);
687 ctx->i1 = LLVMIntTypeInContext(ctx->context, 1);
688 ctx->i8 = LLVMIntTypeInContext(ctx->context, 8);
689 ctx->i16 = LLVMIntTypeInContext(ctx->context, 16);
690 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
691 ctx->i64 = LLVMIntTypeInContext(ctx->context, 64);
692 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
693 ctx->v3i32 = LLVMVectorType(ctx->i32, 3);
694 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
695 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
696 ctx->f32 = LLVMFloatTypeInContext(ctx->context);
697 ctx->f16 = LLVMHalfTypeInContext(ctx->context);
698 ctx->v2f32 = LLVMVectorType(ctx->f32, 2);
699 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
700 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
701
702 ctx->i32zero = LLVMConstInt(ctx->i32, 0, false);
703 ctx->i32one = LLVMConstInt(ctx->i32, 1, false);
704 ctx->f32zero = LLVMConstReal(ctx->f32, 0.0);
705 ctx->f32one = LLVMConstReal(ctx->f32, 1.0);
706
707 args[0] = ctx->f32zero;
708 args[1] = ctx->f32zero;
709 args[2] = ctx->f32zero;
710 args[3] = ctx->f32one;
711 ctx->v4f32empty = LLVMConstVector(args, 4);
712
713 ctx->range_md_kind = LLVMGetMDKindIDInContext(ctx->context,
714 "range", 5);
715 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(ctx->context,
716 "invariant.load", 14);
717 ctx->uniform_md_kind =
718 LLVMGetMDKindIDInContext(ctx->context, "amdgpu.uniform", 14);
719 ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
720
721 args[0] = LLVMConstReal(ctx->f32, 2.5);
722 }
723
724 static int get_llvm_num_components(LLVMValueRef value)
725 {
726 LLVMTypeRef type = LLVMTypeOf(value);
727 unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
728 ? LLVMGetVectorSize(type)
729 : 1;
730 return num_components;
731 }
732
733 static LLVMValueRef llvm_extract_elem(struct nir_to_llvm_context *ctx,
734 LLVMValueRef value,
735 int index)
736 {
737 int count = get_llvm_num_components(value);
738
739 assert(index < count);
740 if (count == 1)
741 return value;
742
743 return LLVMBuildExtractElement(ctx->builder, value,
744 LLVMConstInt(ctx->i32, index, false), "");
745 }
746
747 static LLVMValueRef trim_vector(struct nir_to_llvm_context *ctx,
748 LLVMValueRef value, unsigned count)
749 {
750 unsigned num_components = get_llvm_num_components(value);
751 if (count == num_components)
752 return value;
753
754 LLVMValueRef masks[] = {
755 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
756 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
757
758 if (count == 1)
759 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
760 "");
761
762 LLVMValueRef swizzle = LLVMConstVector(masks, count);
763 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
764 }
765
766 static void
767 build_store_values_extended(struct nir_to_llvm_context *ctx,
768 LLVMValueRef *values,
769 unsigned value_count,
770 unsigned value_stride,
771 LLVMValueRef vec)
772 {
773 LLVMBuilderRef builder = ctx->builder;
774 unsigned i;
775
776 if (value_count == 1) {
777 LLVMBuildStore(builder, vec, values[0]);
778 return;
779 }
780
781 for (i = 0; i < value_count; i++) {
782 LLVMValueRef ptr = values[i * value_stride];
783 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
784 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
785 LLVMBuildStore(builder, value, ptr);
786 }
787 }
788
789 static LLVMTypeRef get_def_type(struct nir_to_llvm_context *ctx,
790 nir_ssa_def *def)
791 {
792 LLVMTypeRef type = LLVMIntTypeInContext(ctx->context, def->bit_size);
793 if (def->num_components > 1) {
794 type = LLVMVectorType(type, def->num_components);
795 }
796 return type;
797 }
798
799 static LLVMValueRef get_src(struct nir_to_llvm_context *ctx, nir_src src)
800 {
801 assert(src.is_ssa);
802 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, src.ssa);
803 return (LLVMValueRef)entry->data;
804 }
805
806
807 static LLVMBasicBlockRef get_block(struct nir_to_llvm_context *ctx,
808 struct nir_block *b)
809 {
810 struct hash_entry *entry = _mesa_hash_table_search(ctx->defs, b);
811 return (LLVMBasicBlockRef)entry->data;
812 }
813
814 static LLVMValueRef get_alu_src(struct nir_to_llvm_context *ctx,
815 nir_alu_src src,
816 unsigned num_components)
817 {
818 LLVMValueRef value = get_src(ctx, src.src);
819 bool need_swizzle = false;
820
821 assert(value);
822 LLVMTypeRef type = LLVMTypeOf(value);
823 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
824 ? LLVMGetVectorSize(type)
825 : 1;
826
827 for (unsigned i = 0; i < num_components; ++i) {
828 assert(src.swizzle[i] < src_components);
829 if (src.swizzle[i] != i)
830 need_swizzle = true;
831 }
832
833 if (need_swizzle || num_components != src_components) {
834 LLVMValueRef masks[] = {
835 LLVMConstInt(ctx->i32, src.swizzle[0], false),
836 LLVMConstInt(ctx->i32, src.swizzle[1], false),
837 LLVMConstInt(ctx->i32, src.swizzle[2], false),
838 LLVMConstInt(ctx->i32, src.swizzle[3], false)};
839
840 if (src_components > 1 && num_components == 1) {
841 value = LLVMBuildExtractElement(ctx->builder, value,
842 masks[0], "");
843 } else if (src_components == 1 && num_components > 1) {
844 LLVMValueRef values[] = {value, value, value, value};
845 value = ac_build_gather_values(&ctx->ac, values, num_components);
846 } else {
847 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
848 value = LLVMBuildShuffleVector(ctx->builder, value, value,
849 swizzle, "");
850 }
851 }
852 assert(!src.negate);
853 assert(!src.abs);
854 return value;
855 }
856
857 static LLVMValueRef emit_int_cmp(struct nir_to_llvm_context *ctx,
858 LLVMIntPredicate pred, LLVMValueRef src0,
859 LLVMValueRef src1)
860 {
861 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
862 return LLVMBuildSelect(ctx->builder, result,
863 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
864 LLVMConstInt(ctx->i32, 0, false), "");
865 }
866
867 static LLVMValueRef emit_float_cmp(struct nir_to_llvm_context *ctx,
868 LLVMRealPredicate pred, LLVMValueRef src0,
869 LLVMValueRef src1)
870 {
871 LLVMValueRef result;
872 src0 = to_float(ctx, src0);
873 src1 = to_float(ctx, src1);
874 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
875 return LLVMBuildSelect(ctx->builder, result,
876 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
877 LLVMConstInt(ctx->i32, 0, false), "");
878 }
879
880 static LLVMValueRef emit_intrin_1f_param(struct nir_to_llvm_context *ctx,
881 const char *intrin,
882 LLVMValueRef src0)
883 {
884 LLVMValueRef params[] = {
885 to_float(ctx, src0),
886 };
887 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 1, AC_FUNC_ATTR_READNONE);
888 }
889
890 static LLVMValueRef emit_intrin_2f_param(struct nir_to_llvm_context *ctx,
891 const char *intrin,
892 LLVMValueRef src0, LLVMValueRef src1)
893 {
894 LLVMValueRef params[] = {
895 to_float(ctx, src0),
896 to_float(ctx, src1),
897 };
898 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 2, AC_FUNC_ATTR_READNONE);
899 }
900
901 static LLVMValueRef emit_intrin_3f_param(struct nir_to_llvm_context *ctx,
902 const char *intrin,
903 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
904 {
905 LLVMValueRef params[] = {
906 to_float(ctx, src0),
907 to_float(ctx, src1),
908 to_float(ctx, src2),
909 };
910 return ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->f32, params, 3, AC_FUNC_ATTR_READNONE);
911 }
912
913 static LLVMValueRef emit_bcsel(struct nir_to_llvm_context *ctx,
914 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
915 {
916 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
917 ctx->i32zero, "");
918 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
919 }
920
921 static LLVMValueRef emit_find_lsb(struct nir_to_llvm_context *ctx,
922 LLVMValueRef src0)
923 {
924 LLVMValueRef params[2] = {
925 src0,
926
927 /* The value of 1 means that ffs(x=0) = undef, so LLVM won't
928 * add special code to check for x=0. The reason is that
929 * the LLVM behavior for x=0 is different from what we
930 * need here.
931 *
932 * The hardware already implements the correct behavior.
933 */
934 LLVMConstInt(ctx->i32, 1, false),
935 };
936 return ac_emit_llvm_intrinsic(&ctx->ac, "llvm.cttz.i32", ctx->i32, params, 2, AC_FUNC_ATTR_READNONE);
937 }
938
939 static LLVMValueRef emit_ifind_msb(struct nir_to_llvm_context *ctx,
940 LLVMValueRef src0)
941 {
942 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.flbit.i32",
943 ctx->i32, &src0, 1,
944 AC_FUNC_ATTR_READNONE);
945
946 /* The HW returns the last bit index from MSB, but NIR wants
947 * the index from LSB. Invert it by doing "31 - msb". */
948 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
949 msb, "");
950
951 LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true);
952 LLVMValueRef cond = LLVMBuildOr(ctx->builder,
953 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
954 src0, ctx->i32zero, ""),
955 LLVMBuildICmp(ctx->builder, LLVMIntEQ,
956 src0, all_ones, ""), "");
957
958 return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, "");
959 }
960
961 static LLVMValueRef emit_ufind_msb(struct nir_to_llvm_context *ctx,
962 LLVMValueRef src0)
963 {
964 LLVMValueRef args[2] = {
965 src0,
966 ctx->i32one,
967 };
968 LLVMValueRef msb = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctlz.i32",
969 ctx->i32, args, ARRAY_SIZE(args),
970 AC_FUNC_ATTR_READNONE);
971
972 /* The HW returns the last bit index from MSB, but NIR wants
973 * the index from LSB. Invert it by doing "31 - msb". */
974 msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false),
975 msb, "");
976
977 return LLVMBuildSelect(ctx->builder,
978 LLVMBuildICmp(ctx->builder, LLVMIntEQ, src0,
979 ctx->i32zero, ""),
980 LLVMConstInt(ctx->i32, -1, true), msb, "");
981 }
982
983 static LLVMValueRef emit_minmax_int(struct nir_to_llvm_context *ctx,
984 LLVMIntPredicate pred,
985 LLVMValueRef src0, LLVMValueRef src1)
986 {
987 return LLVMBuildSelect(ctx->builder,
988 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
989 src0,
990 src1, "");
991
992 }
993 static LLVMValueRef emit_iabs(struct nir_to_llvm_context *ctx,
994 LLVMValueRef src0)
995 {
996 return emit_minmax_int(ctx, LLVMIntSGT, src0,
997 LLVMBuildNeg(ctx->builder, src0, ""));
998 }
999
1000 static LLVMValueRef emit_fsign(struct nir_to_llvm_context *ctx,
1001 LLVMValueRef src0)
1002 {
1003 LLVMValueRef cmp, val;
1004
1005 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32zero, "");
1006 val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32one, src0, "");
1007 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32zero, "");
1008 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, -1.0), "");
1009 return val;
1010 }
1011
1012 static LLVMValueRef emit_isign(struct nir_to_llvm_context *ctx,
1013 LLVMValueRef src0)
1014 {
1015 LLVMValueRef cmp, val;
1016
1017 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32zero, "");
1018 val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32one, src0, "");
1019 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32zero, "");
1020 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, -1, true), "");
1021 return val;
1022 }
1023
1024 static LLVMValueRef emit_ffract(struct nir_to_llvm_context *ctx,
1025 LLVMValueRef src0)
1026 {
1027 const char *intr = "llvm.floor.f32";
1028 LLVMValueRef fsrc0 = to_float(ctx, src0);
1029 LLVMValueRef params[] = {
1030 fsrc0,
1031 };
1032 LLVMValueRef floor = ac_emit_llvm_intrinsic(&ctx->ac, intr,
1033 ctx->f32, params, 1,
1034 AC_FUNC_ATTR_READNONE);
1035 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1036 }
1037
1038 static LLVMValueRef emit_uint_carry(struct nir_to_llvm_context *ctx,
1039 const char *intrin,
1040 LLVMValueRef src0, LLVMValueRef src1)
1041 {
1042 LLVMTypeRef ret_type;
1043 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1044 LLVMValueRef res;
1045 LLVMValueRef params[] = { src0, src1 };
1046 ret_type = LLVMStructTypeInContext(ctx->context, types,
1047 2, true);
1048
1049 res = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ret_type,
1050 params, 2, AC_FUNC_ATTR_READNONE);
1051
1052 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1053 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1054 return res;
1055 }
1056
1057 static LLVMValueRef emit_b2f(struct nir_to_llvm_context *ctx,
1058 LLVMValueRef src0)
1059 {
1060 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1061 }
1062
1063 static LLVMValueRef emit_umul_high(struct nir_to_llvm_context *ctx,
1064 LLVMValueRef src0, LLVMValueRef src1)
1065 {
1066 LLVMValueRef dst64, result;
1067 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1068 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1069
1070 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1071 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1072 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1073 return result;
1074 }
1075
1076 static LLVMValueRef emit_imul_high(struct nir_to_llvm_context *ctx,
1077 LLVMValueRef src0, LLVMValueRef src1)
1078 {
1079 LLVMValueRef dst64, result;
1080 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1081 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1082
1083 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1084 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1085 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1086 return result;
1087 }
1088
1089 static LLVMValueRef emit_bitfield_extract(struct nir_to_llvm_context *ctx,
1090 const char *intrin,
1091 LLVMValueRef srcs[3])
1092 {
1093 LLVMValueRef result;
1094 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1095 result = ac_emit_llvm_intrinsic(&ctx->ac, intrin, ctx->i32, srcs, 3, AC_FUNC_ATTR_READNONE);
1096
1097 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1098 return result;
1099 }
1100
1101 static LLVMValueRef emit_bitfield_insert(struct nir_to_llvm_context *ctx,
1102 LLVMValueRef src0, LLVMValueRef src1,
1103 LLVMValueRef src2, LLVMValueRef src3)
1104 {
1105 LLVMValueRef bfi_args[3], result;
1106
1107 bfi_args[0] = LLVMBuildShl(ctx->builder,
1108 LLVMBuildSub(ctx->builder,
1109 LLVMBuildShl(ctx->builder,
1110 ctx->i32one,
1111 src3, ""),
1112 ctx->i32one, ""),
1113 src2, "");
1114 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1115 bfi_args[2] = src0;
1116
1117 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1118
1119 /* Calculate:
1120 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1121 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1122 */
1123 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1124 LLVMBuildAnd(ctx->builder, bfi_args[0],
1125 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1126
1127 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1128 return result;
1129 }
1130
1131 static LLVMValueRef emit_pack_half_2x16(struct nir_to_llvm_context *ctx,
1132 LLVMValueRef src0)
1133 {
1134 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1135 int i;
1136 LLVMValueRef comp[2];
1137
1138 src0 = to_float(ctx, src0);
1139 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, "");
1140 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, "");
1141 for (i = 0; i < 2; i++) {
1142 comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
1143 comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
1144 comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
1145 }
1146
1147 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
1148 comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
1149
1150 return comp[0];
1151 }
1152
1153 static LLVMValueRef emit_unpack_half_2x16(struct nir_to_llvm_context *ctx,
1154 LLVMValueRef src0)
1155 {
1156 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1157 LLVMValueRef temps[2], result, val;
1158 int i;
1159
1160 for (i = 0; i < 2; i++) {
1161 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1162 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1163 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1164 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1165 }
1166
1167 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1168 ctx->i32zero, "");
1169 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1170 ctx->i32one, "");
1171 return result;
1172 }
1173
1174 /**
1175 * Set range metadata on an instruction. This can only be used on load and
1176 * call instructions. If you know an instruction can only produce the values
1177 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1178 * \p lo is the minimum value inclusive.
1179 * \p hi is the maximum value exclusive.
1180 */
1181 static void set_range_metadata(struct nir_to_llvm_context *ctx,
1182 LLVMValueRef value, unsigned lo, unsigned hi)
1183 {
1184 LLVMValueRef range_md, md_args[2];
1185 LLVMTypeRef type = LLVMTypeOf(value);
1186 LLVMContextRef context = LLVMGetTypeContext(type);
1187
1188 md_args[0] = LLVMConstInt(type, lo, false);
1189 md_args[1] = LLVMConstInt(type, hi, false);
1190 range_md = LLVMMDNodeInContext(context, md_args, 2);
1191 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1192 }
1193
1194 static LLVMValueRef get_thread_id(struct nir_to_llvm_context *ctx)
1195 {
1196 LLVMValueRef tid;
1197 LLVMValueRef tid_args[2];
1198 tid_args[0] = LLVMConstInt(ctx->i32, 0xffffffff, false);
1199 tid_args[1] = ctx->i32zero;
1200 tid_args[1] = ac_emit_llvm_intrinsic(&ctx->ac,
1201 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1202 tid_args, 2, AC_FUNC_ATTR_READNONE);
1203
1204 tid = ac_emit_llvm_intrinsic(&ctx->ac,
1205 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1206 tid_args, 2, AC_FUNC_ATTR_READNONE);
1207 set_range_metadata(ctx, tid, 0, 64);
1208 return tid;
1209 }
1210
1211 /*
1212 * SI implements derivatives using the local data store (LDS)
1213 * All writes to the LDS happen in all executing threads at
1214 * the same time. TID is the Thread ID for the current
1215 * thread and is a value between 0 and 63, representing
1216 * the thread's position in the wavefront.
1217 *
1218 * For the pixel shader threads are grouped into quads of four pixels.
1219 * The TIDs of the pixels of a quad are:
1220 *
1221 * +------+------+
1222 * |4n + 0|4n + 1|
1223 * +------+------+
1224 * |4n + 2|4n + 3|
1225 * +------+------+
1226 *
1227 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
1228 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
1229 * the current pixel's column, and masking with 0xfffffffe yields the TID
1230 * of the left pixel of the current pixel's row.
1231 *
1232 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
1233 * adding 2 yields the TID of the pixel below the top pixel.
1234 */
1235 /* masks for thread ID. */
1236 #define TID_MASK_TOP_LEFT 0xfffffffc
1237 #define TID_MASK_TOP 0xfffffffd
1238 #define TID_MASK_LEFT 0xfffffffe
1239 static LLVMValueRef emit_ddxy(struct nir_to_llvm_context *ctx,
1240 nir_op op,
1241 LLVMValueRef src0)
1242 {
1243 LLVMValueRef tl, trbl, result;
1244 LLVMValueRef tl_tid, trbl_tid;
1245 LLVMValueRef args[2];
1246 LLVMValueRef thread_id;
1247 unsigned mask;
1248 int idx;
1249 ctx->has_ddxy = true;
1250
1251 if (!ctx->lds && !ctx->has_ds_bpermute)
1252 ctx->lds = LLVMAddGlobalInAddressSpace(ctx->module,
1253 LLVMArrayType(ctx->i32, 64),
1254 "ddxy_lds", LOCAL_ADDR_SPACE);
1255
1256 thread_id = get_thread_id(ctx);
1257 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1258 mask = TID_MASK_LEFT;
1259 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1260 mask = TID_MASK_TOP;
1261 else
1262 mask = TID_MASK_TOP_LEFT;
1263
1264 tl_tid = LLVMBuildAnd(ctx->builder, thread_id,
1265 LLVMConstInt(ctx->i32, mask, false), "");
1266 /* for DDX we want to next X pixel, DDY next Y pixel. */
1267 if (op == nir_op_fddx_fine ||
1268 op == nir_op_fddx_coarse ||
1269 op == nir_op_fddx)
1270 idx = 1;
1271 else
1272 idx = 2;
1273
1274 trbl_tid = LLVMBuildAdd(ctx->builder, tl_tid,
1275 LLVMConstInt(ctx->i32, idx, false), "");
1276
1277 if (ctx->has_ds_bpermute) {
1278 args[0] = LLVMBuildMul(ctx->builder, tl_tid,
1279 LLVMConstInt(ctx->i32, 4, false), "");
1280 args[1] = src0;
1281 tl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1282 ctx->i32, args, 2,
1283 AC_FUNC_ATTR_READNONE);
1284
1285 args[0] = LLVMBuildMul(ctx->builder, trbl_tid,
1286 LLVMConstInt(ctx->i32, 4, false), "");
1287 trbl = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.ds.bpermute",
1288 ctx->i32, args, 2,
1289 AC_FUNC_ATTR_READNONE);
1290 } else {
1291 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
1292
1293 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
1294 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
1295 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
1296
1297 LLVMBuildStore(ctx->builder, src0, store_ptr);
1298 tl = LLVMBuildLoad(ctx->builder, load_ptr0, "");
1299 trbl = LLVMBuildLoad(ctx->builder, load_ptr1, "");
1300 }
1301 tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
1302 trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
1303 result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
1304 return result;
1305 }
1306
1307 /*
1308 * this takes an I,J coordinate pair,
1309 * and works out the X and Y derivatives.
1310 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1311 */
1312 static LLVMValueRef emit_ddxy_interp(
1313 struct nir_to_llvm_context *ctx,
1314 LLVMValueRef interp_ij)
1315 {
1316 LLVMValueRef result[4], a;
1317 unsigned i;
1318
1319 for (i = 0; i < 2; i++) {
1320 a = LLVMBuildExtractElement(ctx->builder, interp_ij,
1321 LLVMConstInt(ctx->i32, i, false), "");
1322 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1323 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1324 }
1325 return ac_build_gather_values(&ctx->ac, result, 4);
1326 }
1327
1328 static void visit_alu(struct nir_to_llvm_context *ctx, nir_alu_instr *instr)
1329 {
1330 LLVMValueRef src[4], result = NULL;
1331 unsigned num_components = instr->dest.dest.ssa.num_components;
1332 unsigned src_components;
1333
1334 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1335 switch (instr->op) {
1336 case nir_op_vec2:
1337 case nir_op_vec3:
1338 case nir_op_vec4:
1339 src_components = 1;
1340 break;
1341 case nir_op_pack_half_2x16:
1342 src_components = 2;
1343 break;
1344 case nir_op_unpack_half_2x16:
1345 src_components = 1;
1346 break;
1347 default:
1348 src_components = num_components;
1349 break;
1350 }
1351 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1352 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1353
1354 switch (instr->op) {
1355 case nir_op_fmov:
1356 case nir_op_imov:
1357 result = src[0];
1358 break;
1359 case nir_op_fneg:
1360 src[0] = to_float(ctx, src[0]);
1361 result = LLVMBuildFNeg(ctx->builder, src[0], "");
1362 break;
1363 case nir_op_ineg:
1364 result = LLVMBuildNeg(ctx->builder, src[0], "");
1365 break;
1366 case nir_op_inot:
1367 result = LLVMBuildNot(ctx->builder, src[0], "");
1368 break;
1369 case nir_op_iadd:
1370 result = LLVMBuildAdd(ctx->builder, src[0], src[1], "");
1371 break;
1372 case nir_op_fadd:
1373 src[0] = to_float(ctx, src[0]);
1374 src[1] = to_float(ctx, src[1]);
1375 result = LLVMBuildFAdd(ctx->builder, src[0], src[1], "");
1376 break;
1377 case nir_op_fsub:
1378 src[0] = to_float(ctx, src[0]);
1379 src[1] = to_float(ctx, src[1]);
1380 result = LLVMBuildFSub(ctx->builder, src[0], src[1], "");
1381 break;
1382 case nir_op_isub:
1383 result = LLVMBuildSub(ctx->builder, src[0], src[1], "");
1384 break;
1385 case nir_op_imul:
1386 result = LLVMBuildMul(ctx->builder, src[0], src[1], "");
1387 break;
1388 case nir_op_imod:
1389 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1390 break;
1391 case nir_op_umod:
1392 result = LLVMBuildURem(ctx->builder, src[0], src[1], "");
1393 break;
1394 case nir_op_fmod:
1395 src[0] = to_float(ctx, src[0]);
1396 src[1] = to_float(ctx, src[1]);
1397 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1398 result = emit_intrin_1f_param(ctx, "llvm.floor.f32", result);
1399 result = LLVMBuildFMul(ctx->builder, src[1] , result, "");
1400 result = LLVMBuildFSub(ctx->builder, src[0], result, "");
1401 break;
1402 case nir_op_frem:
1403 src[0] = to_float(ctx, src[0]);
1404 src[1] = to_float(ctx, src[1]);
1405 result = LLVMBuildFRem(ctx->builder, src[0], src[1], "");
1406 break;
1407 case nir_op_irem:
1408 result = LLVMBuildSRem(ctx->builder, src[0], src[1], "");
1409 break;
1410 case nir_op_idiv:
1411 result = LLVMBuildSDiv(ctx->builder, src[0], src[1], "");
1412 break;
1413 case nir_op_udiv:
1414 result = LLVMBuildUDiv(ctx->builder, src[0], src[1], "");
1415 break;
1416 case nir_op_fmul:
1417 src[0] = to_float(ctx, src[0]);
1418 src[1] = to_float(ctx, src[1]);
1419 result = LLVMBuildFMul(ctx->builder, src[0], src[1], "");
1420 break;
1421 case nir_op_fdiv:
1422 src[0] = to_float(ctx, src[0]);
1423 src[1] = to_float(ctx, src[1]);
1424 result = ac_emit_fdiv(&ctx->ac, src[0], src[1]);
1425 break;
1426 case nir_op_frcp:
1427 src[0] = to_float(ctx, src[0]);
1428 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, src[0]);
1429 break;
1430 case nir_op_iand:
1431 result = LLVMBuildAnd(ctx->builder, src[0], src[1], "");
1432 break;
1433 case nir_op_ior:
1434 result = LLVMBuildOr(ctx->builder, src[0], src[1], "");
1435 break;
1436 case nir_op_ixor:
1437 result = LLVMBuildXor(ctx->builder, src[0], src[1], "");
1438 break;
1439 case nir_op_ishl:
1440 result = LLVMBuildShl(ctx->builder, src[0], src[1], "");
1441 break;
1442 case nir_op_ishr:
1443 result = LLVMBuildAShr(ctx->builder, src[0], src[1], "");
1444 break;
1445 case nir_op_ushr:
1446 result = LLVMBuildLShr(ctx->builder, src[0], src[1], "");
1447 break;
1448 case nir_op_ilt:
1449 result = emit_int_cmp(ctx, LLVMIntSLT, src[0], src[1]);
1450 break;
1451 case nir_op_ine:
1452 result = emit_int_cmp(ctx, LLVMIntNE, src[0], src[1]);
1453 break;
1454 case nir_op_ieq:
1455 result = emit_int_cmp(ctx, LLVMIntEQ, src[0], src[1]);
1456 break;
1457 case nir_op_ige:
1458 result = emit_int_cmp(ctx, LLVMIntSGE, src[0], src[1]);
1459 break;
1460 case nir_op_ult:
1461 result = emit_int_cmp(ctx, LLVMIntULT, src[0], src[1]);
1462 break;
1463 case nir_op_uge:
1464 result = emit_int_cmp(ctx, LLVMIntUGE, src[0], src[1]);
1465 break;
1466 case nir_op_feq:
1467 result = emit_float_cmp(ctx, LLVMRealUEQ, src[0], src[1]);
1468 break;
1469 case nir_op_fne:
1470 result = emit_float_cmp(ctx, LLVMRealUNE, src[0], src[1]);
1471 break;
1472 case nir_op_flt:
1473 result = emit_float_cmp(ctx, LLVMRealULT, src[0], src[1]);
1474 break;
1475 case nir_op_fge:
1476 result = emit_float_cmp(ctx, LLVMRealUGE, src[0], src[1]);
1477 break;
1478 case nir_op_fabs:
1479 result = emit_intrin_1f_param(ctx, "llvm.fabs.f32", src[0]);
1480 break;
1481 case nir_op_iabs:
1482 result = emit_iabs(ctx, src[0]);
1483 break;
1484 case nir_op_imax:
1485 result = emit_minmax_int(ctx, LLVMIntSGT, src[0], src[1]);
1486 break;
1487 case nir_op_imin:
1488 result = emit_minmax_int(ctx, LLVMIntSLT, src[0], src[1]);
1489 break;
1490 case nir_op_umax:
1491 result = emit_minmax_int(ctx, LLVMIntUGT, src[0], src[1]);
1492 break;
1493 case nir_op_umin:
1494 result = emit_minmax_int(ctx, LLVMIntULT, src[0], src[1]);
1495 break;
1496 case nir_op_isign:
1497 result = emit_isign(ctx, src[0]);
1498 break;
1499 case nir_op_fsign:
1500 src[0] = to_float(ctx, src[0]);
1501 result = emit_fsign(ctx, src[0]);
1502 break;
1503 case nir_op_ffloor:
1504 result = emit_intrin_1f_param(ctx, "llvm.floor.f32", src[0]);
1505 break;
1506 case nir_op_ftrunc:
1507 result = emit_intrin_1f_param(ctx, "llvm.trunc.f32", src[0]);
1508 break;
1509 case nir_op_fceil:
1510 result = emit_intrin_1f_param(ctx, "llvm.ceil.f32", src[0]);
1511 break;
1512 case nir_op_fround_even:
1513 result = emit_intrin_1f_param(ctx, "llvm.rint.f32", src[0]);
1514 break;
1515 case nir_op_ffract:
1516 result = emit_ffract(ctx, src[0]);
1517 break;
1518 case nir_op_fsin:
1519 result = emit_intrin_1f_param(ctx, "llvm.sin.f32", src[0]);
1520 break;
1521 case nir_op_fcos:
1522 result = emit_intrin_1f_param(ctx, "llvm.cos.f32", src[0]);
1523 break;
1524 case nir_op_fsqrt:
1525 result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
1526 break;
1527 case nir_op_fexp2:
1528 result = emit_intrin_1f_param(ctx, "llvm.exp2.f32", src[0]);
1529 break;
1530 case nir_op_flog2:
1531 result = emit_intrin_1f_param(ctx, "llvm.log2.f32", src[0]);
1532 break;
1533 case nir_op_frsq:
1534 result = emit_intrin_1f_param(ctx, "llvm.sqrt.f32", src[0]);
1535 result = ac_emit_fdiv(&ctx->ac, ctx->f32one, result);
1536 break;
1537 case nir_op_fpow:
1538 result = emit_intrin_2f_param(ctx, "llvm.pow.f32", src[0], src[1]);
1539 break;
1540 case nir_op_fmax:
1541 result = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", src[0], src[1]);
1542 break;
1543 case nir_op_fmin:
1544 result = emit_intrin_2f_param(ctx, "llvm.minnum.f32", src[0], src[1]);
1545 break;
1546 case nir_op_ffma:
1547 result = emit_intrin_3f_param(ctx, "llvm.fma.f32", src[0], src[1], src[2]);
1548 break;
1549 case nir_op_ibitfield_extract:
1550 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.i32", src);
1551 break;
1552 case nir_op_ubitfield_extract:
1553 result = emit_bitfield_extract(ctx, "llvm.AMDGPU.bfe.u32", src);
1554 break;
1555 case nir_op_bitfield_insert:
1556 result = emit_bitfield_insert(ctx, src[0], src[1], src[2], src[3]);
1557 break;
1558 case nir_op_bitfield_reverse:
1559 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1560 break;
1561 case nir_op_bit_count:
1562 result = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->i32, src, 1, AC_FUNC_ATTR_READNONE);
1563 break;
1564 case nir_op_vec2:
1565 case nir_op_vec3:
1566 case nir_op_vec4:
1567 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1568 src[i] = to_integer(ctx, src[i]);
1569 result = ac_build_gather_values(&ctx->ac, src, num_components);
1570 break;
1571 case nir_op_f2i:
1572 src[0] = to_float(ctx, src[0]);
1573 result = LLVMBuildFPToSI(ctx->builder, src[0], ctx->i32, "");
1574 break;
1575 case nir_op_f2u:
1576 src[0] = to_float(ctx, src[0]);
1577 result = LLVMBuildFPToUI(ctx->builder, src[0], ctx->i32, "");
1578 break;
1579 case nir_op_i2f:
1580 result = LLVMBuildSIToFP(ctx->builder, src[0], ctx->f32, "");
1581 break;
1582 case nir_op_u2f:
1583 result = LLVMBuildUIToFP(ctx->builder, src[0], ctx->f32, "");
1584 break;
1585 case nir_op_bcsel:
1586 result = emit_bcsel(ctx, src[0], src[1], src[2]);
1587 break;
1588 case nir_op_find_lsb:
1589 result = emit_find_lsb(ctx, src[0]);
1590 break;
1591 case nir_op_ufind_msb:
1592 result = emit_ufind_msb(ctx, src[0]);
1593 break;
1594 case nir_op_ifind_msb:
1595 result = emit_ifind_msb(ctx, src[0]);
1596 break;
1597 case nir_op_uadd_carry:
1598 result = emit_uint_carry(ctx, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1599 break;
1600 case nir_op_usub_borrow:
1601 result = emit_uint_carry(ctx, "llvm.usub.with.overflow.i32", src[0], src[1]);
1602 break;
1603 case nir_op_b2f:
1604 result = emit_b2f(ctx, src[0]);
1605 break;
1606 case nir_op_fquantize2f16:
1607 src[0] = to_float(ctx, src[0]);
1608 result = LLVMBuildFPTrunc(ctx->builder, src[0], ctx->f16, "");
1609 /* need to convert back up to f32 */
1610 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1611 break;
1612 case nir_op_umul_high:
1613 result = emit_umul_high(ctx, src[0], src[1]);
1614 break;
1615 case nir_op_imul_high:
1616 result = emit_imul_high(ctx, src[0], src[1]);
1617 break;
1618 case nir_op_pack_half_2x16:
1619 result = emit_pack_half_2x16(ctx, src[0]);
1620 break;
1621 case nir_op_unpack_half_2x16:
1622 result = emit_unpack_half_2x16(ctx, src[0]);
1623 break;
1624 case nir_op_fddx:
1625 case nir_op_fddy:
1626 case nir_op_fddx_fine:
1627 case nir_op_fddy_fine:
1628 case nir_op_fddx_coarse:
1629 case nir_op_fddy_coarse:
1630 result = emit_ddxy(ctx, instr->op, src[0]);
1631 break;
1632 default:
1633 fprintf(stderr, "Unknown NIR alu instr: ");
1634 nir_print_instr(&instr->instr, stderr);
1635 fprintf(stderr, "\n");
1636 abort();
1637 }
1638
1639 if (result) {
1640 assert(instr->dest.dest.is_ssa);
1641 result = to_integer(ctx, result);
1642 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
1643 result);
1644 }
1645 }
1646
1647 static void visit_load_const(struct nir_to_llvm_context *ctx,
1648 nir_load_const_instr *instr)
1649 {
1650 LLVMValueRef values[4], value = NULL;
1651 LLVMTypeRef element_type =
1652 LLVMIntTypeInContext(ctx->context, instr->def.bit_size);
1653
1654 for (unsigned i = 0; i < instr->def.num_components; ++i) {
1655 switch (instr->def.bit_size) {
1656 case 32:
1657 values[i] = LLVMConstInt(element_type,
1658 instr->value.u32[i], false);
1659 break;
1660 case 64:
1661 values[i] = LLVMConstInt(element_type,
1662 instr->value.u64[i], false);
1663 break;
1664 default:
1665 fprintf(stderr,
1666 "unsupported nir load_const bit_size: %d\n",
1667 instr->def.bit_size);
1668 abort();
1669 }
1670 }
1671 if (instr->def.num_components > 1) {
1672 value = LLVMConstVector(values, instr->def.num_components);
1673 } else
1674 value = values[0];
1675
1676 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
1677 }
1678
1679 static LLVMValueRef cast_ptr(struct nir_to_llvm_context *ctx, LLVMValueRef ptr,
1680 LLVMTypeRef type)
1681 {
1682 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1683 return LLVMBuildBitCast(ctx->builder, ptr,
1684 LLVMPointerType(type, addr_space), "");
1685 }
1686
1687 static LLVMValueRef
1688 get_buffer_size(struct nir_to_llvm_context *ctx, LLVMValueRef descriptor, bool in_elements)
1689 {
1690 LLVMValueRef size =
1691 LLVMBuildExtractElement(ctx->builder, descriptor,
1692 LLVMConstInt(ctx->i32, 2, false), "");
1693
1694 /* VI only */
1695 if (ctx->options->chip_class >= VI && in_elements) {
1696 /* On VI, the descriptor contains the size in bytes,
1697 * but TXQ must return the size in elements.
1698 * The stride is always non-zero for resources using TXQ.
1699 */
1700 LLVMValueRef stride =
1701 LLVMBuildExtractElement(ctx->builder, descriptor,
1702 LLVMConstInt(ctx->i32, 1, false), "");
1703 stride = LLVMBuildLShr(ctx->builder, stride,
1704 LLVMConstInt(ctx->i32, 16, false), "");
1705 stride = LLVMBuildAnd(ctx->builder, stride,
1706 LLVMConstInt(ctx->i32, 0x3fff, false), "");
1707
1708 size = LLVMBuildUDiv(ctx->builder, size, stride, "");
1709 }
1710 return size;
1711 }
1712
1713 /**
1714 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
1715 * intrinsic names).
1716 */
1717 static void build_int_type_name(
1718 LLVMTypeRef type,
1719 char *buf, unsigned bufsize)
1720 {
1721 assert(bufsize >= 6);
1722
1723 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
1724 snprintf(buf, bufsize, "v%ui32",
1725 LLVMGetVectorSize(type));
1726 else
1727 strcpy(buf, "i32");
1728 }
1729
1730 static LLVMValueRef radv_lower_gather4_integer(struct nir_to_llvm_context *ctx,
1731 struct ac_tex_info *tinfo,
1732 nir_tex_instr *instr,
1733 const char *intr_name,
1734 unsigned coord_vgpr_index)
1735 {
1736 LLVMValueRef coord = tinfo->args[0];
1737 LLVMValueRef half_texel[2];
1738 int c;
1739
1740 //TODO Rect
1741 {
1742 LLVMValueRef txq_args[10];
1743 int txq_arg_count = 0;
1744 LLVMValueRef size;
1745 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
1746 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, false);
1747 txq_args[txq_arg_count++] = tinfo->args[1];
1748 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0xf, 0); /* dmask */
1749 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* unorm */
1750 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
1751 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
1752 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
1753 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
1754 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
1755 txq_args[txq_arg_count++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
1756 size = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
1757 txq_args, txq_arg_count,
1758 AC_FUNC_ATTR_READNONE);
1759
1760 for (c = 0; c < 2; c++) {
1761 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
1762 LLVMConstInt(ctx->i32, c, false), "");
1763 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
1764 half_texel[c] = ac_emit_fdiv(&ctx->ac, ctx->f32one, half_texel[c]);
1765 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
1766 LLVMConstReal(ctx->f32, -0.5), "");
1767 }
1768 }
1769
1770 for (c = 0; c < 2; c++) {
1771 LLVMValueRef tmp;
1772 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
1773 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
1774 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
1775 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
1776 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
1777 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
1778 }
1779
1780 tinfo->args[0] = coord;
1781 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1782 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1783
1784 }
1785
1786 static LLVMValueRef build_tex_intrinsic(struct nir_to_llvm_context *ctx,
1787 nir_tex_instr *instr,
1788 struct ac_tex_info *tinfo)
1789 {
1790 const char *name = "llvm.SI.image.sample";
1791 const char *infix = "";
1792 char intr_name[127];
1793 char type[64];
1794 bool is_shadow = instr->is_shadow;
1795 bool has_offset = tinfo->has_offset;
1796 switch (instr->op) {
1797 case nir_texop_txf:
1798 case nir_texop_txf_ms:
1799 case nir_texop_samples_identical:
1800 name = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? "llvm.SI.image.load" :
1801 instr->sampler_dim == GLSL_SAMPLER_DIM_BUF ? "llvm.SI.vs.load.input" :
1802 "llvm.SI.image.load.mip";
1803 is_shadow = false;
1804 has_offset = false;
1805 break;
1806 case nir_texop_txb:
1807 infix = ".b";
1808 break;
1809 case nir_texop_txl:
1810 infix = ".l";
1811 break;
1812 case nir_texop_txs:
1813 name = "llvm.SI.getresinfo";
1814 break;
1815 case nir_texop_query_levels:
1816 name = "llvm.SI.getresinfo";
1817 break;
1818 case nir_texop_tex:
1819 if (ctx->stage != MESA_SHADER_FRAGMENT)
1820 infix = ".lz";
1821 break;
1822 case nir_texop_txd:
1823 infix = ".d";
1824 break;
1825 case nir_texop_tg4:
1826 name = "llvm.SI.gather4";
1827 infix = ".lz";
1828 break;
1829 case nir_texop_lod:
1830 name = "llvm.SI.getlod";
1831 is_shadow = false;
1832 has_offset = false;
1833 break;
1834 default:
1835 break;
1836 }
1837
1838 build_int_type_name(LLVMTypeOf(tinfo->args[0]), type, sizeof(type));
1839 sprintf(intr_name, "%s%s%s%s.%s", name, is_shadow ? ".c" : "", infix,
1840 has_offset ? ".o" : "", type);
1841
1842 if (instr->op == nir_texop_tg4) {
1843 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
1844 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
1845 return radv_lower_gather4_integer(ctx, tinfo, instr, intr_name,
1846 (int)has_offset + (int)is_shadow);
1847 }
1848 }
1849 return ac_emit_llvm_intrinsic(&ctx->ac, intr_name, tinfo->dst_type, tinfo->args, tinfo->arg_count,
1850 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
1851
1852 }
1853
1854 static LLVMValueRef visit_vulkan_resource_index(struct nir_to_llvm_context *ctx,
1855 nir_intrinsic_instr *instr)
1856 {
1857 LLVMValueRef index = get_src(ctx, instr->src[0]);
1858 unsigned desc_set = nir_intrinsic_desc_set(instr);
1859 unsigned binding = nir_intrinsic_binding(instr);
1860 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1861 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
1862 unsigned base_offset = layout->binding[binding].offset;
1863 LLVMValueRef offset, stride;
1864
1865 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1866 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1867 desc_ptr = ctx->push_constants;
1868 base_offset = ctx->options->layout->push_constant_size;
1869 base_offset += 16 * layout->binding[binding].dynamic_offset_offset;
1870 stride = LLVMConstInt(ctx->i32, 16, false);
1871 } else
1872 stride = LLVMConstInt(ctx->i32, layout->binding[binding].size, false);
1873
1874 offset = LLVMConstInt(ctx->i32, base_offset, false);
1875 index = LLVMBuildMul(ctx->builder, index, stride, "");
1876 offset = LLVMBuildAdd(ctx->builder, offset, index, "");
1877
1878 desc_ptr = build_gep0(ctx, desc_ptr, offset);
1879 desc_ptr = cast_ptr(ctx, desc_ptr, ctx->v4i32);
1880 LLVMSetMetadata(desc_ptr, ctx->uniform_md_kind, ctx->empty_md);
1881
1882 return LLVMBuildLoad(ctx->builder, desc_ptr, "");
1883 }
1884
1885 static LLVMValueRef visit_load_push_constant(struct nir_to_llvm_context *ctx,
1886 nir_intrinsic_instr *instr)
1887 {
1888 LLVMValueRef ptr, addr;
1889
1890 addr = LLVMConstInt(ctx->i32, nir_intrinsic_base(instr), 0);
1891 addr = LLVMBuildAdd(ctx->builder, addr, get_src(ctx, instr->src[0]), "");
1892
1893 ptr = build_gep0(ctx, ctx->push_constants, addr);
1894 ptr = cast_ptr(ctx, ptr, get_def_type(ctx, &instr->dest.ssa));
1895
1896 return LLVMBuildLoad(ctx->builder, ptr, "");
1897 }
1898
1899 static LLVMValueRef visit_get_buffer_size(struct nir_to_llvm_context *ctx,
1900 nir_intrinsic_instr *instr)
1901 {
1902 LLVMValueRef desc = get_src(ctx, instr->src[0]);
1903
1904 return get_buffer_size(ctx, desc, false);
1905 }
1906 static void visit_store_ssbo(struct nir_to_llvm_context *ctx,
1907 nir_intrinsic_instr *instr)
1908 {
1909 const char *store_name;
1910 LLVMTypeRef data_type = ctx->f32;
1911 unsigned writemask = nir_intrinsic_write_mask(instr);
1912 LLVMValueRef base_data, base_offset;
1913 LLVMValueRef params[6];
1914
1915 if (ctx->stage == MESA_SHADER_FRAGMENT)
1916 ctx->shader_info->fs.writes_memory = true;
1917
1918 params[1] = get_src(ctx, instr->src[1]);
1919 params[2] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1920 params[4] = LLVMConstInt(ctx->i1, 0, false); /* glc */
1921 params[5] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1922
1923 if (instr->num_components > 1)
1924 data_type = LLVMVectorType(ctx->f32, instr->num_components);
1925
1926 base_data = to_float(ctx, get_src(ctx, instr->src[0]));
1927 base_data = trim_vector(ctx, base_data, instr->num_components);
1928 base_data = LLVMBuildBitCast(ctx->builder, base_data,
1929 data_type, "");
1930 base_offset = get_src(ctx, instr->src[2]); /* voffset */
1931 while (writemask) {
1932 int start, count;
1933 LLVMValueRef data;
1934 LLVMValueRef offset;
1935 LLVMValueRef tmp;
1936 u_bit_scan_consecutive_range(&writemask, &start, &count);
1937
1938 /* Due to an LLVM limitation, split 3-element writes
1939 * into a 2-element and a 1-element write. */
1940 if (count == 3) {
1941 writemask |= 1 << (start + 2);
1942 count = 2;
1943 }
1944
1945 if (count == 4) {
1946 store_name = "llvm.amdgcn.buffer.store.v4f32";
1947 data = base_data;
1948 } else if (count == 2) {
1949 tmp = LLVMBuildExtractElement(ctx->builder,
1950 base_data, LLVMConstInt(ctx->i32, start, false), "");
1951 data = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), tmp,
1952 ctx->i32zero, "");
1953
1954 tmp = LLVMBuildExtractElement(ctx->builder,
1955 base_data, LLVMConstInt(ctx->i32, start + 1, false), "");
1956 data = LLVMBuildInsertElement(ctx->builder, data, tmp,
1957 ctx->i32one, "");
1958 store_name = "llvm.amdgcn.buffer.store.v2f32";
1959
1960 } else {
1961 assert(count == 1);
1962 if (get_llvm_num_components(base_data) > 1)
1963 data = LLVMBuildExtractElement(ctx->builder, base_data,
1964 LLVMConstInt(ctx->i32, start, false), "");
1965 else
1966 data = base_data;
1967 store_name = "llvm.amdgcn.buffer.store.f32";
1968 }
1969
1970 offset = base_offset;
1971 if (start != 0) {
1972 offset = LLVMBuildAdd(ctx->builder, offset, LLVMConstInt(ctx->i32, start * 4, false), "");
1973 }
1974 params[0] = data;
1975 params[3] = offset;
1976 ac_emit_llvm_intrinsic(&ctx->ac, store_name,
1977 ctx->voidt, params, 6, 0);
1978 }
1979 }
1980
1981 static LLVMValueRef visit_atomic_ssbo(struct nir_to_llvm_context *ctx,
1982 nir_intrinsic_instr *instr)
1983 {
1984 const char *name;
1985 LLVMValueRef params[6];
1986 int arg_count = 0;
1987 if (ctx->stage == MESA_SHADER_FRAGMENT)
1988 ctx->shader_info->fs.writes_memory = true;
1989
1990 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
1991 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[3]), 0);
1992 }
1993 params[arg_count++] = llvm_extract_elem(ctx, get_src(ctx, instr->src[2]), 0);
1994 params[arg_count++] = get_src(ctx, instr->src[0]);
1995 params[arg_count++] = LLVMConstInt(ctx->i32, 0, false); /* vindex */
1996 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
1997 params[arg_count++] = LLVMConstInt(ctx->i1, 0, false); /* slc */
1998
1999 switch (instr->intrinsic) {
2000 case nir_intrinsic_ssbo_atomic_add:
2001 name = "llvm.amdgcn.buffer.atomic.add";
2002 break;
2003 case nir_intrinsic_ssbo_atomic_imin:
2004 name = "llvm.amdgcn.buffer.atomic.smin";
2005 break;
2006 case nir_intrinsic_ssbo_atomic_umin:
2007 name = "llvm.amdgcn.buffer.atomic.umin";
2008 break;
2009 case nir_intrinsic_ssbo_atomic_imax:
2010 name = "llvm.amdgcn.buffer.atomic.smax";
2011 break;
2012 case nir_intrinsic_ssbo_atomic_umax:
2013 name = "llvm.amdgcn.buffer.atomic.umax";
2014 break;
2015 case nir_intrinsic_ssbo_atomic_and:
2016 name = "llvm.amdgcn.buffer.atomic.and";
2017 break;
2018 case nir_intrinsic_ssbo_atomic_or:
2019 name = "llvm.amdgcn.buffer.atomic.or";
2020 break;
2021 case nir_intrinsic_ssbo_atomic_xor:
2022 name = "llvm.amdgcn.buffer.atomic.xor";
2023 break;
2024 case nir_intrinsic_ssbo_atomic_exchange:
2025 name = "llvm.amdgcn.buffer.atomic.swap";
2026 break;
2027 case nir_intrinsic_ssbo_atomic_comp_swap:
2028 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2029 break;
2030 default:
2031 abort();
2032 }
2033
2034 return ac_emit_llvm_intrinsic(&ctx->ac, name, ctx->i32, params, arg_count, 0);
2035 }
2036
2037 static LLVMValueRef visit_load_buffer(struct nir_to_llvm_context *ctx,
2038 nir_intrinsic_instr *instr)
2039 {
2040 const char *load_name;
2041 LLVMTypeRef data_type = ctx->f32;
2042 if (instr->num_components == 3)
2043 data_type = LLVMVectorType(ctx->f32, 4);
2044 else if (instr->num_components > 1)
2045 data_type = LLVMVectorType(ctx->f32, instr->num_components);
2046
2047 if (instr->num_components == 4 || instr->num_components == 3)
2048 load_name = "llvm.amdgcn.buffer.load.v4f32";
2049 else if (instr->num_components == 2)
2050 load_name = "llvm.amdgcn.buffer.load.v2f32";
2051 else if (instr->num_components == 1)
2052 load_name = "llvm.amdgcn.buffer.load.f32";
2053 else
2054 abort();
2055
2056 LLVMValueRef params[] = {
2057 get_src(ctx, instr->src[0]),
2058 LLVMConstInt(ctx->i32, 0, false),
2059 get_src(ctx, instr->src[1]),
2060 LLVMConstInt(ctx->i1, 0, false),
2061 LLVMConstInt(ctx->i1, 0, false),
2062 };
2063
2064 LLVMValueRef ret =
2065 ac_emit_llvm_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2066
2067 if (instr->num_components == 3)
2068 ret = trim_vector(ctx, ret, 3);
2069
2070 return LLVMBuildBitCast(ctx->builder, ret,
2071 get_def_type(ctx, &instr->dest.ssa), "");
2072 }
2073
2074 static LLVMValueRef visit_load_ubo_buffer(struct nir_to_llvm_context *ctx,
2075 nir_intrinsic_instr *instr)
2076 {
2077 LLVMValueRef results[4], ret;
2078 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2079 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2080
2081 rsrc = LLVMBuildBitCast(ctx->builder, rsrc, LLVMVectorType(ctx->i8, 16), "");
2082
2083 for (unsigned i = 0; i < instr->num_components; ++i) {
2084 LLVMValueRef params[] = {
2085 rsrc,
2086 LLVMBuildAdd(ctx->builder, LLVMConstInt(ctx->i32, 4 * i, 0),
2087 offset, "")
2088 };
2089 results[i] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.load.const", ctx->f32,
2090 params, 2, AC_FUNC_ATTR_READNONE);
2091 }
2092
2093
2094 ret = ac_build_gather_values(&ctx->ac, results, instr->num_components);
2095 return LLVMBuildBitCast(ctx->builder, ret,
2096 get_def_type(ctx, &instr->dest.ssa), "");
2097 }
2098
2099 static void
2100 radv_get_deref_offset(struct nir_to_llvm_context *ctx, nir_deref *tail,
2101 bool vs_in, unsigned *vertex_index_out,
2102 unsigned *const_out, LLVMValueRef *indir_out)
2103 {
2104 unsigned const_offset = 0;
2105 LLVMValueRef offset = NULL;
2106
2107 if (vertex_index_out != NULL) {
2108 tail = tail->child;
2109 nir_deref_array *deref_array = nir_deref_as_array(tail);
2110 *vertex_index_out = deref_array->base_offset;
2111 }
2112
2113 while (tail->child != NULL) {
2114 const struct glsl_type *parent_type = tail->type;
2115 tail = tail->child;
2116
2117 if (tail->deref_type == nir_deref_type_array) {
2118 nir_deref_array *deref_array = nir_deref_as_array(tail);
2119 LLVMValueRef index, stride, local_offset;
2120 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2121
2122 const_offset += size * deref_array->base_offset;
2123 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2124 continue;
2125
2126 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2127 index = get_src(ctx, deref_array->indirect);
2128 stride = LLVMConstInt(ctx->i32, size, 0);
2129 local_offset = LLVMBuildMul(ctx->builder, stride, index, "");
2130
2131 if (offset)
2132 offset = LLVMBuildAdd(ctx->builder, offset, local_offset, "");
2133 else
2134 offset = local_offset;
2135 } else if (tail->deref_type == nir_deref_type_struct) {
2136 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2137
2138 for (unsigned i = 0; i < deref_struct->index; i++) {
2139 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2140 const_offset += glsl_count_attribute_slots(ft, vs_in);
2141 }
2142 } else
2143 unreachable("unsupported deref type");
2144
2145 }
2146
2147 if (const_offset && offset)
2148 offset = LLVMBuildAdd(ctx->builder, offset,
2149 LLVMConstInt(ctx->i32, const_offset, 0),
2150 "");
2151
2152 *const_out = const_offset;
2153 *indir_out = offset;
2154 }
2155
2156 static LLVMValueRef visit_load_var(struct nir_to_llvm_context *ctx,
2157 nir_intrinsic_instr *instr)
2158 {
2159 LLVMValueRef values[4];
2160 int idx = instr->variables[0]->var->data.driver_location;
2161 int ve = instr->dest.ssa.num_components;
2162 LLVMValueRef indir_index;
2163 unsigned const_index;
2164 switch (instr->variables[0]->var->data.mode) {
2165 case nir_var_shader_in:
2166 radv_get_deref_offset(ctx, &instr->variables[0]->deref,
2167 ctx->stage == MESA_SHADER_VERTEX, NULL,
2168 &const_index, &indir_index);
2169 for (unsigned chan = 0; chan < ve; chan++) {
2170 if (indir_index) {
2171 unsigned count = glsl_count_attribute_slots(
2172 instr->variables[0]->var->type,
2173 ctx->stage == MESA_SHADER_VERTEX);
2174 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2175 &ctx->ac, ctx->inputs + idx + chan, count,
2176 4, false);
2177
2178 values[chan] = LLVMBuildExtractElement(ctx->builder,
2179 tmp_vec,
2180 indir_index, "");
2181 } else
2182 values[chan] = ctx->inputs[idx + chan + const_index * 4];
2183 }
2184 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2185 break;
2186 case nir_var_local:
2187 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2188 NULL, &const_index, &indir_index);
2189 for (unsigned chan = 0; chan < ve; chan++) {
2190 if (indir_index) {
2191 unsigned count = glsl_count_attribute_slots(
2192 instr->variables[0]->var->type, false);
2193 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2194 &ctx->ac, ctx->locals + idx + chan, count,
2195 4, true);
2196
2197 values[chan] = LLVMBuildExtractElement(ctx->builder,
2198 tmp_vec,
2199 indir_index, "");
2200 } else {
2201 values[chan] = LLVMBuildLoad(ctx->builder, ctx->locals[idx + chan + const_index * 4], "");
2202 }
2203 }
2204 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2205 case nir_var_shader_out:
2206 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2207 NULL, &const_index, &indir_index);
2208 for (unsigned chan = 0; chan < ve; chan++) {
2209 if (indir_index) {
2210 unsigned count = glsl_count_attribute_slots(
2211 instr->variables[0]->var->type, false);
2212 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2213 &ctx->ac, ctx->outputs + idx + chan, count,
2214 4, true);
2215
2216 values[chan] = LLVMBuildExtractElement(ctx->builder,
2217 tmp_vec,
2218 indir_index, "");
2219 } else {
2220 values[chan] = LLVMBuildLoad(ctx->builder,
2221 ctx->outputs[idx + chan + const_index * 4],
2222 "");
2223 }
2224 }
2225 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2226 case nir_var_shared: {
2227 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2228 NULL, &const_index, &indir_index);
2229 LLVMValueRef ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2230 LLVMValueRef derived_ptr;
2231
2232 for (unsigned chan = 0; chan < ve; chan++) {
2233 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2234 if (indir_index)
2235 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2236 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2237 values[chan] = LLVMBuildLoad(ctx->builder, derived_ptr, "");
2238 }
2239 return to_integer(ctx, ac_build_gather_values(&ctx->ac, values, ve));
2240 }
2241 default:
2242 break;
2243 }
2244 return NULL;
2245 }
2246
2247 static void
2248 visit_store_var(struct nir_to_llvm_context *ctx,
2249 nir_intrinsic_instr *instr)
2250 {
2251 LLVMValueRef temp_ptr, value;
2252 int idx = instr->variables[0]->var->data.driver_location;
2253 LLVMValueRef src = to_float(ctx, get_src(ctx, instr->src[0]));
2254 int writemask = instr->const_index[0];
2255 LLVMValueRef indir_index;
2256 unsigned const_index;
2257 switch (instr->variables[0]->var->data.mode) {
2258 case nir_var_shader_out:
2259 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2260 NULL, &const_index, &indir_index);
2261 for (unsigned chan = 0; chan < 4; chan++) {
2262 int stride = 4;
2263 if (!(writemask & (1 << chan)))
2264 continue;
2265 if (get_llvm_num_components(src) == 1)
2266 value = src;
2267 else
2268 value = LLVMBuildExtractElement(ctx->builder, src,
2269 LLVMConstInt(ctx->i32,
2270 chan, false),
2271 "");
2272
2273 if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 ||
2274 instr->variables[0]->var->data.location == VARYING_SLOT_CULL_DIST0)
2275 stride = 1;
2276 if (indir_index) {
2277 unsigned count = glsl_count_attribute_slots(
2278 instr->variables[0]->var->type, false);
2279 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2280 &ctx->ac, ctx->outputs + idx + chan, count,
2281 stride, true);
2282
2283 if (get_llvm_num_components(tmp_vec) > 1) {
2284 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2285 value, indir_index, "");
2286 } else
2287 tmp_vec = value;
2288 build_store_values_extended(ctx, ctx->outputs + idx + chan,
2289 count, stride, tmp_vec);
2290
2291 } else {
2292 temp_ptr = ctx->outputs[idx + chan + const_index * stride];
2293
2294 LLVMBuildStore(ctx->builder, value, temp_ptr);
2295 }
2296 }
2297 break;
2298 case nir_var_local:
2299 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2300 NULL, &const_index, &indir_index);
2301 for (unsigned chan = 0; chan < 4; chan++) {
2302 if (!(writemask & (1 << chan)))
2303 continue;
2304
2305 if (get_llvm_num_components(src) == 1)
2306 value = src;
2307 else
2308 value = LLVMBuildExtractElement(ctx->builder, src,
2309 LLVMConstInt(ctx->i32, chan, false), "");
2310 if (indir_index) {
2311 unsigned count = glsl_count_attribute_slots(
2312 instr->variables[0]->var->type, false);
2313 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
2314 &ctx->ac, ctx->locals + idx + chan, count,
2315 4, true);
2316
2317 tmp_vec = LLVMBuildInsertElement(ctx->builder, tmp_vec,
2318 value, indir_index, "");
2319 build_store_values_extended(ctx, ctx->locals + idx + chan,
2320 count, 4, tmp_vec);
2321 } else {
2322 temp_ptr = ctx->locals[idx + chan + const_index * 4];
2323
2324 LLVMBuildStore(ctx->builder, value, temp_ptr);
2325 }
2326 }
2327 break;
2328 case nir_var_shared: {
2329 LLVMValueRef ptr;
2330 radv_get_deref_offset(ctx, &instr->variables[0]->deref, false,
2331 NULL, &const_index, &indir_index);
2332
2333 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2334 LLVMValueRef derived_ptr;
2335
2336 for (unsigned chan = 0; chan < 4; chan++) {
2337 if (!(writemask & (1 << chan)))
2338 continue;
2339
2340 LLVMValueRef index = LLVMConstInt(ctx->i32, chan, false);
2341
2342 if (get_llvm_num_components(src) == 1)
2343 value = src;
2344 else
2345 value = LLVMBuildExtractElement(ctx->builder, src,
2346 LLVMConstInt(ctx->i32,
2347 chan, false),
2348 "");
2349
2350 if (indir_index)
2351 index = LLVMBuildAdd(ctx->builder, index, indir_index, "");
2352
2353 derived_ptr = LLVMBuildGEP(ctx->builder, ptr, &index, 1, "");
2354 LLVMBuildStore(ctx->builder,
2355 to_integer(ctx, value), derived_ptr);
2356 }
2357 break;
2358 }
2359 default:
2360 break;
2361 }
2362 }
2363
2364 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
2365 {
2366 switch (dim) {
2367 case GLSL_SAMPLER_DIM_BUF:
2368 return 1;
2369 case GLSL_SAMPLER_DIM_1D:
2370 return array ? 2 : 1;
2371 case GLSL_SAMPLER_DIM_2D:
2372 return array ? 3 : 2;
2373 case GLSL_SAMPLER_DIM_MS:
2374 return array ? 4 : 3;
2375 case GLSL_SAMPLER_DIM_3D:
2376 case GLSL_SAMPLER_DIM_CUBE:
2377 return 3;
2378 case GLSL_SAMPLER_DIM_RECT:
2379 case GLSL_SAMPLER_DIM_SUBPASS:
2380 return 2;
2381 case GLSL_SAMPLER_DIM_SUBPASS_MS:
2382 return 3;
2383 default:
2384 break;
2385 }
2386 return 0;
2387 }
2388
2389 static LLVMValueRef get_image_coords(struct nir_to_llvm_context *ctx,
2390 nir_intrinsic_instr *instr)
2391 {
2392 const struct glsl_type *type = instr->variables[0]->var->type;
2393 if(instr->variables[0]->deref.child)
2394 type = instr->variables[0]->deref.child->type;
2395
2396 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
2397 LLVMValueRef coords[4];
2398 LLVMValueRef masks[] = {
2399 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
2400 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false),
2401 };
2402 LLVMValueRef res;
2403 int count;
2404 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
2405 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
2406 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2407 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
2408 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
2409
2410 count = image_type_to_components_count(dim,
2411 glsl_sampler_type_is_array(type));
2412
2413 if (count == 1) {
2414 if (instr->src[0].ssa->num_components)
2415 res = LLVMBuildExtractElement(ctx->builder, src0, masks[0], "");
2416 else
2417 res = src0;
2418 } else {
2419 int chan;
2420 if (is_ms)
2421 count--;
2422 for (chan = 0; chan < count; ++chan) {
2423 coords[chan] = LLVMBuildExtractElement(ctx->builder, src0, masks[chan], "");
2424 }
2425
2426 if (add_frag_pos) {
2427 for (chan = 0; chan < count; ++chan)
2428 coords[chan] = LLVMBuildAdd(ctx->builder, coords[chan], LLVMBuildFPToUI(ctx->builder, ctx->frag_pos[chan], ctx->i32, ""), "");
2429 }
2430 if (is_ms) {
2431 coords[count] = llvm_extract_elem(ctx, get_src(ctx, instr->src[1]), 0);
2432 count++;
2433 }
2434
2435 if (count == 3) {
2436 coords[3] = LLVMGetUndef(ctx->i32);
2437 count = 4;
2438 }
2439 res = ac_build_gather_values(&ctx->ac, coords, count);
2440 }
2441 return res;
2442 }
2443
2444 static void build_type_name_for_intr(
2445 LLVMTypeRef type,
2446 char *buf, unsigned bufsize)
2447 {
2448 LLVMTypeRef elem_type = type;
2449
2450 assert(bufsize >= 8);
2451
2452 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
2453 int ret = snprintf(buf, bufsize, "v%u",
2454 LLVMGetVectorSize(type));
2455 if (ret < 0) {
2456 char *type_name = LLVMPrintTypeToString(type);
2457 fprintf(stderr, "Error building type name for: %s\n",
2458 type_name);
2459 return;
2460 }
2461 elem_type = LLVMGetElementType(type);
2462 buf += ret;
2463 bufsize -= ret;
2464 }
2465 switch (LLVMGetTypeKind(elem_type)) {
2466 default: break;
2467 case LLVMIntegerTypeKind:
2468 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
2469 break;
2470 case LLVMFloatTypeKind:
2471 snprintf(buf, bufsize, "f32");
2472 break;
2473 case LLVMDoubleTypeKind:
2474 snprintf(buf, bufsize, "f64");
2475 break;
2476 }
2477 }
2478
2479 static void get_image_intr_name(const char *base_name,
2480 LLVMTypeRef data_type,
2481 LLVMTypeRef coords_type,
2482 LLVMTypeRef rsrc_type,
2483 char *out_name, unsigned out_len)
2484 {
2485 char coords_type_name[8];
2486
2487 build_type_name_for_intr(coords_type, coords_type_name,
2488 sizeof(coords_type_name));
2489
2490 if (HAVE_LLVM <= 0x0309) {
2491 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
2492 } else {
2493 char data_type_name[8];
2494 char rsrc_type_name[8];
2495
2496 build_type_name_for_intr(data_type, data_type_name,
2497 sizeof(data_type_name));
2498 build_type_name_for_intr(rsrc_type, rsrc_type_name,
2499 sizeof(rsrc_type_name));
2500 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
2501 data_type_name, coords_type_name, rsrc_type_name);
2502 }
2503 }
2504
2505 static LLVMValueRef visit_image_load(struct nir_to_llvm_context *ctx,
2506 nir_intrinsic_instr *instr)
2507 {
2508 LLVMValueRef params[7];
2509 LLVMValueRef res;
2510 char intrinsic_name[64];
2511 const nir_variable *var = instr->variables[0]->var;
2512 const struct glsl_type *type = var->type;
2513 if(instr->variables[0]->deref.child)
2514 type = instr->variables[0]->deref.child->type;
2515
2516 type = glsl_without_array(type);
2517 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2518 params[0] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2519 params[1] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2520 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2521 params[2] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2522 params[3] = LLVMConstInt(ctx->i1, 0, false); /* glc */
2523 params[4] = LLVMConstInt(ctx->i1, 0, false); /* slc */
2524 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.load.format.v4f32", ctx->v4f32,
2525 params, 5, 0);
2526
2527 res = trim_vector(ctx, res, instr->dest.ssa.num_components);
2528 res = to_integer(ctx, res);
2529 } else {
2530 bool is_da = glsl_sampler_type_is_array(type) ||
2531 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2532 LLVMValueRef da = is_da ? ctx->i32one : ctx->i32zero;
2533 LLVMValueRef glc = LLVMConstInt(ctx->i1, 0, false);
2534 LLVMValueRef slc = LLVMConstInt(ctx->i1, 0, false);
2535
2536 params[0] = get_image_coords(ctx, instr);
2537 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2538 params[2] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2539 if (HAVE_LLVM <= 0x0309) {
2540 params[3] = LLVMConstInt(ctx->i1, 0, false); /* r128 */
2541 params[4] = da;
2542 params[5] = glc;
2543 params[6] = slc;
2544 } else {
2545 LLVMValueRef lwe = LLVMConstInt(ctx->i1, 0, false);
2546 params[3] = glc;
2547 params[4] = slc;
2548 params[5] = lwe;
2549 params[6] = da;
2550 }
2551
2552 get_image_intr_name("llvm.amdgcn.image.load",
2553 ctx->v4f32, /* vdata */
2554 LLVMTypeOf(params[0]), /* coords */
2555 LLVMTypeOf(params[1]), /* rsrc */
2556 intrinsic_name, sizeof(intrinsic_name));
2557
2558 res = ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->v4f32,
2559 params, 7, AC_FUNC_ATTR_READONLY);
2560 }
2561 return to_integer(ctx, res);
2562 }
2563
2564 static void visit_image_store(struct nir_to_llvm_context *ctx,
2565 nir_intrinsic_instr *instr)
2566 {
2567 LLVMValueRef params[8];
2568 char intrinsic_name[64];
2569 const nir_variable *var = instr->variables[0]->var;
2570 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2571 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2572 const struct glsl_type *type = glsl_without_array(var->type);
2573
2574 if (ctx->stage == MESA_SHADER_FRAGMENT)
2575 ctx->shader_info->fs.writes_memory = true;
2576
2577 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2578 params[0] = to_float(ctx, get_src(ctx, instr->src[2])); /* data */
2579 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2580 params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2581 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2582 params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
2583 params[4] = i1false; /* glc */
2584 params[5] = i1false; /* slc */
2585 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
2586 params, 6, 0);
2587 } else {
2588 bool is_da = glsl_sampler_type_is_array(type) ||
2589 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2590 LLVMValueRef da = is_da ? i1true : i1false;
2591 LLVMValueRef glc = i1false;
2592 LLVMValueRef slc = i1false;
2593
2594 params[0] = to_float(ctx, get_src(ctx, instr->src[2]));
2595 params[1] = get_image_coords(ctx, instr); /* coords */
2596 params[2] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2597 params[3] = LLVMConstInt(ctx->i32, 15, false); /* dmask */
2598 if (HAVE_LLVM <= 0x0309) {
2599 params[4] = i1false; /* r128 */
2600 params[5] = da;
2601 params[6] = glc;
2602 params[7] = slc;
2603 } else {
2604 LLVMValueRef lwe = i1false;
2605 params[4] = glc;
2606 params[5] = slc;
2607 params[6] = lwe;
2608 params[7] = da;
2609 }
2610
2611 get_image_intr_name("llvm.amdgcn.image.store",
2612 LLVMTypeOf(params[0]), /* vdata */
2613 LLVMTypeOf(params[1]), /* coords */
2614 LLVMTypeOf(params[2]), /* rsrc */
2615 intrinsic_name, sizeof(intrinsic_name));
2616
2617 ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->voidt,
2618 params, 8, 0);
2619 }
2620
2621 }
2622
2623 static LLVMValueRef visit_image_atomic(struct nir_to_llvm_context *ctx,
2624 nir_intrinsic_instr *instr)
2625 {
2626 LLVMValueRef params[6];
2627 int param_count = 0;
2628 const nir_variable *var = instr->variables[0]->var;
2629 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
2630 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
2631 const char *base_name = "llvm.amdgcn.image.atomic";
2632 const char *atomic_name;
2633 LLVMValueRef coords;
2634 char intrinsic_name[32], coords_type[8];
2635 const struct glsl_type *type = glsl_without_array(var->type);
2636
2637 if (ctx->stage == MESA_SHADER_FRAGMENT)
2638 ctx->shader_info->fs.writes_memory = true;
2639
2640 params[param_count++] = get_src(ctx, instr->src[2]);
2641 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
2642 params[param_count++] = get_src(ctx, instr->src[3]);
2643
2644 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
2645 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER);
2646 coords = params[param_count++] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, instr->src[0]),
2647 LLVMConstInt(ctx->i32, 0, false), ""); /* vindex */
2648 params[param_count++] = ctx->i32zero; /* voffset */
2649 params[param_count++] = i1false; /* glc */
2650 params[param_count++] = i1false; /* slc */
2651 } else {
2652 bool da = glsl_sampler_type_is_array(type) ||
2653 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
2654
2655 coords = params[param_count++] = get_image_coords(ctx, instr);
2656 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2657 params[param_count++] = i1false; /* r128 */
2658 params[param_count++] = da ? i1true : i1false; /* da */
2659 params[param_count++] = i1false; /* slc */
2660 }
2661
2662 switch (instr->intrinsic) {
2663 case nir_intrinsic_image_atomic_add:
2664 atomic_name = "add";
2665 break;
2666 case nir_intrinsic_image_atomic_min:
2667 atomic_name = "smin";
2668 break;
2669 case nir_intrinsic_image_atomic_max:
2670 atomic_name = "smax";
2671 break;
2672 case nir_intrinsic_image_atomic_and:
2673 atomic_name = "and";
2674 break;
2675 case nir_intrinsic_image_atomic_or:
2676 atomic_name = "or";
2677 break;
2678 case nir_intrinsic_image_atomic_xor:
2679 atomic_name = "xor";
2680 break;
2681 case nir_intrinsic_image_atomic_exchange:
2682 atomic_name = "swap";
2683 break;
2684 case nir_intrinsic_image_atomic_comp_swap:
2685 atomic_name = "cmpswap";
2686 break;
2687 default:
2688 abort();
2689 }
2690 build_int_type_name(LLVMTypeOf(coords),
2691 coords_type, sizeof(coords_type));
2692
2693 snprintf(intrinsic_name, sizeof(intrinsic_name),
2694 "%s.%s.%s", base_name, atomic_name, coords_type);
2695 return ac_emit_llvm_intrinsic(&ctx->ac, intrinsic_name, ctx->i32, params, param_count, 0);
2696 }
2697
2698 static LLVMValueRef visit_image_size(struct nir_to_llvm_context *ctx,
2699 nir_intrinsic_instr *instr)
2700 {
2701 LLVMValueRef res;
2702 LLVMValueRef params[10];
2703 const nir_variable *var = instr->variables[0]->var;
2704 const struct glsl_type *type = instr->variables[0]->var->type;
2705 bool da = glsl_sampler_type_is_array(var->type) ||
2706 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE;
2707 if(instr->variables[0]->deref.child)
2708 type = instr->variables[0]->deref.child->type;
2709
2710 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
2711 return get_buffer_size(ctx, get_sampler_desc(ctx, instr->variables[0], DESC_BUFFER), true);
2712 params[0] = ctx->i32zero;
2713 params[1] = get_sampler_desc(ctx, instr->variables[0], DESC_IMAGE);
2714 params[2] = LLVMConstInt(ctx->i32, 15, false);
2715 params[3] = ctx->i32zero;
2716 params[4] = ctx->i32zero;
2717 params[5] = da ? ctx->i32one : ctx->i32zero;
2718 params[6] = ctx->i32zero;
2719 params[7] = ctx->i32zero;
2720 params[8] = ctx->i32zero;
2721 params[9] = ctx->i32zero;
2722
2723 res = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.getresinfo.i32", ctx->v4i32,
2724 params, 10, AC_FUNC_ATTR_READNONE);
2725
2726 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
2727 glsl_sampler_type_is_array(type)) {
2728 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
2729 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
2730 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, res, two, "");
2731 z = LLVMBuildSDiv(ctx->builder, z, six, "");
2732 res = LLVMBuildInsertElement(ctx->builder, res, z, two, "");
2733 }
2734 return res;
2735 }
2736
2737 static void emit_waitcnt(struct nir_to_llvm_context *ctx)
2738 {
2739 LLVMValueRef args[1] = {
2740 LLVMConstInt(ctx->i32, 0xf70, false),
2741 };
2742 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.waitcnt",
2743 ctx->voidt, args, 1, 0);
2744 }
2745
2746 static void emit_barrier(struct nir_to_llvm_context *ctx)
2747 {
2748 // TODO tess
2749 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.amdgcn.s.barrier",
2750 ctx->voidt, NULL, 0, 0);
2751 }
2752
2753 static void emit_discard_if(struct nir_to_llvm_context *ctx,
2754 nir_intrinsic_instr *instr)
2755 {
2756 LLVMValueRef cond;
2757 ctx->shader_info->fs.can_discard = true;
2758
2759 cond = LLVMBuildICmp(ctx->builder, LLVMIntNE,
2760 get_src(ctx, instr->src[0]),
2761 ctx->i32zero, "");
2762
2763 cond = LLVMBuildSelect(ctx->builder, cond,
2764 LLVMConstReal(ctx->f32, -1.0f),
2765 ctx->f32zero, "");
2766 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
2767 ctx->voidt,
2768 &cond, 1, 0);
2769 }
2770
2771 static LLVMValueRef
2772 visit_load_local_invocation_index(struct nir_to_llvm_context *ctx)
2773 {
2774 LLVMValueRef result;
2775 LLVMValueRef thread_id = get_thread_id(ctx);
2776 result = LLVMBuildAnd(ctx->builder, ctx->tg_size,
2777 LLVMConstInt(ctx->i32, 0xfc0, false), "");
2778
2779 return LLVMBuildAdd(ctx->builder, result, thread_id, "");
2780 }
2781
2782 static LLVMValueRef visit_var_atomic(struct nir_to_llvm_context *ctx,
2783 nir_intrinsic_instr *instr)
2784 {
2785 LLVMValueRef ptr, result;
2786 int idx = instr->variables[0]->var->data.driver_location;
2787 LLVMValueRef src = get_src(ctx, instr->src[0]);
2788 ptr = get_shared_memory_ptr(ctx, idx, ctx->i32);
2789
2790 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap) {
2791 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
2792 result = LLVMBuildAtomicCmpXchg(ctx->builder,
2793 ptr, src, src1,
2794 LLVMAtomicOrderingSequentiallyConsistent,
2795 LLVMAtomicOrderingSequentiallyConsistent,
2796 false);
2797 } else {
2798 LLVMAtomicRMWBinOp op;
2799 switch (instr->intrinsic) {
2800 case nir_intrinsic_var_atomic_add:
2801 op = LLVMAtomicRMWBinOpAdd;
2802 break;
2803 case nir_intrinsic_var_atomic_umin:
2804 op = LLVMAtomicRMWBinOpUMin;
2805 break;
2806 case nir_intrinsic_var_atomic_umax:
2807 op = LLVMAtomicRMWBinOpUMax;
2808 break;
2809 case nir_intrinsic_var_atomic_imin:
2810 op = LLVMAtomicRMWBinOpMin;
2811 break;
2812 case nir_intrinsic_var_atomic_imax:
2813 op = LLVMAtomicRMWBinOpMax;
2814 break;
2815 case nir_intrinsic_var_atomic_and:
2816 op = LLVMAtomicRMWBinOpAnd;
2817 break;
2818 case nir_intrinsic_var_atomic_or:
2819 op = LLVMAtomicRMWBinOpOr;
2820 break;
2821 case nir_intrinsic_var_atomic_xor:
2822 op = LLVMAtomicRMWBinOpXor;
2823 break;
2824 case nir_intrinsic_var_atomic_exchange:
2825 op = LLVMAtomicRMWBinOpXchg;
2826 break;
2827 default:
2828 return NULL;
2829 }
2830
2831 result = LLVMBuildAtomicRMW(ctx->builder, op, ptr, to_integer(ctx, src),
2832 LLVMAtomicOrderingSequentiallyConsistent,
2833 false);
2834 }
2835 return result;
2836 }
2837
2838 #define INTERP_CENTER 0
2839 #define INTERP_CENTROID 1
2840 #define INTERP_SAMPLE 2
2841
2842 static LLVMValueRef lookup_interp_param(struct nir_to_llvm_context *ctx,
2843 enum glsl_interp_mode interp, unsigned location)
2844 {
2845 switch (interp) {
2846 case INTERP_MODE_FLAT:
2847 default:
2848 return NULL;
2849 case INTERP_MODE_SMOOTH:
2850 case INTERP_MODE_NONE:
2851 if (location == INTERP_CENTER)
2852 return ctx->persp_center;
2853 else if (location == INTERP_CENTROID)
2854 return ctx->persp_centroid;
2855 else if (location == INTERP_SAMPLE)
2856 return ctx->persp_sample;
2857 break;
2858 case INTERP_MODE_NOPERSPECTIVE:
2859 if (location == INTERP_CENTER)
2860 return ctx->linear_center;
2861 else if (location == INTERP_CENTROID)
2862 return ctx->linear_centroid;
2863 else if (location == INTERP_SAMPLE)
2864 return ctx->linear_sample;
2865 break;
2866 }
2867 return NULL;
2868 }
2869
2870 static LLVMValueRef load_sample_position(struct nir_to_llvm_context *ctx,
2871 LLVMValueRef sample_id)
2872 {
2873 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
2874 LLVMValueRef offset0 = LLVMBuildMul(ctx->builder, sample_id, LLVMConstInt(ctx->i32, 8, false), "");
2875 LLVMValueRef offset1 = LLVMBuildAdd(ctx->builder, offset0, LLVMConstInt(ctx->i32, 4, false), "");
2876 LLVMValueRef result[2];
2877
2878 result[0] = build_indexed_load_const(ctx, ctx->sample_positions, offset0);
2879 result[1] = build_indexed_load_const(ctx, ctx->sample_positions, offset1);
2880
2881 return ac_build_gather_values(&ctx->ac, result, 2);
2882 }
2883
2884 static LLVMValueRef load_sample_pos(struct nir_to_llvm_context *ctx)
2885 {
2886 LLVMValueRef values[2];
2887
2888 values[0] = emit_ffract(ctx, ctx->frag_pos[0]);
2889 values[1] = emit_ffract(ctx, ctx->frag_pos[1]);
2890 return ac_build_gather_values(&ctx->ac, values, 2);
2891 }
2892
2893 static LLVMValueRef visit_interp(struct nir_to_llvm_context *ctx,
2894 nir_intrinsic_instr *instr)
2895 {
2896 LLVMValueRef result[2];
2897 LLVMValueRef interp_param, attr_number;
2898 unsigned location;
2899 unsigned chan;
2900 LLVMValueRef src_c0, src_c1;
2901 const char *intr_name;
2902 LLVMValueRef src0;
2903 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
2904 switch (instr->intrinsic) {
2905 case nir_intrinsic_interp_var_at_centroid:
2906 location = INTERP_CENTROID;
2907 break;
2908 case nir_intrinsic_interp_var_at_sample:
2909 case nir_intrinsic_interp_var_at_offset:
2910 location = INTERP_SAMPLE;
2911 src0 = get_src(ctx, instr->src[0]);
2912 break;
2913 default:
2914 break;
2915 }
2916
2917 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
2918 src_c0 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32zero, ""));
2919 src_c1 = to_float(ctx, LLVMBuildExtractElement(ctx->builder, src0, ctx->i32one, ""));
2920 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
2921 LLVMValueRef sample_position;
2922 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
2923
2924 /* fetch sample ID */
2925 sample_position = load_sample_position(ctx, src0);
2926
2927 src_c0 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32zero, "");
2928 src_c0 = LLVMBuildFSub(ctx->builder, src_c0, halfval, "");
2929 src_c1 = LLVMBuildExtractElement(ctx->builder, sample_position, ctx->i32one, "");
2930 src_c1 = LLVMBuildFSub(ctx->builder, src_c1, halfval, "");
2931 }
2932 interp_param = lookup_interp_param(ctx, instr->variables[0]->var->data.interpolation, location);
2933 attr_number = LLVMConstInt(ctx->i32, input_index, false);
2934
2935 if (location == INTERP_SAMPLE) {
2936 LLVMValueRef ij_out[2];
2937 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
2938
2939 /*
2940 * take the I then J parameters, and the DDX/Y for it, and
2941 * calculate the IJ inputs for the interpolator.
2942 * temp1 = ddx * offset/sample.x + I;
2943 * interp_param.I = ddy * offset/sample.y + temp1;
2944 * temp1 = ddx * offset/sample.x + J;
2945 * interp_param.J = ddy * offset/sample.y + temp1;
2946 */
2947 for (unsigned i = 0; i < 2; i++) {
2948 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, false);
2949 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, false);
2950 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->builder,
2951 ddxy_out, ix_ll, "");
2952 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->builder,
2953 ddxy_out, iy_ll, "");
2954 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->builder,
2955 interp_param, ix_ll, "");
2956 LLVMValueRef temp1, temp2;
2957
2958 interp_el = LLVMBuildBitCast(ctx->builder, interp_el,
2959 ctx->f32, "");
2960
2961 temp1 = LLVMBuildFMul(ctx->builder, ddx_el, src_c0, "");
2962 temp1 = LLVMBuildFAdd(ctx->builder, temp1, interp_el, "");
2963
2964 temp2 = LLVMBuildFMul(ctx->builder, ddy_el, src_c1, "");
2965 temp2 = LLVMBuildFAdd(ctx->builder, temp2, temp1, "");
2966
2967 ij_out[i] = LLVMBuildBitCast(ctx->builder,
2968 temp2, ctx->i32, "");
2969 }
2970 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
2971
2972 }
2973 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
2974 for (chan = 0; chan < 2; chan++) {
2975 LLVMValueRef args[4];
2976 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
2977
2978 args[0] = llvm_chan;
2979 args[1] = attr_number;
2980 args[2] = ctx->prim_mask;
2981 args[3] = interp_param;
2982 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
2983 ctx->f32, args, args[3] ? 4 : 3,
2984 AC_FUNC_ATTR_READNONE);
2985 }
2986 return ac_build_gather_values(&ctx->ac, result, 2);
2987 }
2988
2989 static void
2990 visit_emit_vertex(struct nir_to_llvm_context *ctx,
2991 nir_intrinsic_instr *instr)
2992 {
2993 LLVMValueRef gs_next_vertex;
2994 LLVMValueRef can_emit, kill;
2995 LLVMValueRef args[2];
2996 int idx;
2997
2998 assert(instr->const_index[0] == 0);
2999 /* Write vertex attribute values to GSVS ring */
3000 gs_next_vertex = LLVMBuildLoad(ctx->builder,
3001 ctx->gs_next_vertex,
3002 "");
3003
3004 /* If this thread has already emitted the declared maximum number of
3005 * vertices, kill it: excessive vertex emissions are not supposed to
3006 * have any effect, and GS threads have no externally observable
3007 * effects other than emitting vertices.
3008 */
3009 can_emit = LLVMBuildICmp(ctx->builder, LLVMIntULT, gs_next_vertex,
3010 LLVMConstInt(ctx->i32, ctx->gs_max_out_vertices, false), "");
3011
3012 kill = LLVMBuildSelect(ctx->builder, can_emit,
3013 LLVMConstReal(ctx->f32, 1.0f),
3014 LLVMConstReal(ctx->f32, -1.0f), "");
3015 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kill",
3016 ctx->voidt, &kill, 1, 0);
3017
3018 /* loop num outputs */
3019 idx = 0;
3020 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
3021 LLVMValueRef *out_ptr = &ctx->outputs[i * 4];
3022 if (!(ctx->output_mask & (1ull << i)))
3023 continue;
3024
3025 for (unsigned j = 0; j < 4; j++) {
3026 LLVMValueRef out_val = LLVMBuildLoad(ctx->builder,
3027 out_ptr[j], "");
3028 LLVMValueRef voffset = LLVMConstInt(ctx->i32, (idx * 4 + j) * ctx->gs_max_out_vertices, false);
3029 voffset = LLVMBuildAdd(ctx->builder, voffset, gs_next_vertex, "");
3030 voffset = LLVMBuildMul(ctx->builder, voffset, LLVMConstInt(ctx->i32, 4, false), "");
3031
3032 out_val = LLVMBuildBitCast(ctx->builder, out_val, ctx->i32, "");
3033
3034 build_tbuffer_store(ctx, ctx->gsvs_ring,
3035 out_val, 1,
3036 voffset, ctx->gs2vs_offset, 0,
3037 V_008F0C_BUF_DATA_FORMAT_32,
3038 V_008F0C_BUF_NUM_FORMAT_UINT,
3039 1, 0, 1, 1, 0);
3040 }
3041 idx++;
3042 }
3043
3044 gs_next_vertex = LLVMBuildAdd(ctx->builder, gs_next_vertex,
3045 ctx->i32one, "");
3046 LLVMBuildStore(ctx->builder, gs_next_vertex, ctx->gs_next_vertex);
3047 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (0 << 8), false);
3048 args[1] = ctx->gs_wave_id;
3049 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
3050 ctx->voidt, args, 2, 0);
3051 }
3052
3053 static void
3054 visit_end_primitive(struct nir_to_llvm_context *ctx,
3055 nir_intrinsic_instr *instr)
3056 {
3057 LLVMValueRef args[2];
3058
3059 assert(instr->const_index[0] == 0);
3060 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_CUT | SENDMSG_GS | (0 << 8), false);
3061 args[1] = ctx->gs_wave_id;
3062
3063 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg", ctx->voidt,
3064 args, 2, 0);
3065 }
3066
3067 static void visit_intrinsic(struct nir_to_llvm_context *ctx,
3068 nir_intrinsic_instr *instr)
3069 {
3070 LLVMValueRef result = NULL;
3071
3072 switch (instr->intrinsic) {
3073 case nir_intrinsic_load_work_group_id: {
3074 result = ctx->workgroup_ids;
3075 break;
3076 }
3077 case nir_intrinsic_load_base_vertex: {
3078 result = ctx->base_vertex;
3079 break;
3080 }
3081 case nir_intrinsic_load_vertex_id_zero_base: {
3082 result = ctx->vertex_id;
3083 break;
3084 }
3085 case nir_intrinsic_load_local_invocation_id: {
3086 result = ctx->local_invocation_ids;
3087 break;
3088 }
3089 case nir_intrinsic_load_base_instance:
3090 result = ctx->start_instance;
3091 break;
3092 case nir_intrinsic_load_invocation_id:
3093 result = ctx->gs_invocation_id;
3094 break;
3095 case nir_intrinsic_load_primitive_id:
3096 if (ctx->stage == MESA_SHADER_GEOMETRY)
3097 result = ctx->gs_prim_id;
3098 else
3099 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
3100 break;
3101 case nir_intrinsic_load_sample_id:
3102 ctx->shader_info->fs.force_persample = true;
3103 result = unpack_param(ctx, ctx->ancillary, 8, 4);
3104 break;
3105 case nir_intrinsic_load_sample_pos:
3106 ctx->shader_info->fs.force_persample = true;
3107 result = load_sample_pos(ctx);
3108 break;
3109 case nir_intrinsic_load_front_face:
3110 result = ctx->front_face;
3111 break;
3112 case nir_intrinsic_load_instance_id:
3113 result = ctx->instance_id;
3114 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3115 ctx->shader_info->vs.vgpr_comp_cnt);
3116 break;
3117 case nir_intrinsic_load_num_work_groups:
3118 result = ctx->num_work_groups;
3119 break;
3120 case nir_intrinsic_load_local_invocation_index:
3121 result = visit_load_local_invocation_index(ctx);
3122 break;
3123 case nir_intrinsic_load_push_constant:
3124 result = visit_load_push_constant(ctx, instr);
3125 break;
3126 case nir_intrinsic_vulkan_resource_index:
3127 result = visit_vulkan_resource_index(ctx, instr);
3128 break;
3129 case nir_intrinsic_store_ssbo:
3130 visit_store_ssbo(ctx, instr);
3131 break;
3132 case nir_intrinsic_load_ssbo:
3133 result = visit_load_buffer(ctx, instr);
3134 break;
3135 case nir_intrinsic_ssbo_atomic_add:
3136 case nir_intrinsic_ssbo_atomic_imin:
3137 case nir_intrinsic_ssbo_atomic_umin:
3138 case nir_intrinsic_ssbo_atomic_imax:
3139 case nir_intrinsic_ssbo_atomic_umax:
3140 case nir_intrinsic_ssbo_atomic_and:
3141 case nir_intrinsic_ssbo_atomic_or:
3142 case nir_intrinsic_ssbo_atomic_xor:
3143 case nir_intrinsic_ssbo_atomic_exchange:
3144 case nir_intrinsic_ssbo_atomic_comp_swap:
3145 result = visit_atomic_ssbo(ctx, instr);
3146 break;
3147 case nir_intrinsic_load_ubo:
3148 result = visit_load_ubo_buffer(ctx, instr);
3149 break;
3150 case nir_intrinsic_get_buffer_size:
3151 result = visit_get_buffer_size(ctx, instr);
3152 break;
3153 case nir_intrinsic_load_var:
3154 result = visit_load_var(ctx, instr);
3155 break;
3156 case nir_intrinsic_store_var:
3157 visit_store_var(ctx, instr);
3158 break;
3159 case nir_intrinsic_image_load:
3160 result = visit_image_load(ctx, instr);
3161 break;
3162 case nir_intrinsic_image_store:
3163 visit_image_store(ctx, instr);
3164 break;
3165 case nir_intrinsic_image_atomic_add:
3166 case nir_intrinsic_image_atomic_min:
3167 case nir_intrinsic_image_atomic_max:
3168 case nir_intrinsic_image_atomic_and:
3169 case nir_intrinsic_image_atomic_or:
3170 case nir_intrinsic_image_atomic_xor:
3171 case nir_intrinsic_image_atomic_exchange:
3172 case nir_intrinsic_image_atomic_comp_swap:
3173 result = visit_image_atomic(ctx, instr);
3174 break;
3175 case nir_intrinsic_image_size:
3176 result = visit_image_size(ctx, instr);
3177 break;
3178 case nir_intrinsic_discard:
3179 ctx->shader_info->fs.can_discard = true;
3180 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.AMDGPU.kilp",
3181 ctx->voidt,
3182 NULL, 0, 0);
3183 break;
3184 case nir_intrinsic_discard_if:
3185 emit_discard_if(ctx, instr);
3186 break;
3187 case nir_intrinsic_memory_barrier:
3188 emit_waitcnt(ctx);
3189 break;
3190 case nir_intrinsic_barrier:
3191 emit_barrier(ctx);
3192 break;
3193 case nir_intrinsic_var_atomic_add:
3194 case nir_intrinsic_var_atomic_imin:
3195 case nir_intrinsic_var_atomic_umin:
3196 case nir_intrinsic_var_atomic_imax:
3197 case nir_intrinsic_var_atomic_umax:
3198 case nir_intrinsic_var_atomic_and:
3199 case nir_intrinsic_var_atomic_or:
3200 case nir_intrinsic_var_atomic_xor:
3201 case nir_intrinsic_var_atomic_exchange:
3202 case nir_intrinsic_var_atomic_comp_swap:
3203 result = visit_var_atomic(ctx, instr);
3204 break;
3205 case nir_intrinsic_interp_var_at_centroid:
3206 case nir_intrinsic_interp_var_at_sample:
3207 case nir_intrinsic_interp_var_at_offset:
3208 result = visit_interp(ctx, instr);
3209 break;
3210 case nir_intrinsic_emit_vertex:
3211 visit_emit_vertex(ctx, instr);
3212 break;
3213 case nir_intrinsic_end_primitive:
3214 visit_end_primitive(ctx, instr);
3215 break;
3216 default:
3217 fprintf(stderr, "Unknown intrinsic: ");
3218 nir_print_instr(&instr->instr, stderr);
3219 fprintf(stderr, "\n");
3220 break;
3221 }
3222 if (result) {
3223 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3224 }
3225 }
3226
3227 static LLVMValueRef get_sampler_desc(struct nir_to_llvm_context *ctx,
3228 nir_deref_var *deref,
3229 enum desc_type desc_type)
3230 {
3231 unsigned desc_set = deref->var->data.descriptor_set;
3232 LLVMValueRef list = ctx->descriptor_sets[desc_set];
3233 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[desc_set].layout;
3234 struct radv_descriptor_set_binding_layout *binding = layout->binding + deref->var->data.binding;
3235 unsigned offset = binding->offset;
3236 unsigned stride = binding->size;
3237 unsigned type_size;
3238 LLVMBuilderRef builder = ctx->builder;
3239 LLVMTypeRef type;
3240 LLVMValueRef index = NULL;
3241
3242 assert(deref->var->data.binding < layout->binding_count);
3243
3244 switch (desc_type) {
3245 case DESC_IMAGE:
3246 type = ctx->v8i32;
3247 type_size = 32;
3248 break;
3249 case DESC_FMASK:
3250 type = ctx->v8i32;
3251 offset += 32;
3252 type_size = 32;
3253 break;
3254 case DESC_SAMPLER:
3255 type = ctx->v4i32;
3256 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
3257 offset += 64;
3258
3259 type_size = 16;
3260 break;
3261 case DESC_BUFFER:
3262 type = ctx->v4i32;
3263 type_size = 16;
3264 break;
3265 default:
3266 unreachable("invalid desc_type\n");
3267 }
3268
3269 if (deref->deref.child) {
3270 nir_deref_array *child = (nir_deref_array*)deref->deref.child;
3271
3272 assert(child->deref_array_type != nir_deref_array_type_wildcard);
3273 offset += child->base_offset * stride;
3274 if (child->deref_array_type == nir_deref_array_type_indirect) {
3275 index = get_src(ctx, child->indirect);
3276 }
3277 }
3278
3279 assert(stride % type_size == 0);
3280
3281 if (!index)
3282 index = ctx->i32zero;
3283
3284 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, stride / type_size, 0), "");
3285
3286 list = build_gep0(ctx, list, LLVMConstInt(ctx->i32, offset, 0));
3287 list = LLVMBuildPointerCast(builder, list, const_array(type, 0), "");
3288
3289 return build_indexed_load_const(ctx, list, index);
3290 }
3291
3292 static void set_tex_fetch_args(struct nir_to_llvm_context *ctx,
3293 struct ac_tex_info *tinfo,
3294 nir_tex_instr *instr,
3295 nir_texop op,
3296 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
3297 LLVMValueRef *param, unsigned count,
3298 unsigned dmask)
3299 {
3300 int num_args;
3301 unsigned is_rect = 0;
3302 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
3303
3304 if (op == nir_texop_lod)
3305 da = false;
3306 /* Pad to power of two vector */
3307 while (count < util_next_power_of_two(count))
3308 param[count++] = LLVMGetUndef(ctx->i32);
3309
3310 if (count > 1)
3311 tinfo->args[0] = ac_build_gather_values(&ctx->ac, param, count);
3312 else
3313 tinfo->args[0] = param[0];
3314
3315 tinfo->args[1] = res_ptr;
3316 num_args = 2;
3317
3318 if (op == nir_texop_txf ||
3319 op == nir_texop_txf_ms ||
3320 op == nir_texop_query_levels ||
3321 op == nir_texop_texture_samples ||
3322 op == nir_texop_txs)
3323 tinfo->dst_type = ctx->v4i32;
3324 else {
3325 tinfo->dst_type = ctx->v4f32;
3326 tinfo->args[num_args++] = samp_ptr;
3327 }
3328
3329 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
3330 tinfo->args[0] = res_ptr;
3331 tinfo->args[1] = LLVMConstInt(ctx->i32, 0, false);
3332 tinfo->args[2] = param[0];
3333 tinfo->arg_count = 3;
3334 return;
3335 }
3336
3337 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, dmask, 0);
3338 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, is_rect, 0); /* unorm */
3339 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* r128 */
3340 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, da ? 1 : 0, 0);
3341 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* glc */
3342 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* slc */
3343 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* tfe */
3344 tinfo->args[num_args++] = LLVMConstInt(ctx->i32, 0, 0); /* lwe */
3345
3346 tinfo->arg_count = num_args;
3347 }
3348
3349 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
3350 *
3351 * SI-CI:
3352 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
3353 * filtering manually. The driver sets img7 to a mask clearing
3354 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
3355 * s_and_b32 samp0, samp0, img7
3356 *
3357 * VI:
3358 * The ANISO_OVERRIDE sampler field enables this fix in TA.
3359 */
3360 static LLVMValueRef sici_fix_sampler_aniso(struct nir_to_llvm_context *ctx,
3361 LLVMValueRef res, LLVMValueRef samp)
3362 {
3363 LLVMBuilderRef builder = ctx->builder;
3364 LLVMValueRef img7, samp0;
3365
3366 if (ctx->options->chip_class >= VI)
3367 return samp;
3368
3369 img7 = LLVMBuildExtractElement(builder, res,
3370 LLVMConstInt(ctx->i32, 7, 0), "");
3371 samp0 = LLVMBuildExtractElement(builder, samp,
3372 LLVMConstInt(ctx->i32, 0, 0), "");
3373 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
3374 return LLVMBuildInsertElement(builder, samp, samp0,
3375 LLVMConstInt(ctx->i32, 0, 0), "");
3376 }
3377
3378 static void tex_fetch_ptrs(struct nir_to_llvm_context *ctx,
3379 nir_tex_instr *instr,
3380 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
3381 LLVMValueRef *fmask_ptr)
3382 {
3383 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
3384 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_BUFFER);
3385 else
3386 *res_ptr = get_sampler_desc(ctx, instr->texture, DESC_IMAGE);
3387 if (samp_ptr) {
3388 if (instr->sampler)
3389 *samp_ptr = get_sampler_desc(ctx, instr->sampler, DESC_SAMPLER);
3390 else
3391 *samp_ptr = get_sampler_desc(ctx, instr->texture, DESC_SAMPLER);
3392 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
3393 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
3394 }
3395 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
3396 instr->op == nir_texop_samples_identical))
3397 *fmask_ptr = get_sampler_desc(ctx, instr->texture, DESC_FMASK);
3398 }
3399
3400 static void visit_tex(struct nir_to_llvm_context *ctx, nir_tex_instr *instr)
3401 {
3402 LLVMValueRef result = NULL;
3403 struct ac_tex_info tinfo = { 0 };
3404 unsigned dmask = 0xf;
3405 LLVMValueRef address[16];
3406 LLVMValueRef coords[5];
3407 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
3408 LLVMValueRef bias = NULL, offsets = NULL;
3409 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
3410 LLVMValueRef ddx = NULL, ddy = NULL;
3411 LLVMValueRef derivs[6];
3412 unsigned chan, count = 0;
3413 unsigned const_src = 0, num_deriv_comp = 0;
3414
3415 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
3416
3417 for (unsigned i = 0; i < instr->num_srcs; i++) {
3418 switch (instr->src[i].src_type) {
3419 case nir_tex_src_coord:
3420 coord = get_src(ctx, instr->src[i].src);
3421 break;
3422 case nir_tex_src_projector:
3423 break;
3424 case nir_tex_src_comparator:
3425 comparator = get_src(ctx, instr->src[i].src);
3426 break;
3427 case nir_tex_src_offset:
3428 offsets = get_src(ctx, instr->src[i].src);
3429 const_src = i;
3430 break;
3431 case nir_tex_src_bias:
3432 bias = get_src(ctx, instr->src[i].src);
3433 break;
3434 case nir_tex_src_lod:
3435 lod = get_src(ctx, instr->src[i].src);
3436 break;
3437 case nir_tex_src_ms_index:
3438 sample_index = get_src(ctx, instr->src[i].src);
3439 break;
3440 case nir_tex_src_ms_mcs:
3441 break;
3442 case nir_tex_src_ddx:
3443 ddx = get_src(ctx, instr->src[i].src);
3444 num_deriv_comp = instr->src[i].src.ssa->num_components;
3445 break;
3446 case nir_tex_src_ddy:
3447 ddy = get_src(ctx, instr->src[i].src);
3448 break;
3449 case nir_tex_src_texture_offset:
3450 case nir_tex_src_sampler_offset:
3451 case nir_tex_src_plane:
3452 default:
3453 break;
3454 }
3455 }
3456
3457 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
3458 result = get_buffer_size(ctx, res_ptr, false);
3459 goto write_result;
3460 }
3461
3462 if (instr->op == nir_texop_texture_samples) {
3463 LLVMValueRef res, samples, is_msaa;
3464 res = LLVMBuildBitCast(ctx->builder, res_ptr, ctx->v8i32, "");
3465 samples = LLVMBuildExtractElement(ctx->builder, res,
3466 LLVMConstInt(ctx->i32, 3, false), "");
3467 is_msaa = LLVMBuildLShr(ctx->builder, samples,
3468 LLVMConstInt(ctx->i32, 28, false), "");
3469 is_msaa = LLVMBuildAnd(ctx->builder, is_msaa,
3470 LLVMConstInt(ctx->i32, 0xe, false), "");
3471 is_msaa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, is_msaa,
3472 LLVMConstInt(ctx->i32, 0xe, false), "");
3473
3474 samples = LLVMBuildLShr(ctx->builder, samples,
3475 LLVMConstInt(ctx->i32, 16, false), "");
3476 samples = LLVMBuildAnd(ctx->builder, samples,
3477 LLVMConstInt(ctx->i32, 0xf, false), "");
3478 samples = LLVMBuildShl(ctx->builder, ctx->i32one,
3479 samples, "");
3480 samples = LLVMBuildSelect(ctx->builder, is_msaa, samples,
3481 ctx->i32one, "");
3482 result = samples;
3483 goto write_result;
3484 }
3485
3486 if (coord)
3487 for (chan = 0; chan < instr->coord_components; chan++)
3488 coords[chan] = llvm_extract_elem(ctx, coord, chan);
3489
3490 if (offsets && instr->op != nir_texop_txf) {
3491 LLVMValueRef offset[3], pack;
3492 for (chan = 0; chan < 3; ++chan)
3493 offset[chan] = ctx->i32zero;
3494
3495 tinfo.has_offset = true;
3496 for (chan = 0; chan < get_llvm_num_components(offsets); chan++) {
3497 offset[chan] = llvm_extract_elem(ctx, offsets, chan);
3498 offset[chan] = LLVMBuildAnd(ctx->builder, offset[chan],
3499 LLVMConstInt(ctx->i32, 0x3f, false), "");
3500 if (chan)
3501 offset[chan] = LLVMBuildShl(ctx->builder, offset[chan],
3502 LLVMConstInt(ctx->i32, chan * 8, false), "");
3503 }
3504 pack = LLVMBuildOr(ctx->builder, offset[0], offset[1], "");
3505 pack = LLVMBuildOr(ctx->builder, pack, offset[2], "");
3506 address[count++] = pack;
3507
3508 }
3509 /* pack LOD bias value */
3510 if (instr->op == nir_texop_txb && bias) {
3511 address[count++] = bias;
3512 }
3513
3514 /* Pack depth comparison value */
3515 if (instr->is_shadow && comparator) {
3516 address[count++] = llvm_extract_elem(ctx, comparator, 0);
3517 }
3518
3519 /* pack derivatives */
3520 if (ddx || ddy) {
3521 switch (instr->sampler_dim) {
3522 case GLSL_SAMPLER_DIM_3D:
3523 case GLSL_SAMPLER_DIM_CUBE:
3524 num_deriv_comp = 3;
3525 break;
3526 case GLSL_SAMPLER_DIM_2D:
3527 default:
3528 num_deriv_comp = 2;
3529 break;
3530 case GLSL_SAMPLER_DIM_1D:
3531 num_deriv_comp = 1;
3532 break;
3533 }
3534
3535 for (unsigned i = 0; i < num_deriv_comp; i++) {
3536 derivs[i * 2] = to_float(ctx, llvm_extract_elem(ctx, ddx, i));
3537 derivs[i * 2 + 1] = to_float(ctx, llvm_extract_elem(ctx, ddy, i));
3538 }
3539 }
3540
3541 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
3542 for (chan = 0; chan < instr->coord_components; chan++)
3543 coords[chan] = to_float(ctx, coords[chan]);
3544 if (instr->coord_components == 3)
3545 coords[3] = LLVMGetUndef(ctx->f32);
3546 ac_prepare_cube_coords(&ctx->ac,
3547 instr->op == nir_texop_txd, instr->is_array,
3548 coords, derivs);
3549 if (num_deriv_comp)
3550 num_deriv_comp--;
3551 }
3552
3553 if (ddx || ddy) {
3554 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
3555 address[count++] = derivs[i];
3556 }
3557
3558 /* Pack texture coordinates */
3559 if (coord) {
3560 address[count++] = coords[0];
3561 if (instr->coord_components > 1)
3562 address[count++] = coords[1];
3563 if (instr->coord_components > 2) {
3564 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
3565 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D && instr->op != nir_texop_txf) {
3566 coords[2] = to_float(ctx, coords[2]);
3567 coords[2] = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32, &coords[2],
3568 1, 0);
3569 coords[2] = to_integer(ctx, coords[2]);
3570 }
3571 address[count++] = coords[2];
3572 }
3573 }
3574
3575 /* Pack LOD */
3576 if ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) && lod) {
3577 address[count++] = lod;
3578 } else if (instr->op == nir_texop_txf_ms && sample_index) {
3579 address[count++] = sample_index;
3580 } else if(instr->op == nir_texop_txs) {
3581 count = 0;
3582 if (lod)
3583 address[count++] = lod;
3584 else
3585 address[count++] = ctx->i32zero;
3586 }
3587
3588 for (chan = 0; chan < count; chan++) {
3589 address[chan] = LLVMBuildBitCast(ctx->builder,
3590 address[chan], ctx->i32, "");
3591 }
3592
3593 if (instr->op == nir_texop_samples_identical) {
3594 LLVMValueRef txf_address[4];
3595 struct ac_tex_info txf_info = { 0 };
3596 unsigned txf_count = count;
3597 memcpy(txf_address, address, sizeof(txf_address));
3598
3599 if (!instr->is_array)
3600 txf_address[2] = ctx->i32zero;
3601 txf_address[3] = ctx->i32zero;
3602
3603 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3604 fmask_ptr, NULL,
3605 txf_address, txf_count, 0xf);
3606
3607 result = build_tex_intrinsic(ctx, instr, &txf_info);
3608
3609 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3610 result = emit_int_cmp(ctx, LLVMIntEQ, result, ctx->i32zero);
3611 goto write_result;
3612 }
3613
3614 /* Adjust the sample index according to FMASK.
3615 *
3616 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3617 * which is the identity mapping. Each nibble says which physical sample
3618 * should be fetched to get that sample.
3619 *
3620 * For example, 0x11111100 means there are only 2 samples stored and
3621 * the second sample covers 3/4 of the pixel. When reading samples 0
3622 * and 1, return physical sample 0 (determined by the first two 0s
3623 * in FMASK), otherwise return physical sample 1.
3624 *
3625 * The sample index should be adjusted as follows:
3626 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3627 */
3628 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS) {
3629 LLVMValueRef txf_address[4];
3630 struct ac_tex_info txf_info = { 0 };
3631 unsigned txf_count = count;
3632 memcpy(txf_address, address, sizeof(txf_address));
3633
3634 if (!instr->is_array)
3635 txf_address[2] = ctx->i32zero;
3636 txf_address[3] = ctx->i32zero;
3637
3638 set_tex_fetch_args(ctx, &txf_info, instr, nir_texop_txf,
3639 fmask_ptr, NULL,
3640 txf_address, txf_count, 0xf);
3641
3642 result = build_tex_intrinsic(ctx, instr, &txf_info);
3643 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3644 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3645
3646 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3647 result,
3648 ctx->i32zero, "");
3649
3650 unsigned sample_chan = instr->is_array ? 3 : 2;
3651
3652 LLVMValueRef sample_index4 =
3653 LLVMBuildMul(ctx->builder, address[sample_chan], four, "");
3654 LLVMValueRef shifted_fmask =
3655 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3656 LLVMValueRef final_sample =
3657 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3658
3659 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3660 * resource descriptor is 0 (invalid),
3661 */
3662 LLVMValueRef fmask_desc =
3663 LLVMBuildBitCast(ctx->builder, fmask_ptr,
3664 ctx->v8i32, "");
3665
3666 LLVMValueRef fmask_word1 =
3667 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3668 ctx->i32one, "");
3669
3670 LLVMValueRef word1_is_nonzero =
3671 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3672 fmask_word1, ctx->i32zero, "");
3673
3674 /* Replace the MSAA sample index. */
3675 address[sample_chan] =
3676 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3677 final_sample, address[sample_chan], "");
3678 }
3679
3680 if (offsets && instr->op == nir_texop_txf) {
3681 nir_const_value *const_offset =
3682 nir_src_as_const_value(instr->src[const_src].src);
3683 int num_offsets = instr->src[const_src].src.ssa->num_components;
3684 assert(const_offset);
3685 num_offsets = MIN2(num_offsets, instr->coord_components);
3686 if (num_offsets > 2)
3687 address[2] = LLVMBuildAdd(ctx->builder,
3688 address[2], LLVMConstInt(ctx->i32, const_offset->i32[2], false), "");
3689 if (num_offsets > 1)
3690 address[1] = LLVMBuildAdd(ctx->builder,
3691 address[1], LLVMConstInt(ctx->i32, const_offset->i32[1], false), "");
3692 address[0] = LLVMBuildAdd(ctx->builder,
3693 address[0], LLVMConstInt(ctx->i32, const_offset->i32[0], false), "");
3694
3695 }
3696
3697 /* TODO TG4 support */
3698 if (instr->op == nir_texop_tg4) {
3699 if (instr->is_shadow)
3700 dmask = 1;
3701 else
3702 dmask = 1 << instr->component;
3703 }
3704 set_tex_fetch_args(ctx, &tinfo, instr, instr->op,
3705 res_ptr, samp_ptr, address, count, dmask);
3706
3707 result = build_tex_intrinsic(ctx, instr, &tinfo);
3708
3709 if (instr->op == nir_texop_query_levels)
3710 result = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, 3, false), "");
3711 else if (instr->is_shadow && instr->op != nir_texop_txs && instr->op != nir_texop_lod && instr->op != nir_texop_tg4)
3712 result = LLVMBuildExtractElement(ctx->builder, result, ctx->i32zero, "");
3713 else if (instr->op == nir_texop_txs &&
3714 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
3715 instr->is_array) {
3716 LLVMValueRef two = LLVMConstInt(ctx->i32, 2, false);
3717 LLVMValueRef six = LLVMConstInt(ctx->i32, 6, false);
3718 LLVMValueRef z = LLVMBuildExtractElement(ctx->builder, result, two, "");
3719 z = LLVMBuildSDiv(ctx->builder, z, six, "");
3720 result = LLVMBuildInsertElement(ctx->builder, result, z, two, "");
3721 } else if (instr->dest.ssa.num_components != 4)
3722 result = trim_vector(ctx, result, instr->dest.ssa.num_components);
3723
3724 write_result:
3725 if (result) {
3726 assert(instr->dest.is_ssa);
3727 result = to_integer(ctx, result);
3728 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3729 }
3730 }
3731
3732
3733 static void visit_phi(struct nir_to_llvm_context *ctx, nir_phi_instr *instr)
3734 {
3735 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
3736 LLVMValueRef result = LLVMBuildPhi(ctx->builder, type, "");
3737
3738 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
3739 _mesa_hash_table_insert(ctx->phis, instr, result);
3740 }
3741
3742 static void visit_post_phi(struct nir_to_llvm_context *ctx,
3743 nir_phi_instr *instr,
3744 LLVMValueRef llvm_phi)
3745 {
3746 nir_foreach_phi_src(src, instr) {
3747 LLVMBasicBlockRef block = get_block(ctx, src->pred);
3748 LLVMValueRef llvm_src = get_src(ctx, src->src);
3749
3750 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
3751 }
3752 }
3753
3754 static void phi_post_pass(struct nir_to_llvm_context *ctx)
3755 {
3756 struct hash_entry *entry;
3757 hash_table_foreach(ctx->phis, entry) {
3758 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
3759 (LLVMValueRef)entry->data);
3760 }
3761 }
3762
3763
3764 static void visit_ssa_undef(struct nir_to_llvm_context *ctx,
3765 nir_ssa_undef_instr *instr)
3766 {
3767 unsigned num_components = instr->def.num_components;
3768 LLVMValueRef undef;
3769
3770 if (num_components == 1)
3771 undef = LLVMGetUndef(ctx->i32);
3772 else {
3773 undef = LLVMGetUndef(LLVMVectorType(ctx->i32, num_components));
3774 }
3775 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
3776 }
3777
3778 static void visit_jump(struct nir_to_llvm_context *ctx,
3779 nir_jump_instr *instr)
3780 {
3781 switch (instr->type) {
3782 case nir_jump_break:
3783 LLVMBuildBr(ctx->builder, ctx->break_block);
3784 LLVMClearInsertionPosition(ctx->builder);
3785 break;
3786 case nir_jump_continue:
3787 LLVMBuildBr(ctx->builder, ctx->continue_block);
3788 LLVMClearInsertionPosition(ctx->builder);
3789 break;
3790 default:
3791 fprintf(stderr, "Unknown NIR jump instr: ");
3792 nir_print_instr(&instr->instr, stderr);
3793 fprintf(stderr, "\n");
3794 abort();
3795 }
3796 }
3797
3798 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3799 struct exec_list *list);
3800
3801 static void visit_block(struct nir_to_llvm_context *ctx, nir_block *block)
3802 {
3803 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->builder);
3804 nir_foreach_instr(instr, block)
3805 {
3806 switch (instr->type) {
3807 case nir_instr_type_alu:
3808 visit_alu(ctx, nir_instr_as_alu(instr));
3809 break;
3810 case nir_instr_type_load_const:
3811 visit_load_const(ctx, nir_instr_as_load_const(instr));
3812 break;
3813 case nir_instr_type_intrinsic:
3814 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
3815 break;
3816 case nir_instr_type_tex:
3817 visit_tex(ctx, nir_instr_as_tex(instr));
3818 break;
3819 case nir_instr_type_phi:
3820 visit_phi(ctx, nir_instr_as_phi(instr));
3821 break;
3822 case nir_instr_type_ssa_undef:
3823 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
3824 break;
3825 case nir_instr_type_jump:
3826 visit_jump(ctx, nir_instr_as_jump(instr));
3827 break;
3828 default:
3829 fprintf(stderr, "Unknown NIR instr type: ");
3830 nir_print_instr(instr, stderr);
3831 fprintf(stderr, "\n");
3832 abort();
3833 }
3834 }
3835
3836 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
3837 }
3838
3839 static void visit_if(struct nir_to_llvm_context *ctx, nir_if *if_stmt)
3840 {
3841 LLVMValueRef value = get_src(ctx, if_stmt->condition);
3842
3843 LLVMBasicBlockRef merge_block =
3844 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3845 LLVMBasicBlockRef if_block =
3846 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3847 LLVMBasicBlockRef else_block = merge_block;
3848 if (!exec_list_is_empty(&if_stmt->else_list))
3849 else_block = LLVMAppendBasicBlockInContext(
3850 ctx->context, ctx->main_function, "");
3851
3852 LLVMValueRef cond = LLVMBuildICmp(ctx->builder, LLVMIntNE, value,
3853 LLVMConstInt(ctx->i32, 0, false), "");
3854 LLVMBuildCondBr(ctx->builder, cond, if_block, else_block);
3855
3856 LLVMPositionBuilderAtEnd(ctx->builder, if_block);
3857 visit_cf_list(ctx, &if_stmt->then_list);
3858 if (LLVMGetInsertBlock(ctx->builder))
3859 LLVMBuildBr(ctx->builder, merge_block);
3860
3861 if (!exec_list_is_empty(&if_stmt->else_list)) {
3862 LLVMPositionBuilderAtEnd(ctx->builder, else_block);
3863 visit_cf_list(ctx, &if_stmt->else_list);
3864 if (LLVMGetInsertBlock(ctx->builder))
3865 LLVMBuildBr(ctx->builder, merge_block);
3866 }
3867
3868 LLVMPositionBuilderAtEnd(ctx->builder, merge_block);
3869 }
3870
3871 static void visit_loop(struct nir_to_llvm_context *ctx, nir_loop *loop)
3872 {
3873 LLVMBasicBlockRef continue_parent = ctx->continue_block;
3874 LLVMBasicBlockRef break_parent = ctx->break_block;
3875
3876 ctx->continue_block =
3877 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3878 ctx->break_block =
3879 LLVMAppendBasicBlockInContext(ctx->context, ctx->main_function, "");
3880
3881 LLVMBuildBr(ctx->builder, ctx->continue_block);
3882 LLVMPositionBuilderAtEnd(ctx->builder, ctx->continue_block);
3883 visit_cf_list(ctx, &loop->body);
3884
3885 if (LLVMGetInsertBlock(ctx->builder))
3886 LLVMBuildBr(ctx->builder, ctx->continue_block);
3887 LLVMPositionBuilderAtEnd(ctx->builder, ctx->break_block);
3888
3889 ctx->continue_block = continue_parent;
3890 ctx->break_block = break_parent;
3891 }
3892
3893 static void visit_cf_list(struct nir_to_llvm_context *ctx,
3894 struct exec_list *list)
3895 {
3896 foreach_list_typed(nir_cf_node, node, node, list)
3897 {
3898 switch (node->type) {
3899 case nir_cf_node_block:
3900 visit_block(ctx, nir_cf_node_as_block(node));
3901 break;
3902
3903 case nir_cf_node_if:
3904 visit_if(ctx, nir_cf_node_as_if(node));
3905 break;
3906
3907 case nir_cf_node_loop:
3908 visit_loop(ctx, nir_cf_node_as_loop(node));
3909 break;
3910
3911 default:
3912 assert(0);
3913 }
3914 }
3915 }
3916
3917 static void
3918 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
3919 struct nir_variable *variable)
3920 {
3921 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
3922 LLVMValueRef t_offset;
3923 LLVMValueRef t_list;
3924 LLVMValueRef args[3];
3925 LLVMValueRef input;
3926 LLVMValueRef buffer_index;
3927 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
3928 int idx = variable->data.location;
3929 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
3930
3931 variable->data.driver_location = idx * 4;
3932
3933 if (ctx->options->key.vs.instance_rate_inputs & (1u << index)) {
3934 buffer_index = LLVMBuildAdd(ctx->builder, ctx->instance_id,
3935 ctx->start_instance, "");
3936 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(3,
3937 ctx->shader_info->vs.vgpr_comp_cnt);
3938 } else
3939 buffer_index = LLVMBuildAdd(ctx->builder, ctx->vertex_id,
3940 ctx->base_vertex, "");
3941
3942 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
3943 t_offset = LLVMConstInt(ctx->i32, index + i, false);
3944
3945 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
3946 args[0] = t_list;
3947 args[1] = LLVMConstInt(ctx->i32, 0, false);
3948 args[2] = buffer_index;
3949 input = ac_emit_llvm_intrinsic(&ctx->ac,
3950 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
3951 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3952
3953 for (unsigned chan = 0; chan < 4; chan++) {
3954 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3955 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
3956 to_integer(ctx, LLVMBuildExtractElement(ctx->builder,
3957 input, llvm_chan, ""));
3958 }
3959 }
3960 }
3961
3962
3963 static void interp_fs_input(struct nir_to_llvm_context *ctx,
3964 unsigned attr,
3965 LLVMValueRef interp_param,
3966 LLVMValueRef prim_mask,
3967 LLVMValueRef result[4])
3968 {
3969 const char *intr_name;
3970 LLVMValueRef attr_number;
3971 unsigned chan;
3972
3973 attr_number = LLVMConstInt(ctx->i32, attr, false);
3974
3975 /* fs.constant returns the param from the middle vertex, so it's not
3976 * really useful for flat shading. It's meant to be used for custom
3977 * interpolation (but the intrinsic can't fetch from the other two
3978 * vertices).
3979 *
3980 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
3981 * to do the right thing. The only reason we use fs.constant is that
3982 * fs.interp cannot be used on integers, because they can be equal
3983 * to NaN.
3984 */
3985 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3986
3987 for (chan = 0; chan < 4; chan++) {
3988 LLVMValueRef args[4];
3989 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, false);
3990
3991 args[0] = llvm_chan;
3992 args[1] = attr_number;
3993 args[2] = prim_mask;
3994 args[3] = interp_param;
3995 result[chan] = ac_emit_llvm_intrinsic(&ctx->ac, intr_name,
3996 ctx->f32, args, args[3] ? 4 : 3,
3997 AC_FUNC_ATTR_READNONE | AC_FUNC_ATTR_NOUNWIND);
3998 }
3999 }
4000
4001 static void
4002 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
4003 struct nir_variable *variable)
4004 {
4005 int idx = variable->data.location;
4006 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4007 LLVMValueRef interp;
4008
4009 variable->data.driver_location = idx * 4;
4010 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
4011
4012 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
4013 unsigned interp_type;
4014 if (variable->data.sample) {
4015 interp_type = INTERP_SAMPLE;
4016 ctx->shader_info->fs.force_persample = true;
4017 } else if (variable->data.centroid)
4018 interp_type = INTERP_CENTROID;
4019 else
4020 interp_type = INTERP_CENTER;
4021
4022 interp = lookup_interp_param(ctx, variable->data.interpolation, interp_type);
4023 } else
4024 interp = NULL;
4025
4026 for (unsigned i = 0; i < attrib_count; ++i)
4027 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
4028
4029 }
4030
4031 static void
4032 handle_shader_input_decl(struct nir_to_llvm_context *ctx,
4033 struct nir_variable *variable)
4034 {
4035 switch (ctx->stage) {
4036 case MESA_SHADER_VERTEX:
4037 handle_vs_input_decl(ctx, variable);
4038 break;
4039 case MESA_SHADER_FRAGMENT:
4040 handle_fs_input_decl(ctx, variable);
4041 break;
4042 default:
4043 break;
4044 }
4045
4046 }
4047
4048 static void
4049 handle_fs_inputs_pre(struct nir_to_llvm_context *ctx,
4050 struct nir_shader *nir)
4051 {
4052 unsigned index = 0;
4053 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
4054 LLVMValueRef interp_param;
4055 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
4056
4057 if (!(ctx->input_mask & (1ull << i)))
4058 continue;
4059
4060 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC) {
4061 interp_param = *inputs;
4062 interp_fs_input(ctx, index, interp_param, ctx->prim_mask,
4063 inputs);
4064
4065 if (!interp_param)
4066 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
4067 ++index;
4068 } else if (i == VARYING_SLOT_POS) {
4069 for(int i = 0; i < 3; ++i)
4070 inputs[i] = ctx->frag_pos[i];
4071
4072 inputs[3] = ac_emit_fdiv(&ctx->ac, ctx->f32one, ctx->frag_pos[3]);
4073 }
4074 }
4075 ctx->shader_info->fs.num_interp = index;
4076 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
4077 ctx->shader_info->fs.has_pcoord = true;
4078 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
4079 }
4080
4081 static LLVMValueRef
4082 ac_build_alloca(struct nir_to_llvm_context *ctx,
4083 LLVMTypeRef type,
4084 const char *name)
4085 {
4086 LLVMBuilderRef builder = ctx->builder;
4087 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
4088 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
4089 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
4090 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
4091 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ctx->context);
4092 LLVMValueRef res;
4093
4094 if (first_instr) {
4095 LLVMPositionBuilderBefore(first_builder, first_instr);
4096 } else {
4097 LLVMPositionBuilderAtEnd(first_builder, first_block);
4098 }
4099
4100 res = LLVMBuildAlloca(first_builder, type, name);
4101 LLVMBuildStore(builder, LLVMConstNull(type), res);
4102
4103 LLVMDisposeBuilder(first_builder);
4104
4105 return res;
4106 }
4107
4108 static LLVMValueRef si_build_alloca_undef(struct nir_to_llvm_context *ctx,
4109 LLVMTypeRef type,
4110 const char *name)
4111 {
4112 LLVMValueRef ptr = ac_build_alloca(ctx, type, name);
4113 LLVMBuildStore(ctx->builder, LLVMGetUndef(type), ptr);
4114 return ptr;
4115 }
4116
4117 static void
4118 handle_shader_output_decl(struct nir_to_llvm_context *ctx,
4119 struct nir_variable *variable)
4120 {
4121 int idx = variable->data.location + variable->data.index;
4122 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4123
4124 variable->data.driver_location = idx * 4;
4125
4126 if (ctx->stage == MESA_SHADER_VERTEX) {
4127
4128 if (idx == VARYING_SLOT_CLIP_DIST0 ||
4129 idx == VARYING_SLOT_CULL_DIST0) {
4130 int length = glsl_get_length(variable->type);
4131 if (idx == VARYING_SLOT_CLIP_DIST0) {
4132 ctx->shader_info->vs.clip_dist_mask = (1 << length) - 1;
4133 ctx->num_clips = length;
4134 } else if (idx == VARYING_SLOT_CULL_DIST0) {
4135 ctx->shader_info->vs.cull_dist_mask = (1 << length) - 1;
4136 ctx->num_culls = length;
4137 }
4138 if (length > 4)
4139 attrib_count = 2;
4140 else
4141 attrib_count = 1;
4142 }
4143 }
4144
4145 for (unsigned i = 0; i < attrib_count; ++i) {
4146 for (unsigned chan = 0; chan < 4; chan++) {
4147 ctx->outputs[radeon_llvm_reg_index_soa(idx + i, chan)] =
4148 si_build_alloca_undef(ctx, ctx->f32, "");
4149 }
4150 }
4151 ctx->output_mask |= ((1ull << attrib_count) - 1) << idx;
4152 }
4153
4154 static void
4155 setup_locals(struct nir_to_llvm_context *ctx,
4156 struct nir_function *func)
4157 {
4158 int i, j;
4159 ctx->num_locals = 0;
4160 nir_foreach_variable(variable, &func->impl->locals) {
4161 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
4162 variable->data.driver_location = ctx->num_locals * 4;
4163 ctx->num_locals += attrib_count;
4164 }
4165 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
4166 if (!ctx->locals)
4167 return;
4168
4169 for (i = 0; i < ctx->num_locals; i++) {
4170 for (j = 0; j < 4; j++) {
4171 ctx->locals[i * 4 + j] =
4172 si_build_alloca_undef(ctx, ctx->f32, "temp");
4173 }
4174 }
4175 }
4176
4177 static LLVMValueRef
4178 emit_float_saturate(struct nir_to_llvm_context *ctx, LLVMValueRef v, float lo, float hi)
4179 {
4180 v = to_float(ctx, v);
4181 v = emit_intrin_2f_param(ctx, "llvm.maxnum.f32", v, LLVMConstReal(ctx->f32, lo));
4182 return emit_intrin_2f_param(ctx, "llvm.minnum.f32", v, LLVMConstReal(ctx->f32, hi));
4183 }
4184
4185
4186 static LLVMValueRef emit_pack_int16(struct nir_to_llvm_context *ctx,
4187 LLVMValueRef src0, LLVMValueRef src1)
4188 {
4189 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
4190 LLVMValueRef comp[2];
4191
4192 comp[0] = LLVMBuildAnd(ctx->builder, src0, LLVMConstInt(ctx-> i32, 65535, 0), "");
4193 comp[1] = LLVMBuildAnd(ctx->builder, src1, LLVMConstInt(ctx-> i32, 65535, 0), "");
4194 comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
4195 return LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
4196 }
4197
4198 /* Initialize arguments for the shader export intrinsic */
4199 static void
4200 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
4201 LLVMValueRef *values,
4202 unsigned target,
4203 LLVMValueRef *args)
4204 {
4205 /* Default is 0xf. Adjusted below depending on the format. */
4206 args[0] = LLVMConstInt(ctx->i32, target != V_008DFC_SQ_EXP_NULL ? 0xf : 0, false);
4207 /* Specify whether the EXEC mask represents the valid mask */
4208 args[1] = LLVMConstInt(ctx->i32, 0, false);
4209
4210 /* Specify whether this is the last export */
4211 args[2] = LLVMConstInt(ctx->i32, 0, false);
4212 /* Specify the target we are exporting */
4213 args[3] = LLVMConstInt(ctx->i32, target, false);
4214
4215 args[4] = LLVMConstInt(ctx->i32, 0, false); /* COMPR flag */
4216 args[5] = LLVMGetUndef(ctx->f32);
4217 args[6] = LLVMGetUndef(ctx->f32);
4218 args[7] = LLVMGetUndef(ctx->f32);
4219 args[8] = LLVMGetUndef(ctx->f32);
4220
4221 if (!values)
4222 return;
4223
4224 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
4225 LLVMValueRef val[4];
4226 unsigned index = target - V_008DFC_SQ_EXP_MRT;
4227 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
4228 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
4229
4230 switch(col_format) {
4231 case V_028714_SPI_SHADER_ZERO:
4232 args[0] = LLVMConstInt(ctx->i32, 0x0, 0);
4233 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_NULL, 0);
4234 break;
4235
4236 case V_028714_SPI_SHADER_32_R:
4237 args[0] = LLVMConstInt(ctx->i32, 0x1, 0);
4238 args[5] = values[0];
4239 break;
4240
4241 case V_028714_SPI_SHADER_32_GR:
4242 args[0] = LLVMConstInt(ctx->i32, 0x3, 0);
4243 args[5] = values[0];
4244 args[6] = values[1];
4245 break;
4246
4247 case V_028714_SPI_SHADER_32_AR:
4248 args[0] = LLVMConstInt(ctx->i32, 0x9, 0);
4249 args[5] = values[0];
4250 args[8] = values[3];
4251 break;
4252
4253 case V_028714_SPI_SHADER_FP16_ABGR:
4254 args[4] = ctx->i32one;
4255
4256 for (unsigned chan = 0; chan < 2; chan++) {
4257 LLVMValueRef pack_args[2] = {
4258 values[2 * chan],
4259 values[2 * chan + 1]
4260 };
4261 LLVMValueRef packed;
4262
4263 packed = ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.packf16",
4264 ctx->i32, pack_args, 2,
4265 AC_FUNC_ATTR_READNONE);
4266 args[chan + 5] = packed;
4267 }
4268 break;
4269
4270 case V_028714_SPI_SHADER_UNORM16_ABGR:
4271 for (unsigned chan = 0; chan < 4; chan++) {
4272 val[chan] = emit_float_saturate(ctx, values[chan], 0, 1);
4273 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4274 LLVMConstReal(ctx->f32, 65535), "");
4275 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4276 LLVMConstReal(ctx->f32, 0.5), "");
4277 val[chan] = LLVMBuildFPToUI(ctx->builder, val[chan],
4278 ctx->i32, "");
4279 }
4280
4281 args[4] = ctx->i32one;
4282 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4283 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4284 break;
4285
4286 case V_028714_SPI_SHADER_SNORM16_ABGR:
4287 for (unsigned chan = 0; chan < 4; chan++) {
4288 val[chan] = emit_float_saturate(ctx, values[chan], -1, 1);
4289 val[chan] = LLVMBuildFMul(ctx->builder, val[chan],
4290 LLVMConstReal(ctx->f32, 32767), "");
4291
4292 /* If positive, add 0.5, else add -0.5. */
4293 val[chan] = LLVMBuildFAdd(ctx->builder, val[chan],
4294 LLVMBuildSelect(ctx->builder,
4295 LLVMBuildFCmp(ctx->builder, LLVMRealOGE,
4296 val[chan], ctx->f32zero, ""),
4297 LLVMConstReal(ctx->f32, 0.5),
4298 LLVMConstReal(ctx->f32, -0.5), ""), "");
4299 val[chan] = LLVMBuildFPToSI(ctx->builder, val[chan], ctx->i32, "");
4300 }
4301
4302 args[4] = ctx->i32one;
4303 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4304 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4305 break;
4306
4307 case V_028714_SPI_SHADER_UINT16_ABGR: {
4308 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 255 : 65535, 0);
4309
4310 for (unsigned chan = 0; chan < 4; chan++) {
4311 val[chan] = to_integer(ctx, values[chan]);
4312 val[chan] = emit_minmax_int(ctx, LLVMIntULT, val[chan], max);
4313 }
4314
4315 args[4] = ctx->i32one;
4316 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4317 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4318 break;
4319 }
4320
4321 case V_028714_SPI_SHADER_SINT16_ABGR: {
4322 LLVMValueRef max = LLVMConstInt(ctx->i32, is_int8 ? 127 : 32767, 0);
4323 LLVMValueRef min = LLVMConstInt(ctx->i32, is_int8 ? -128 : -32768, 0);
4324
4325 /* Clamp. */
4326 for (unsigned chan = 0; chan < 4; chan++) {
4327 val[chan] = to_integer(ctx, values[chan]);
4328 val[chan] = emit_minmax_int(ctx, LLVMIntSLT, val[chan], max);
4329 val[chan] = emit_minmax_int(ctx, LLVMIntSGT, val[chan], min);
4330 }
4331
4332 args[4] = ctx->i32one;
4333 args[5] = emit_pack_int16(ctx, val[0], val[1]);
4334 args[6] = emit_pack_int16(ctx, val[2], val[3]);
4335 break;
4336 }
4337
4338 default:
4339 case V_028714_SPI_SHADER_32_ABGR:
4340 memcpy(&args[5], values, sizeof(values[0]) * 4);
4341 break;
4342 }
4343 } else
4344 memcpy(&args[5], values, sizeof(values[0]) * 4);
4345
4346 for (unsigned i = 5; i < 9; ++i)
4347 args[i] = to_float(ctx, args[i]);
4348 }
4349
4350 static void
4351 handle_vs_outputs_post(struct nir_to_llvm_context *ctx)
4352 {
4353 uint32_t param_count = 0;
4354 unsigned target;
4355 unsigned pos_idx, num_pos_exports = 0;
4356 LLVMValueRef args[9];
4357 LLVMValueRef pos_args[4][9] = { { 0 } };
4358 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
4359 int i;
4360 const uint64_t clip_mask = ctx->output_mask & ((1ull << VARYING_SLOT_CLIP_DIST0) |
4361 (1ull << VARYING_SLOT_CLIP_DIST1) |
4362 (1ull << VARYING_SLOT_CULL_DIST0) |
4363 (1ull << VARYING_SLOT_CULL_DIST1));
4364
4365 if (clip_mask) {
4366 LLVMValueRef slots[8];
4367 unsigned j;
4368
4369 if (ctx->shader_info->vs.cull_dist_mask)
4370 ctx->shader_info->vs.cull_dist_mask <<= ctx->num_clips;
4371
4372 i = VARYING_SLOT_CLIP_DIST0;
4373 for (j = 0; j < ctx->num_clips; j++)
4374 slots[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4375 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4376 i = VARYING_SLOT_CULL_DIST0;
4377 for (j = 0; j < ctx->num_culls; j++)
4378 slots[ctx->num_clips + j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4379 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4380
4381 for (i = ctx->num_clips + ctx->num_culls; i < 8; i++)
4382 slots[i] = LLVMGetUndef(ctx->f32);
4383
4384 if (ctx->num_clips + ctx->num_culls > 4) {
4385 target = V_008DFC_SQ_EXP_POS + 3;
4386 si_llvm_init_export_args(ctx, &slots[4], target, args);
4387 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4388 args, sizeof(args));
4389 }
4390
4391 target = V_008DFC_SQ_EXP_POS + 2;
4392 si_llvm_init_export_args(ctx, &slots[0], target, args);
4393 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4394 args, sizeof(args));
4395
4396 }
4397
4398 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4399 LLVMValueRef values[4];
4400 if (!(ctx->output_mask & (1ull << i)))
4401 continue;
4402
4403 for (unsigned j = 0; j < 4; j++)
4404 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4405 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4406
4407 if (i == VARYING_SLOT_POS) {
4408 target = V_008DFC_SQ_EXP_POS;
4409 } else if (i == VARYING_SLOT_CLIP_DIST0 ||
4410 i == VARYING_SLOT_CLIP_DIST1 ||
4411 i == VARYING_SLOT_CULL_DIST0 ||
4412 i == VARYING_SLOT_CULL_DIST1) {
4413 continue;
4414 } else if (i == VARYING_SLOT_PSIZ) {
4415 ctx->shader_info->vs.writes_pointsize = true;
4416 psize_value = values[0];
4417 continue;
4418 } else if (i == VARYING_SLOT_LAYER) {
4419 ctx->shader_info->vs.writes_layer = true;
4420 layer_value = values[0];
4421 continue;
4422 } else if (i == VARYING_SLOT_VIEWPORT) {
4423 ctx->shader_info->vs.writes_viewport_index = true;
4424 viewport_index_value = values[0];
4425 continue;
4426 } else if (i >= VARYING_SLOT_VAR0) {
4427 ctx->shader_info->vs.export_mask |= 1u << (i - VARYING_SLOT_VAR0);
4428 target = V_008DFC_SQ_EXP_PARAM + param_count;
4429 param_count++;
4430 }
4431
4432 si_llvm_init_export_args(ctx, values, target, args);
4433
4434 if (target >= V_008DFC_SQ_EXP_POS &&
4435 target <= (V_008DFC_SQ_EXP_POS + 3)) {
4436 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
4437 args, sizeof(args));
4438 } else {
4439 ac_emit_llvm_intrinsic(&ctx->ac,
4440 "llvm.SI.export",
4441 ctx->voidt,
4442 args, 9, 0);
4443 }
4444 }
4445
4446 /* We need to add the position output manually if it's missing. */
4447 if (!pos_args[0][0]) {
4448 pos_args[0][0] = LLVMConstInt(ctx->i32, 0xf, false);
4449 pos_args[0][1] = ctx->i32zero; /* EXEC mask */
4450 pos_args[0][2] = ctx->i32zero; /* last export? */
4451 pos_args[0][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS, false);
4452 pos_args[0][4] = ctx->i32zero; /* COMPR flag */
4453 pos_args[0][5] = ctx->f32zero; /* X */
4454 pos_args[0][6] = ctx->f32zero; /* Y */
4455 pos_args[0][7] = ctx->f32zero; /* Z */
4456 pos_args[0][8] = ctx->f32one; /* W */
4457 }
4458
4459 uint32_t mask = ((ctx->shader_info->vs.writes_pointsize == true ? 1 : 0) |
4460 (ctx->shader_info->vs.writes_layer == true ? 4 : 0) |
4461 (ctx->shader_info->vs.writes_viewport_index == true ? 8 : 0));
4462 if (mask) {
4463 pos_args[1][0] = LLVMConstInt(ctx->i32, mask, false); /* writemask */
4464 pos_args[1][1] = ctx->i32zero; /* EXEC mask */
4465 pos_args[1][2] = ctx->i32zero; /* last export? */
4466 pos_args[1][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + 1, false);
4467 pos_args[1][4] = ctx->i32zero; /* COMPR flag */
4468 pos_args[1][5] = ctx->f32zero; /* X */
4469 pos_args[1][6] = ctx->f32zero; /* Y */
4470 pos_args[1][7] = ctx->f32zero; /* Z */
4471 pos_args[1][8] = ctx->f32zero; /* W */
4472
4473 if (ctx->shader_info->vs.writes_pointsize == true)
4474 pos_args[1][5] = psize_value;
4475 if (ctx->shader_info->vs.writes_layer == true)
4476 pos_args[1][7] = layer_value;
4477 if (ctx->shader_info->vs.writes_viewport_index == true)
4478 pos_args[1][8] = viewport_index_value;
4479 }
4480 for (i = 0; i < 4; i++) {
4481 if (pos_args[i][0])
4482 num_pos_exports++;
4483 }
4484
4485 pos_idx = 0;
4486 for (i = 0; i < 4; i++) {
4487 if (!pos_args[i][0])
4488 continue;
4489
4490 /* Specify the target we are exporting */
4491 pos_args[i][3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_POS + pos_idx++, false);
4492 if (pos_idx == num_pos_exports)
4493 pos_args[i][2] = ctx->i32one;
4494 ac_emit_llvm_intrinsic(&ctx->ac,
4495 "llvm.SI.export",
4496 ctx->voidt,
4497 pos_args[i], 9, 0);
4498 }
4499
4500 ctx->shader_info->vs.pos_exports = num_pos_exports;
4501 ctx->shader_info->vs.param_exports = param_count;
4502 }
4503
4504 static void
4505 si_export_mrt_color(struct nir_to_llvm_context *ctx,
4506 LLVMValueRef *color, unsigned param, bool is_last)
4507 {
4508 LLVMValueRef args[9];
4509 /* Export */
4510 si_llvm_init_export_args(ctx, color, param,
4511 args);
4512
4513 if (is_last) {
4514 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4515 args[2] = ctx->i32one; /* DONE bit */
4516 } else if (args[0] == ctx->i32zero)
4517 return; /* unnecessary NULL export */
4518
4519 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4520 ctx->voidt, args, 9, 0);
4521 }
4522
4523 static void
4524 si_export_mrt_z(struct nir_to_llvm_context *ctx,
4525 LLVMValueRef depth, LLVMValueRef stencil,
4526 LLVMValueRef samplemask)
4527 {
4528 LLVMValueRef args[9];
4529 unsigned mask = 0;
4530 args[1] = ctx->i32one; /* whether the EXEC mask is valid */
4531 args[2] = ctx->i32one; /* DONE bit */
4532 /* Specify the target we are exporting */
4533 args[3] = LLVMConstInt(ctx->i32, V_008DFC_SQ_EXP_MRTZ, false);
4534
4535 args[4] = ctx->i32zero; /* COMP flag */
4536 args[5] = LLVMGetUndef(ctx->f32); /* R, depth */
4537 args[6] = LLVMGetUndef(ctx->f32); /* G, stencil test val[0:7], stencil op val[8:15] */
4538 args[7] = LLVMGetUndef(ctx->f32); /* B, sample mask */
4539 args[8] = LLVMGetUndef(ctx->f32); /* A, alpha to mask */
4540
4541 if (depth) {
4542 args[5] = depth;
4543 mask |= 0x1;
4544 }
4545
4546 if (stencil) {
4547 args[6] = stencil;
4548 mask |= 0x2;
4549 }
4550
4551 if (samplemask) {
4552 args[7] = samplemask;
4553 mask |= 0x04;
4554 }
4555
4556 /* SI (except OLAND) has a bug that it only looks
4557 * at the X writemask component. */
4558 if (ctx->options->chip_class == SI &&
4559 ctx->options->family != CHIP_OLAND)
4560 mask |= 0x01;
4561
4562 args[0] = LLVMConstInt(ctx->i32, mask, false);
4563 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.export",
4564 ctx->voidt, args, 9, 0);
4565 }
4566
4567 static void
4568 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
4569 {
4570 unsigned index = 0;
4571 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4572
4573 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4574 LLVMValueRef values[4];
4575
4576 if (!(ctx->output_mask & (1ull << i)))
4577 continue;
4578
4579 if (i == FRAG_RESULT_DEPTH) {
4580 ctx->shader_info->fs.writes_z = true;
4581 depth = to_float(ctx, LLVMBuildLoad(ctx->builder,
4582 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4583 } else if (i == FRAG_RESULT_STENCIL) {
4584 ctx->shader_info->fs.writes_stencil = true;
4585 stencil = to_float(ctx, LLVMBuildLoad(ctx->builder,
4586 ctx->outputs[radeon_llvm_reg_index_soa(i, 0)], ""));
4587 } else {
4588 bool last = false;
4589 for (unsigned j = 0; j < 4; j++)
4590 values[j] = to_float(ctx, LLVMBuildLoad(ctx->builder,
4591 ctx->outputs[radeon_llvm_reg_index_soa(i, j)], ""));
4592
4593 if (!ctx->shader_info->fs.writes_z && !ctx->shader_info->fs.writes_stencil)
4594 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
4595
4596 si_export_mrt_color(ctx, values, V_008DFC_SQ_EXP_MRT + index, last);
4597 index++;
4598 }
4599 }
4600
4601 if (depth || stencil)
4602 si_export_mrt_z(ctx, depth, stencil, samplemask);
4603 else if (!index)
4604 si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true);
4605
4606 ctx->shader_info->fs.output_mask = index ? ((1ull << index) - 1) : 0;
4607 }
4608
4609 static void
4610 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
4611 {
4612 LLVMValueRef args[2];
4613
4614 args[0] = LLVMConstInt(ctx->i32, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE, false);
4615 args[1] = ctx->gs_wave_id;
4616 ac_emit_llvm_intrinsic(&ctx->ac, "llvm.SI.sendmsg",
4617 ctx->voidt, args, 2, 0);
4618 }
4619
4620 static void
4621 handle_shader_outputs_post(struct nir_to_llvm_context *ctx)
4622 {
4623 switch (ctx->stage) {
4624 case MESA_SHADER_VERTEX:
4625 handle_vs_outputs_post(ctx);
4626 break;
4627 case MESA_SHADER_FRAGMENT:
4628 handle_fs_outputs_post(ctx);
4629 break;
4630 case MESA_SHADER_GEOMETRY:
4631 emit_gs_epilogue(ctx);
4632 break;
4633 default:
4634 break;
4635 }
4636 }
4637
4638 static void
4639 handle_shared_compute_var(struct nir_to_llvm_context *ctx,
4640 struct nir_variable *variable, uint32_t *offset, int idx)
4641 {
4642 unsigned size = glsl_count_attribute_slots(variable->type, false);
4643 variable->data.driver_location = *offset;
4644 *offset += size;
4645 }
4646
4647 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
4648 {
4649 LLVMPassManagerRef passmgr;
4650 /* Create the pass manager */
4651 passmgr = LLVMCreateFunctionPassManagerForModule(
4652 ctx->module);
4653
4654 /* This pass should eliminate all the load and store instructions */
4655 LLVMAddPromoteMemoryToRegisterPass(passmgr);
4656
4657 /* Add some optimization passes */
4658 LLVMAddScalarReplAggregatesPass(passmgr);
4659 LLVMAddLICMPass(passmgr);
4660 LLVMAddAggressiveDCEPass(passmgr);
4661 LLVMAddCFGSimplificationPass(passmgr);
4662 LLVMAddInstructionCombiningPass(passmgr);
4663
4664 /* Run the pass */
4665 LLVMInitializeFunctionPassManager(passmgr);
4666 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
4667 LLVMFinalizeFunctionPassManager(passmgr);
4668
4669 LLVMDisposeBuilder(ctx->builder);
4670 LLVMDisposePassManager(passmgr);
4671 }
4672
4673 static void
4674 ac_setup_rings(struct nir_to_llvm_context *ctx)
4675 {
4676 if (ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) {
4677 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, ctx->i32one);
4678 }
4679
4680 if (ctx->is_gs_copy_shader) {
4681 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 3, false));
4682 }
4683 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4684 LLVMValueRef tmp;
4685 ctx->esgs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 2, false));
4686 ctx->gsvs_ring = build_indexed_load_const(ctx, ctx->ring_offsets, LLVMConstInt(ctx->i32, 4, false));
4687
4688 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v4i32, "");
4689
4690 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->i32, 2, false), "");
4691 tmp = LLVMBuildExtractElement(ctx->builder, ctx->gsvs_ring, ctx->i32one, "");
4692 tmp = LLVMBuildOr(ctx->builder, tmp, ctx->gsvs_ring_stride, "");
4693 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->builder, ctx->gsvs_ring, tmp, ctx->i32one, "");
4694
4695 ctx->gsvs_ring = LLVMBuildBitCast(ctx->builder, ctx->gsvs_ring, ctx->v16i8, "");
4696 }
4697 }
4698
4699 static
4700 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
4701 struct nir_shader *nir,
4702 struct ac_shader_variant_info *shader_info,
4703 const struct ac_nir_compiler_options *options)
4704 {
4705 struct nir_to_llvm_context ctx = {0};
4706 struct nir_function *func;
4707 unsigned i;
4708 ctx.options = options;
4709 ctx.shader_info = shader_info;
4710 ctx.context = LLVMContextCreate();
4711 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
4712
4713 ac_llvm_context_init(&ctx.ac, ctx.context);
4714 ctx.ac.module = ctx.module;
4715
4716 ctx.has_ds_bpermute = ctx.options->chip_class >= VI;
4717
4718 memset(shader_info, 0, sizeof(*shader_info));
4719
4720 LLVMSetTarget(ctx.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
4721 setup_types(&ctx);
4722
4723 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
4724 ctx.ac.builder = ctx.builder;
4725 ctx.stage = nir->stage;
4726
4727 for (i = 0; i < AC_UD_MAX_SETS; i++)
4728 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4729 for (i = 0; i < AC_UD_MAX_UD; i++)
4730 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4731
4732 create_function(&ctx);
4733
4734 if (nir->stage == MESA_SHADER_COMPUTE) {
4735 int num_shared = 0;
4736 nir_foreach_variable(variable, &nir->shared)
4737 num_shared++;
4738 if (num_shared) {
4739 int idx = 0;
4740 uint32_t shared_size = 0;
4741 LLVMValueRef var;
4742 LLVMTypeRef i8p = LLVMPointerType(ctx.i8, LOCAL_ADDR_SPACE);
4743 nir_foreach_variable(variable, &nir->shared) {
4744 handle_shared_compute_var(&ctx, variable, &shared_size, idx);
4745 idx++;
4746 }
4747
4748 shared_size *= 4;
4749 var = LLVMAddGlobalInAddressSpace(ctx.module,
4750 LLVMArrayType(ctx.i8, shared_size),
4751 "compute_lds",
4752 LOCAL_ADDR_SPACE);
4753 LLVMSetAlignment(var, 4);
4754 ctx.shared_memory = LLVMBuildBitCast(ctx.builder, var, i8p, "");
4755 }
4756 } else if (nir->stage == MESA_SHADER_GEOMETRY) {
4757 ctx.gs_next_vertex = ac_build_alloca(&ctx, ctx.i32, "gs_next_vertex");
4758
4759 ctx.gs_max_out_vertices = nir->info->gs.vertices_out;
4760 }
4761
4762 ac_setup_rings(&ctx);
4763
4764 nir_foreach_variable(variable, &nir->inputs)
4765 handle_shader_input_decl(&ctx, variable);
4766
4767 if (nir->stage == MESA_SHADER_FRAGMENT)
4768 handle_fs_inputs_pre(&ctx, nir);
4769
4770 nir_foreach_variable(variable, &nir->outputs)
4771 handle_shader_output_decl(&ctx, variable);
4772
4773 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4774 _mesa_key_pointer_equal);
4775 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
4776 _mesa_key_pointer_equal);
4777
4778 func = (struct nir_function *)exec_list_get_head(&nir->functions);
4779
4780 setup_locals(&ctx, func);
4781
4782 visit_cf_list(&ctx, &func->impl->body);
4783 phi_post_pass(&ctx);
4784
4785 handle_shader_outputs_post(&ctx);
4786 LLVMBuildRetVoid(ctx.builder);
4787
4788 ac_llvm_finalize_module(&ctx);
4789 free(ctx.locals);
4790 ralloc_free(ctx.defs);
4791 ralloc_free(ctx.phis);
4792
4793 if (nir->stage == MESA_SHADER_GEOMETRY) {
4794 shader_info->gs.gsvs_vertex_size = util_bitcount64(ctx.output_mask) * 16;
4795 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
4796 nir->info->gs.vertices_out;
4797 }
4798 return ctx.module;
4799 }
4800
4801 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4802 {
4803 unsigned *retval = (unsigned *)context;
4804 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4805 char *description = LLVMGetDiagInfoDescription(di);
4806
4807 if (severity == LLVMDSError) {
4808 *retval = 1;
4809 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4810 description);
4811 }
4812
4813 LLVMDisposeMessage(description);
4814 }
4815
4816 static unsigned ac_llvm_compile(LLVMModuleRef M,
4817 struct ac_shader_binary *binary,
4818 LLVMTargetMachineRef tm)
4819 {
4820 unsigned retval = 0;
4821 char *err;
4822 LLVMContextRef llvm_ctx;
4823 LLVMMemoryBufferRef out_buffer;
4824 unsigned buffer_size;
4825 const char *buffer_data;
4826 LLVMBool mem_err;
4827
4828 /* Setup Diagnostic Handler*/
4829 llvm_ctx = LLVMGetModuleContext(M);
4830
4831 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4832 &retval);
4833
4834 /* Compile IR*/
4835 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
4836 &err, &out_buffer);
4837
4838 /* Process Errors/Warnings */
4839 if (mem_err) {
4840 fprintf(stderr, "%s: %s", __FUNCTION__, err);
4841 free(err);
4842 retval = 1;
4843 goto out;
4844 }
4845
4846 /* Extract Shader Code*/
4847 buffer_size = LLVMGetBufferSize(out_buffer);
4848 buffer_data = LLVMGetBufferStart(out_buffer);
4849
4850 ac_elf_read(buffer_data, buffer_size, binary);
4851
4852 /* Clean up */
4853 LLVMDisposeMemoryBuffer(out_buffer);
4854
4855 out:
4856 return retval;
4857 }
4858
4859 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
4860 LLVMModuleRef llvm_module,
4861 struct ac_shader_binary *binary,
4862 struct ac_shader_config *config,
4863 struct ac_shader_variant_info *shader_info,
4864 gl_shader_stage stage,
4865 bool dump_shader, bool supports_spill)
4866 {
4867 if (dump_shader)
4868 ac_dump_module(llvm_module);
4869
4870 memset(binary, 0, sizeof(*binary));
4871 int v = ac_llvm_compile(llvm_module, binary, tm);
4872 if (v) {
4873 fprintf(stderr, "compile failed\n");
4874 }
4875
4876 if (dump_shader)
4877 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
4878
4879 ac_shader_binary_read_config(binary, config, 0, supports_spill);
4880
4881 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4882 LLVMDisposeModule(llvm_module);
4883 LLVMContextDispose(ctx);
4884
4885 if (stage == MESA_SHADER_FRAGMENT) {
4886 shader_info->num_input_vgprs = 0;
4887 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
4888 shader_info->num_input_vgprs += 2;
4889 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
4890 shader_info->num_input_vgprs += 2;
4891 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
4892 shader_info->num_input_vgprs += 2;
4893 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
4894 shader_info->num_input_vgprs += 3;
4895 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
4896 shader_info->num_input_vgprs += 2;
4897 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
4898 shader_info->num_input_vgprs += 2;
4899 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
4900 shader_info->num_input_vgprs += 2;
4901 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
4902 shader_info->num_input_vgprs += 1;
4903 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
4904 shader_info->num_input_vgprs += 1;
4905 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
4906 shader_info->num_input_vgprs += 1;
4907 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
4908 shader_info->num_input_vgprs += 1;
4909 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
4910 shader_info->num_input_vgprs += 1;
4911 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
4912 shader_info->num_input_vgprs += 1;
4913 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
4914 shader_info->num_input_vgprs += 1;
4915 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
4916 shader_info->num_input_vgprs += 1;
4917 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
4918 shader_info->num_input_vgprs += 1;
4919 }
4920 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
4921
4922 /* +3 for scratch wave offset and VCC */
4923 config->num_sgprs = MAX2(config->num_sgprs,
4924 shader_info->num_input_sgprs + 3);
4925 }
4926
4927 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
4928 struct ac_shader_binary *binary,
4929 struct ac_shader_config *config,
4930 struct ac_shader_variant_info *shader_info,
4931 struct nir_shader *nir,
4932 const struct ac_nir_compiler_options *options,
4933 bool dump_shader)
4934 {
4935
4936 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, shader_info,
4937 options);
4938
4939 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir->stage, dump_shader, options->supports_spill);
4940 switch (nir->stage) {
4941 case MESA_SHADER_COMPUTE:
4942 for (int i = 0; i < 3; ++i)
4943 shader_info->cs.block_size[i] = nir->info->cs.local_size[i];
4944 break;
4945 case MESA_SHADER_FRAGMENT:
4946 shader_info->fs.early_fragment_test = nir->info->fs.early_fragment_tests;
4947 break;
4948 case MESA_SHADER_GEOMETRY:
4949 shader_info->gs.vertices_in = nir->info->gs.vertices_in;
4950 shader_info->gs.vertices_out = nir->info->gs.vertices_out;
4951 shader_info->gs.output_prim = nir->info->gs.output_primitive;
4952 shader_info->gs.invocations = nir->info->gs.invocations;
4953 break;
4954 case MESA_SHADER_VERTEX:
4955 shader_info->vs.as_es = options->key.vs.as_es;
4956 break;
4957 default:
4958 break;
4959 }
4960 }
4961
4962 static void
4963 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
4964 {
4965 LLVMValueRef args[9];
4966 args[0] = ctx->gsvs_ring;
4967 args[1] = LLVMBuildMul(ctx->builder, ctx->vertex_id, LLVMConstInt(ctx->i32, 4, false), "");
4968 args[3] = ctx->i32zero;
4969 args[4] = ctx->i32one; /* OFFEN */
4970 args[5] = ctx->i32zero; /* IDXEN */
4971 args[6] = ctx->i32one; /* GLC */
4972 args[7] = ctx->i32one; /* SLC */
4973 args[8] = ctx->i32zero; /* TFE */
4974
4975 int idx = 0;
4976 for (unsigned i = 0; i < RADEON_LLVM_MAX_OUTPUTS; ++i) {
4977 if (!(ctx->output_mask & (1ull << i)))
4978 continue;
4979
4980 for (unsigned j = 0; j < 4; j++) {
4981 LLVMValueRef value;
4982 args[2] = LLVMConstInt(ctx->i32,
4983 (idx * 4 + j) *
4984 ctx->gs_max_out_vertices * 16 * 4, false);
4985
4986 value = ac_emit_llvm_intrinsic(&ctx->ac,
4987 "llvm.SI.buffer.load.dword.i32.i32",
4988 ctx->i32, args, 9,
4989 AC_FUNC_ATTR_READONLY);
4990
4991 LLVMBuildStore(ctx->builder,
4992 to_float(ctx, value), ctx->outputs[radeon_llvm_reg_index_soa(i, j)]);
4993 }
4994 idx++;
4995 }
4996 handle_vs_outputs_post(ctx);
4997 }
4998
4999 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
5000 struct nir_shader *geom_shader,
5001 struct ac_shader_binary *binary,
5002 struct ac_shader_config *config,
5003 struct ac_shader_variant_info *shader_info,
5004 const struct ac_nir_compiler_options *options,
5005 bool dump_shader)
5006 {
5007 struct nir_to_llvm_context ctx = {0};
5008 ctx.context = LLVMContextCreate();
5009 ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
5010 ctx.options = options;
5011 ctx.shader_info = shader_info;
5012
5013 ac_llvm_context_init(&ctx.ac, ctx.context);
5014 ctx.ac.module = ctx.module;
5015
5016 ctx.is_gs_copy_shader = true;
5017 LLVMSetTarget(ctx.module, "amdgcn--");
5018 setup_types(&ctx);
5019
5020 ctx.builder = LLVMCreateBuilderInContext(ctx.context);
5021 ctx.ac.builder = ctx.builder;
5022 ctx.stage = MESA_SHADER_VERTEX;
5023
5024 create_function(&ctx);
5025
5026 ctx.gs_max_out_vertices = geom_shader->info->gs.vertices_out;
5027 ac_setup_rings(&ctx);
5028
5029 nir_foreach_variable(variable, &geom_shader->outputs)
5030 handle_shader_output_decl(&ctx, variable);
5031
5032 ac_gs_copy_shader_emit(&ctx);
5033
5034 LLVMBuildRetVoid(ctx.builder);
5035
5036 ac_llvm_finalize_module(&ctx);
5037
5038 ac_compile_llvm_module(tm, ctx.module, binary, config, shader_info,
5039 MESA_SHADER_VERTEX,
5040 dump_shader, options->supports_spill);
5041 }