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[mesa.git] / src / amd / common / ac_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Bas Nieuwenhuizen
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ac_nir_to_llvm.h"
25 #include "ac_llvm_build.h"
26 #include "ac_llvm_util.h"
27 #include "ac_binary.h"
28 #include "sid.h"
29 #include "nir/nir.h"
30 #include "../vulkan/radv_descriptor_set.h"
31 #include "util/bitscan.h"
32 #include <llvm-c/Transforms/Scalar.h>
33 #include "ac_shader_abi.h"
34 #include "ac_shader_info.h"
35 #include "ac_shader_util.h"
36 #include "ac_exp_param.h"
37
38 enum radeon_llvm_calling_convention {
39 RADEON_LLVM_AMDGPU_VS = 87,
40 RADEON_LLVM_AMDGPU_GS = 88,
41 RADEON_LLVM_AMDGPU_PS = 89,
42 RADEON_LLVM_AMDGPU_CS = 90,
43 RADEON_LLVM_AMDGPU_HS = 93,
44 };
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct ac_nir_context {
49 struct ac_llvm_context ac;
50 struct ac_shader_abi *abi;
51
52 gl_shader_stage stage;
53
54 struct hash_table *defs;
55 struct hash_table *phis;
56 struct hash_table *vars;
57
58 LLVMValueRef main_function;
59 LLVMBasicBlockRef continue_block;
60 LLVMBasicBlockRef break_block;
61
62 int num_locals;
63 LLVMValueRef *locals;
64 };
65
66 struct nir_to_llvm_context {
67 struct ac_llvm_context ac;
68 const struct ac_nir_compiler_options *options;
69 struct ac_shader_variant_info *shader_info;
70 struct ac_shader_abi abi;
71
72 unsigned max_workgroup_size;
73 LLVMContextRef context;
74 LLVMValueRef main_function;
75
76 LLVMValueRef descriptor_sets[AC_UD_MAX_SETS];
77 LLVMValueRef ring_offsets;
78
79 LLVMValueRef vertex_buffers;
80 LLVMValueRef rel_auto_id;
81 LLVMValueRef vs_prim_id;
82 LLVMValueRef ls_out_layout;
83 LLVMValueRef es2gs_offset;
84
85 LLVMValueRef tcs_offchip_layout;
86 LLVMValueRef tcs_out_offsets;
87 LLVMValueRef tcs_out_layout;
88 LLVMValueRef tcs_in_layout;
89 LLVMValueRef oc_lds;
90 LLVMValueRef merged_wave_info;
91 LLVMValueRef tess_factor_offset;
92 LLVMValueRef tes_rel_patch_id;
93 LLVMValueRef tes_u;
94 LLVMValueRef tes_v;
95
96 LLVMValueRef gsvs_ring_stride;
97 LLVMValueRef gsvs_num_entries;
98 LLVMValueRef gs2vs_offset;
99 LLVMValueRef gs_wave_id;
100 LLVMValueRef gs_vtx_offset[6];
101
102 LLVMValueRef esgs_ring;
103 LLVMValueRef gsvs_ring;
104 LLVMValueRef hs_ring_tess_offchip;
105 LLVMValueRef hs_ring_tess_factor;
106
107 LLVMValueRef sample_pos_offset;
108 LLVMValueRef persp_sample, persp_center, persp_centroid;
109 LLVMValueRef linear_sample, linear_center, linear_centroid;
110
111 gl_shader_stage stage;
112
113 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
114
115 uint64_t input_mask;
116 uint64_t output_mask;
117 uint8_t num_output_clips;
118 uint8_t num_output_culls;
119
120 bool is_gs_copy_shader;
121 LLVMValueRef gs_next_vertex;
122 unsigned gs_max_out_vertices;
123
124 unsigned tes_primitive_mode;
125 uint64_t tess_outputs_written;
126 uint64_t tess_patch_outputs_written;
127
128 uint32_t tcs_patch_outputs_read;
129 uint64_t tcs_outputs_read;
130 };
131
132 static inline struct nir_to_llvm_context *
133 nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
134 {
135 struct nir_to_llvm_context *ctx = NULL;
136 return container_of(abi, ctx, abi);
137 }
138
139 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
140 const nir_deref_var *deref,
141 enum ac_descriptor_type desc_type,
142 const nir_tex_instr *instr,
143 bool image, bool write);
144
145 static unsigned radeon_llvm_reg_index_soa(unsigned index, unsigned chan)
146 {
147 return (index * 4) + chan;
148 }
149
150 static unsigned shader_io_get_unique_index(gl_varying_slot slot)
151 {
152 /* handle patch indices separate */
153 if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
154 return 0;
155 if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
156 return 1;
157 if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
158 return 2 + (slot - VARYING_SLOT_PATCH0);
159
160 if (slot == VARYING_SLOT_POS)
161 return 0;
162 if (slot == VARYING_SLOT_PSIZ)
163 return 1;
164 if (slot == VARYING_SLOT_CLIP_DIST0)
165 return 2;
166 /* 3 is reserved for clip dist as well */
167 if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
168 return 4 + (slot - VARYING_SLOT_VAR0);
169 unreachable("illegal slot in get unique index\n");
170 }
171
172 static void set_llvm_calling_convention(LLVMValueRef func,
173 gl_shader_stage stage)
174 {
175 enum radeon_llvm_calling_convention calling_conv;
176
177 switch (stage) {
178 case MESA_SHADER_VERTEX:
179 case MESA_SHADER_TESS_EVAL:
180 calling_conv = RADEON_LLVM_AMDGPU_VS;
181 break;
182 case MESA_SHADER_GEOMETRY:
183 calling_conv = RADEON_LLVM_AMDGPU_GS;
184 break;
185 case MESA_SHADER_TESS_CTRL:
186 calling_conv = HAVE_LLVM >= 0x0500 ? RADEON_LLVM_AMDGPU_HS : RADEON_LLVM_AMDGPU_VS;
187 break;
188 case MESA_SHADER_FRAGMENT:
189 calling_conv = RADEON_LLVM_AMDGPU_PS;
190 break;
191 case MESA_SHADER_COMPUTE:
192 calling_conv = RADEON_LLVM_AMDGPU_CS;
193 break;
194 default:
195 unreachable("Unhandle shader type");
196 }
197
198 LLVMSetFunctionCallConv(func, calling_conv);
199 }
200
201 #define MAX_ARGS 23
202 struct arg_info {
203 LLVMTypeRef types[MAX_ARGS];
204 LLVMValueRef *assign[MAX_ARGS];
205 unsigned array_params_mask;
206 uint8_t count;
207 uint8_t sgpr_count;
208 uint8_t num_sgprs_used;
209 uint8_t num_vgprs_used;
210 };
211
212 enum ac_arg_regfile {
213 ARG_SGPR,
214 ARG_VGPR,
215 };
216
217 static void
218 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
219 LLVMValueRef *param_ptr)
220 {
221 assert(info->count < MAX_ARGS);
222
223 info->assign[info->count] = param_ptr;
224 info->types[info->count] = type;
225 info->count++;
226
227 if (regfile == ARG_SGPR) {
228 info->num_sgprs_used += ac_get_type_size(type) / 4;
229 info->sgpr_count++;
230 } else {
231 assert(regfile == ARG_VGPR);
232 info->num_vgprs_used += ac_get_type_size(type) / 4;
233 }
234 }
235
236 static inline void
237 add_array_arg(struct arg_info *info, LLVMTypeRef type, LLVMValueRef *param_ptr)
238 {
239 info->array_params_mask |= (1 << info->count);
240 add_arg(info, ARG_SGPR, type, param_ptr);
241 }
242
243 static void assign_arguments(LLVMValueRef main_function,
244 struct arg_info *info)
245 {
246 unsigned i;
247 for (i = 0; i < info->count; i++) {
248 if (info->assign[i])
249 *info->assign[i] = LLVMGetParam(main_function, i);
250 }
251 }
252
253 static LLVMValueRef
254 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
255 LLVMBuilderRef builder, LLVMTypeRef *return_types,
256 unsigned num_return_elems,
257 struct arg_info *args,
258 unsigned max_workgroup_size,
259 bool unsafe_math)
260 {
261 LLVMTypeRef main_function_type, ret_type;
262 LLVMBasicBlockRef main_function_body;
263
264 if (num_return_elems)
265 ret_type = LLVMStructTypeInContext(ctx, return_types,
266 num_return_elems, true);
267 else
268 ret_type = LLVMVoidTypeInContext(ctx);
269
270 /* Setup the function */
271 main_function_type =
272 LLVMFunctionType(ret_type, args->types, args->count, 0);
273 LLVMValueRef main_function =
274 LLVMAddFunction(module, "main", main_function_type);
275 main_function_body =
276 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
277 LLVMPositionBuilderAtEnd(builder, main_function_body);
278
279 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
280 for (unsigned i = 0; i < args->sgpr_count; ++i) {
281 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
282
283 if (args->array_params_mask & (1 << i)) {
284 LLVMValueRef P = LLVMGetParam(main_function, i);
285 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
286 ac_add_attr_dereferenceable(P, UINT64_MAX);
287 }
288 }
289
290 if (max_workgroup_size) {
291 ac_llvm_add_target_dep_function_attr(main_function,
292 "amdgpu-max-work-group-size",
293 max_workgroup_size);
294 }
295 if (unsafe_math) {
296 /* These were copied from some LLVM test. */
297 LLVMAddTargetDependentFunctionAttr(main_function,
298 "less-precise-fpmad",
299 "true");
300 LLVMAddTargetDependentFunctionAttr(main_function,
301 "no-infs-fp-math",
302 "true");
303 LLVMAddTargetDependentFunctionAttr(main_function,
304 "no-nans-fp-math",
305 "true");
306 LLVMAddTargetDependentFunctionAttr(main_function,
307 "unsafe-fp-math",
308 "true");
309 LLVMAddTargetDependentFunctionAttr(main_function,
310 "no-signed-zeros-fp-math",
311 "true");
312 }
313 return main_function;
314 }
315
316 static LLVMValueRef unpack_param(struct ac_llvm_context *ctx,
317 LLVMValueRef param, unsigned rshift,
318 unsigned bitwidth)
319 {
320 LLVMValueRef value = param;
321 if (rshift)
322 value = LLVMBuildLShr(ctx->builder, value,
323 LLVMConstInt(ctx->i32, rshift, false), "");
324
325 if (rshift + bitwidth < 32) {
326 unsigned mask = (1 << bitwidth) - 1;
327 value = LLVMBuildAnd(ctx->builder, value,
328 LLVMConstInt(ctx->i32, mask, false), "");
329 }
330 return value;
331 }
332
333 static LLVMValueRef get_rel_patch_id(struct nir_to_llvm_context *ctx)
334 {
335 switch (ctx->stage) {
336 case MESA_SHADER_TESS_CTRL:
337 return unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
338 case MESA_SHADER_TESS_EVAL:
339 return ctx->tes_rel_patch_id;
340 break;
341 default:
342 unreachable("Illegal stage");
343 }
344 }
345
346 /* Tessellation shaders pass outputs to the next shader using LDS.
347 *
348 * LS outputs = TCS inputs
349 * TCS outputs = TES inputs
350 *
351 * The LDS layout is:
352 * - TCS inputs for patch 0
353 * - TCS inputs for patch 1
354 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
355 * - ...
356 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
357 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
358 * - TCS outputs for patch 1
359 * - Per-patch TCS outputs for patch 1
360 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
361 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
362 * - ...
363 *
364 * All three shaders VS(LS), TCS, TES share the same LDS space.
365 */
366 static LLVMValueRef
367 get_tcs_in_patch_stride(struct nir_to_llvm_context *ctx)
368 {
369 if (ctx->stage == MESA_SHADER_VERTEX)
370 return unpack_param(&ctx->ac, ctx->ls_out_layout, 0, 13);
371 else if (ctx->stage == MESA_SHADER_TESS_CTRL)
372 return unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
373 else {
374 assert(0);
375 return NULL;
376 }
377 }
378
379 static LLVMValueRef
380 get_tcs_out_patch_stride(struct nir_to_llvm_context *ctx)
381 {
382 return unpack_param(&ctx->ac, ctx->tcs_out_layout, 0, 13);
383 }
384
385 static LLVMValueRef
386 get_tcs_out_patch0_offset(struct nir_to_llvm_context *ctx)
387 {
388 return LLVMBuildMul(ctx->ac.builder,
389 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 0, 16),
390 LLVMConstInt(ctx->ac.i32, 4, false), "");
391 }
392
393 static LLVMValueRef
394 get_tcs_out_patch0_patch_data_offset(struct nir_to_llvm_context *ctx)
395 {
396 return LLVMBuildMul(ctx->ac.builder,
397 unpack_param(&ctx->ac, ctx->tcs_out_offsets, 16, 16),
398 LLVMConstInt(ctx->ac.i32, 4, false), "");
399 }
400
401 static LLVMValueRef
402 get_tcs_in_current_patch_offset(struct nir_to_llvm_context *ctx)
403 {
404 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
405 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
406
407 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
408 }
409
410 static LLVMValueRef
411 get_tcs_out_current_patch_offset(struct nir_to_llvm_context *ctx)
412 {
413 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
414 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
415 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
416
417 return LLVMBuildAdd(ctx->ac.builder, patch0_offset,
418 LLVMBuildMul(ctx->ac.builder, patch_stride,
419 rel_patch_id, ""),
420 "");
421 }
422
423 static LLVMValueRef
424 get_tcs_out_current_patch_data_offset(struct nir_to_llvm_context *ctx)
425 {
426 LLVMValueRef patch0_patch_data_offset =
427 get_tcs_out_patch0_patch_data_offset(ctx);
428 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
429 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
430
431 return LLVMBuildAdd(ctx->ac.builder, patch0_patch_data_offset,
432 LLVMBuildMul(ctx->ac.builder, patch_stride,
433 rel_patch_id, ""),
434 "");
435 }
436
437 static void
438 set_loc(struct ac_userdata_info *ud_info, uint8_t *sgpr_idx, uint8_t num_sgprs,
439 uint32_t indirect_offset)
440 {
441 ud_info->sgpr_idx = *sgpr_idx;
442 ud_info->num_sgprs = num_sgprs;
443 ud_info->indirect = indirect_offset > 0;
444 ud_info->indirect_offset = indirect_offset;
445 *sgpr_idx += num_sgprs;
446 }
447
448 static void
449 set_loc_shader(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
450 uint8_t num_sgprs)
451 {
452 struct ac_userdata_info *ud_info =
453 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
454 assert(ud_info);
455
456 set_loc(ud_info, sgpr_idx, num_sgprs, 0);
457 }
458
459 static void
460 set_loc_desc(struct nir_to_llvm_context *ctx, int idx, uint8_t *sgpr_idx,
461 uint32_t indirect_offset)
462 {
463 struct ac_userdata_info *ud_info =
464 &ctx->shader_info->user_sgprs_locs.descriptor_sets[idx];
465 assert(ud_info);
466
467 set_loc(ud_info, sgpr_idx, 2, indirect_offset);
468 }
469
470 struct user_sgpr_info {
471 bool need_ring_offsets;
472 uint8_t sgpr_count;
473 bool indirect_all_descriptor_sets;
474 };
475
476 static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
477 gl_shader_stage stage)
478 {
479 switch (stage) {
480 case MESA_SHADER_VERTEX:
481 if (ctx->shader_info->info.needs_multiview_view_index ||
482 (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls && ctx->options->key.has_multiview_view_index))
483 return true;
484 break;
485 case MESA_SHADER_TESS_EVAL:
486 if (ctx->shader_info->info.needs_multiview_view_index || (!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
487 return true;
488 break;
489 case MESA_SHADER_GEOMETRY:
490 case MESA_SHADER_TESS_CTRL:
491 if (ctx->shader_info->info.needs_multiview_view_index)
492 return true;
493 break;
494 default:
495 break;
496 }
497 return false;
498 }
499
500 static uint8_t
501 count_vs_user_sgprs(struct nir_to_llvm_context *ctx)
502 {
503 uint8_t count = 0;
504
505 count += ctx->shader_info->info.vs.has_vertex_buffers ? 2 : 0;
506 count += ctx->shader_info->info.vs.needs_draw_id ? 3 : 2;
507
508 return count;
509 }
510
511 static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
512 gl_shader_stage stage,
513 bool has_previous_stage,
514 gl_shader_stage previous_stage,
515 bool needs_view_index,
516 struct user_sgpr_info *user_sgpr_info)
517 {
518 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
519
520 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
521 if (stage == MESA_SHADER_GEOMETRY ||
522 stage == MESA_SHADER_VERTEX ||
523 stage == MESA_SHADER_TESS_CTRL ||
524 stage == MESA_SHADER_TESS_EVAL ||
525 ctx->is_gs_copy_shader)
526 user_sgpr_info->need_ring_offsets = true;
527
528 if (stage == MESA_SHADER_FRAGMENT &&
529 ctx->shader_info->info.ps.needs_sample_positions)
530 user_sgpr_info->need_ring_offsets = true;
531
532 /* 2 user sgprs will nearly always be allocated for scratch/rings */
533 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
534 user_sgpr_info->sgpr_count += 2;
535 }
536
537 switch (stage) {
538 case MESA_SHADER_COMPUTE:
539 if (ctx->shader_info->info.cs.uses_grid_size)
540 user_sgpr_info->sgpr_count += 3;
541 break;
542 case MESA_SHADER_FRAGMENT:
543 user_sgpr_info->sgpr_count += ctx->shader_info->info.ps.needs_sample_positions;
544 break;
545 case MESA_SHADER_VERTEX:
546 if (!ctx->is_gs_copy_shader)
547 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
548 if (ctx->options->key.vs.as_ls)
549 user_sgpr_info->sgpr_count++;
550 break;
551 case MESA_SHADER_TESS_CTRL:
552 if (has_previous_stage) {
553 if (previous_stage == MESA_SHADER_VERTEX)
554 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
555 user_sgpr_info->sgpr_count++;
556 }
557 user_sgpr_info->sgpr_count += 4;
558 break;
559 case MESA_SHADER_TESS_EVAL:
560 user_sgpr_info->sgpr_count += 1;
561 break;
562 case MESA_SHADER_GEOMETRY:
563 if (has_previous_stage) {
564 if (previous_stage == MESA_SHADER_VERTEX) {
565 user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
566 } else {
567 user_sgpr_info->sgpr_count++;
568 }
569 }
570 user_sgpr_info->sgpr_count += 2;
571 break;
572 default:
573 break;
574 }
575
576 if (needs_view_index)
577 user_sgpr_info->sgpr_count++;
578
579 if (ctx->shader_info->info.loads_push_constants)
580 user_sgpr_info->sgpr_count += 2;
581
582 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16;
583 uint32_t remaining_sgprs = available_sgprs - user_sgpr_info->sgpr_count;
584
585 if (remaining_sgprs / 2 < util_bitcount(ctx->shader_info->info.desc_set_used_mask)) {
586 user_sgpr_info->sgpr_count += 2;
587 user_sgpr_info->indirect_all_descriptor_sets = true;
588 } else {
589 user_sgpr_info->sgpr_count += util_bitcount(ctx->shader_info->info.desc_set_used_mask) * 2;
590 }
591 }
592
593 static void
594 declare_global_input_sgprs(struct nir_to_llvm_context *ctx,
595 gl_shader_stage stage,
596 bool has_previous_stage,
597 gl_shader_stage previous_stage,
598 const struct user_sgpr_info *user_sgpr_info,
599 struct arg_info *args,
600 LLVMValueRef *desc_sets)
601 {
602 LLVMTypeRef type = ac_array_in_const_addr_space(ctx->ac.i8);
603 unsigned num_sets = ctx->options->layout ?
604 ctx->options->layout->num_sets : 0;
605 unsigned stage_mask = 1 << stage;
606
607 if (has_previous_stage)
608 stage_mask |= 1 << previous_stage;
609
610 /* 1 for each descriptor set */
611 if (!user_sgpr_info->indirect_all_descriptor_sets) {
612 for (unsigned i = 0; i < num_sets; ++i) {
613 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
614 add_array_arg(args, type,
615 &ctx->descriptor_sets[i]);
616 }
617 }
618 } else {
619 add_array_arg(args, ac_array_in_const_addr_space(type), desc_sets);
620 }
621
622 if (ctx->shader_info->info.loads_push_constants) {
623 /* 1 for push constants and dynamic descriptors */
624 add_array_arg(args, type, &ctx->abi.push_constants);
625 }
626 }
627
628 static void
629 declare_vs_specific_input_sgprs(struct nir_to_llvm_context *ctx,
630 gl_shader_stage stage,
631 bool has_previous_stage,
632 gl_shader_stage previous_stage,
633 struct arg_info *args)
634 {
635 if (!ctx->is_gs_copy_shader &&
636 (stage == MESA_SHADER_VERTEX ||
637 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
638 if (ctx->shader_info->info.vs.has_vertex_buffers) {
639 add_arg(args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
640 &ctx->vertex_buffers);
641 }
642 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
643 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
644 if (ctx->shader_info->info.vs.needs_draw_id) {
645 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
646 }
647 }
648 }
649
650 static void
651 declare_vs_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
652 {
653 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
654 if (!ctx->is_gs_copy_shader) {
655 if (ctx->options->key.vs.as_ls) {
656 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
657 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
658 } else {
659 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
660 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
661 }
662 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
663 }
664 }
665
666 static void
667 declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, struct arg_info *args)
668 {
669 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
670 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
671 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
672 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
673 }
674
675 static void
676 set_global_input_locs(struct nir_to_llvm_context *ctx, gl_shader_stage stage,
677 bool has_previous_stage, gl_shader_stage previous_stage,
678 const struct user_sgpr_info *user_sgpr_info,
679 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
680 {
681 unsigned num_sets = ctx->options->layout ?
682 ctx->options->layout->num_sets : 0;
683 unsigned stage_mask = 1 << stage;
684
685 if (has_previous_stage)
686 stage_mask |= 1 << previous_stage;
687
688 if (!user_sgpr_info->indirect_all_descriptor_sets) {
689 for (unsigned i = 0; i < num_sets; ++i) {
690 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
691 set_loc_desc(ctx, i, user_sgpr_idx, 0);
692 } else
693 ctx->descriptor_sets[i] = NULL;
694 }
695 } else {
696 set_loc_shader(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
697 user_sgpr_idx, 2);
698
699 for (unsigned i = 0; i < num_sets; ++i) {
700 if (ctx->options->layout->set[i].layout->shader_stages & stage_mask) {
701 set_loc_desc(ctx, i, user_sgpr_idx, i * 8);
702 ctx->descriptor_sets[i] =
703 ac_build_load_to_sgpr(&ctx->ac,
704 desc_sets,
705 LLVMConstInt(ctx->ac.i32, i, false));
706
707 } else
708 ctx->descriptor_sets[i] = NULL;
709 }
710 ctx->shader_info->need_indirect_descriptor_sets = true;
711 }
712
713 if (ctx->shader_info->info.loads_push_constants) {
714 set_loc_shader(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx, 2);
715 }
716 }
717
718 static void
719 set_vs_specific_input_locs(struct nir_to_llvm_context *ctx,
720 gl_shader_stage stage, bool has_previous_stage,
721 gl_shader_stage previous_stage,
722 uint8_t *user_sgpr_idx)
723 {
724 if (!ctx->is_gs_copy_shader &&
725 (stage == MESA_SHADER_VERTEX ||
726 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
727 if (ctx->shader_info->info.vs.has_vertex_buffers) {
728 set_loc_shader(ctx, AC_UD_VS_VERTEX_BUFFERS,
729 user_sgpr_idx, 2);
730 }
731
732 unsigned vs_num = 2;
733 if (ctx->shader_info->info.vs.needs_draw_id)
734 vs_num++;
735
736 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
737 user_sgpr_idx, vs_num);
738 }
739 }
740
741 static void create_function(struct nir_to_llvm_context *ctx,
742 gl_shader_stage stage,
743 bool has_previous_stage,
744 gl_shader_stage previous_stage)
745 {
746 uint8_t user_sgpr_idx;
747 struct user_sgpr_info user_sgpr_info;
748 struct arg_info args = {};
749 LLVMValueRef desc_sets;
750 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
751 allocate_user_sgprs(ctx, stage, has_previous_stage,
752 previous_stage, needs_view_index, &user_sgpr_info);
753
754 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
755 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
756 &ctx->ring_offsets);
757 }
758
759 switch (stage) {
760 case MESA_SHADER_COMPUTE:
761 declare_global_input_sgprs(ctx, stage, has_previous_stage,
762 previous_stage, &user_sgpr_info,
763 &args, &desc_sets);
764
765 if (ctx->shader_info->info.cs.uses_grid_size) {
766 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
767 &ctx->abi.num_work_groups);
768 }
769
770 for (int i = 0; i < 3; i++) {
771 ctx->abi.workgroup_ids[i] = NULL;
772 if (ctx->shader_info->info.cs.uses_block_id[i]) {
773 add_arg(&args, ARG_SGPR, ctx->ac.i32,
774 &ctx->abi.workgroup_ids[i]);
775 }
776 }
777
778 if (ctx->shader_info->info.cs.uses_local_invocation_idx)
779 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
780 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
781 &ctx->abi.local_invocation_ids);
782 break;
783 case MESA_SHADER_VERTEX:
784 declare_global_input_sgprs(ctx, stage, has_previous_stage,
785 previous_stage, &user_sgpr_info,
786 &args, &desc_sets);
787 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
788 previous_stage, &args);
789
790 if (needs_view_index)
791 add_arg(&args, ARG_SGPR, ctx->ac.i32,
792 &ctx->abi.view_index);
793 if (ctx->options->key.vs.as_es)
794 add_arg(&args, ARG_SGPR, ctx->ac.i32,
795 &ctx->es2gs_offset);
796 else if (ctx->options->key.vs.as_ls)
797 add_arg(&args, ARG_SGPR, ctx->ac.i32,
798 &ctx->ls_out_layout);
799
800 declare_vs_input_vgprs(ctx, &args);
801 break;
802 case MESA_SHADER_TESS_CTRL:
803 if (has_previous_stage) {
804 // First 6 system regs
805 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
806 add_arg(&args, ARG_SGPR, ctx->ac.i32,
807 &ctx->merged_wave_info);
808 add_arg(&args, ARG_SGPR, ctx->ac.i32,
809 &ctx->tess_factor_offset);
810
811 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
812 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
813 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
814
815 declare_global_input_sgprs(ctx, stage,
816 has_previous_stage,
817 previous_stage,
818 &user_sgpr_info, &args,
819 &desc_sets);
820 declare_vs_specific_input_sgprs(ctx, stage,
821 has_previous_stage,
822 previous_stage, &args);
823
824 add_arg(&args, ARG_SGPR, ctx->ac.i32,
825 &ctx->ls_out_layout);
826
827 add_arg(&args, ARG_SGPR, ctx->ac.i32,
828 &ctx->tcs_offchip_layout);
829 add_arg(&args, ARG_SGPR, ctx->ac.i32,
830 &ctx->tcs_out_offsets);
831 add_arg(&args, ARG_SGPR, ctx->ac.i32,
832 &ctx->tcs_out_layout);
833 add_arg(&args, ARG_SGPR, ctx->ac.i32,
834 &ctx->tcs_in_layout);
835 if (needs_view_index)
836 add_arg(&args, ARG_SGPR, ctx->ac.i32,
837 &ctx->abi.view_index);
838
839 add_arg(&args, ARG_VGPR, ctx->ac.i32,
840 &ctx->abi.tcs_patch_id);
841 add_arg(&args, ARG_VGPR, ctx->ac.i32,
842 &ctx->abi.tcs_rel_ids);
843
844 declare_vs_input_vgprs(ctx, &args);
845 } else {
846 declare_global_input_sgprs(ctx, stage,
847 has_previous_stage,
848 previous_stage,
849 &user_sgpr_info, &args,
850 &desc_sets);
851
852 add_arg(&args, ARG_SGPR, ctx->ac.i32,
853 &ctx->tcs_offchip_layout);
854 add_arg(&args, ARG_SGPR, ctx->ac.i32,
855 &ctx->tcs_out_offsets);
856 add_arg(&args, ARG_SGPR, ctx->ac.i32,
857 &ctx->tcs_out_layout);
858 add_arg(&args, ARG_SGPR, ctx->ac.i32,
859 &ctx->tcs_in_layout);
860 if (needs_view_index)
861 add_arg(&args, ARG_SGPR, ctx->ac.i32,
862 &ctx->abi.view_index);
863
864 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
865 add_arg(&args, ARG_SGPR, ctx->ac.i32,
866 &ctx->tess_factor_offset);
867 add_arg(&args, ARG_VGPR, ctx->ac.i32,
868 &ctx->abi.tcs_patch_id);
869 add_arg(&args, ARG_VGPR, ctx->ac.i32,
870 &ctx->abi.tcs_rel_ids);
871 }
872 break;
873 case MESA_SHADER_TESS_EVAL:
874 declare_global_input_sgprs(ctx, stage, has_previous_stage,
875 previous_stage, &user_sgpr_info,
876 &args, &desc_sets);
877
878 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
879 if (needs_view_index)
880 add_arg(&args, ARG_SGPR, ctx->ac.i32,
881 &ctx->abi.view_index);
882
883 if (ctx->options->key.tes.as_es) {
884 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
885 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
886 add_arg(&args, ARG_SGPR, ctx->ac.i32,
887 &ctx->es2gs_offset);
888 } else {
889 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
890 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
891 }
892 declare_tes_input_vgprs(ctx, &args);
893 break;
894 case MESA_SHADER_GEOMETRY:
895 if (has_previous_stage) {
896 // First 6 system regs
897 add_arg(&args, ARG_SGPR, ctx->ac.i32,
898 &ctx->gs2vs_offset);
899 add_arg(&args, ARG_SGPR, ctx->ac.i32,
900 &ctx->merged_wave_info);
901 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
902
903 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
904 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
905 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
906
907 declare_global_input_sgprs(ctx, stage,
908 has_previous_stage,
909 previous_stage,
910 &user_sgpr_info, &args,
911 &desc_sets);
912
913 if (previous_stage == MESA_SHADER_TESS_EVAL) {
914 add_arg(&args, ARG_SGPR, ctx->ac.i32,
915 &ctx->tcs_offchip_layout);
916 } else {
917 declare_vs_specific_input_sgprs(ctx, stage,
918 has_previous_stage,
919 previous_stage,
920 &args);
921 }
922
923 add_arg(&args, ARG_SGPR, ctx->ac.i32,
924 &ctx->gsvs_ring_stride);
925 add_arg(&args, ARG_SGPR, ctx->ac.i32,
926 &ctx->gsvs_num_entries);
927 if (needs_view_index)
928 add_arg(&args, ARG_SGPR, ctx->ac.i32,
929 &ctx->abi.view_index);
930
931 add_arg(&args, ARG_VGPR, ctx->ac.i32,
932 &ctx->gs_vtx_offset[0]);
933 add_arg(&args, ARG_VGPR, ctx->ac.i32,
934 &ctx->gs_vtx_offset[2]);
935 add_arg(&args, ARG_VGPR, ctx->ac.i32,
936 &ctx->abi.gs_prim_id);
937 add_arg(&args, ARG_VGPR, ctx->ac.i32,
938 &ctx->abi.gs_invocation_id);
939 add_arg(&args, ARG_VGPR, ctx->ac.i32,
940 &ctx->gs_vtx_offset[4]);
941
942 if (previous_stage == MESA_SHADER_VERTEX) {
943 declare_vs_input_vgprs(ctx, &args);
944 } else {
945 declare_tes_input_vgprs(ctx, &args);
946 }
947 } else {
948 declare_global_input_sgprs(ctx, stage,
949 has_previous_stage,
950 previous_stage,
951 &user_sgpr_info, &args,
952 &desc_sets);
953
954 add_arg(&args, ARG_SGPR, ctx->ac.i32,
955 &ctx->gsvs_ring_stride);
956 add_arg(&args, ARG_SGPR, ctx->ac.i32,
957 &ctx->gsvs_num_entries);
958 if (needs_view_index)
959 add_arg(&args, ARG_SGPR, ctx->ac.i32,
960 &ctx->abi.view_index);
961
962 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
963 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
964 add_arg(&args, ARG_VGPR, ctx->ac.i32,
965 &ctx->gs_vtx_offset[0]);
966 add_arg(&args, ARG_VGPR, ctx->ac.i32,
967 &ctx->gs_vtx_offset[1]);
968 add_arg(&args, ARG_VGPR, ctx->ac.i32,
969 &ctx->abi.gs_prim_id);
970 add_arg(&args, ARG_VGPR, ctx->ac.i32,
971 &ctx->gs_vtx_offset[2]);
972 add_arg(&args, ARG_VGPR, ctx->ac.i32,
973 &ctx->gs_vtx_offset[3]);
974 add_arg(&args, ARG_VGPR, ctx->ac.i32,
975 &ctx->gs_vtx_offset[4]);
976 add_arg(&args, ARG_VGPR, ctx->ac.i32,
977 &ctx->gs_vtx_offset[5]);
978 add_arg(&args, ARG_VGPR, ctx->ac.i32,
979 &ctx->abi.gs_invocation_id);
980 }
981 break;
982 case MESA_SHADER_FRAGMENT:
983 declare_global_input_sgprs(ctx, stage, has_previous_stage,
984 previous_stage, &user_sgpr_info,
985 &args, &desc_sets);
986
987 if (ctx->shader_info->info.ps.needs_sample_positions)
988 add_arg(&args, ARG_SGPR, ctx->ac.i32,
989 &ctx->sample_pos_offset);
990
991 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
992 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_sample);
993 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_center);
994 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->persp_centroid);
995 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
996 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_sample);
997 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_center);
998 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->linear_centroid);
999 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1000 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1001 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1002 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1003 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1004 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1005 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1006 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1007 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1008 break;
1009 default:
1010 unreachable("Shader stage not implemented");
1011 }
1012
1013 ctx->main_function = create_llvm_function(
1014 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1015 ctx->max_workgroup_size,
1016 ctx->options->unsafe_math);
1017 set_llvm_calling_convention(ctx->main_function, stage);
1018
1019
1020 ctx->shader_info->num_input_vgprs = 0;
1021 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1022
1023 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1024
1025 if (ctx->stage != MESA_SHADER_FRAGMENT)
1026 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1027
1028 assign_arguments(ctx->main_function, &args);
1029
1030 user_sgpr_idx = 0;
1031
1032 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1033 set_loc_shader(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1034 &user_sgpr_idx, 2);
1035 if (ctx->options->supports_spill) {
1036 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1037 LLVMPointerType(ctx->ac.i8, AC_CONST_ADDR_SPACE),
1038 NULL, 0, AC_FUNC_ATTR_READNONE);
1039 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1040 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1041 }
1042 }
1043
1044 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1045 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1046 if (has_previous_stage)
1047 user_sgpr_idx = 0;
1048
1049 set_global_input_locs(ctx, stage, has_previous_stage, previous_stage,
1050 &user_sgpr_info, desc_sets, &user_sgpr_idx);
1051
1052 switch (stage) {
1053 case MESA_SHADER_COMPUTE:
1054 if (ctx->shader_info->info.cs.uses_grid_size) {
1055 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1056 &user_sgpr_idx, 3);
1057 }
1058 break;
1059 case MESA_SHADER_VERTEX:
1060 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1061 previous_stage, &user_sgpr_idx);
1062 if (ctx->abi.view_index)
1063 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1064 if (ctx->options->key.vs.as_ls) {
1065 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1066 &user_sgpr_idx, 1);
1067 }
1068 if (ctx->options->key.vs.as_ls)
1069 ac_declare_lds_as_pointer(&ctx->ac);
1070 break;
1071 case MESA_SHADER_TESS_CTRL:
1072 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1073 previous_stage, &user_sgpr_idx);
1074 if (has_previous_stage)
1075 set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
1076 &user_sgpr_idx, 1);
1077 set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
1078 if (ctx->abi.view_index)
1079 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1080 ac_declare_lds_as_pointer(&ctx->ac);
1081 break;
1082 case MESA_SHADER_TESS_EVAL:
1083 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, &user_sgpr_idx, 1);
1084 if (ctx->abi.view_index)
1085 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1086 break;
1087 case MESA_SHADER_GEOMETRY:
1088 if (has_previous_stage) {
1089 if (previous_stage == MESA_SHADER_VERTEX)
1090 set_vs_specific_input_locs(ctx, stage,
1091 has_previous_stage,
1092 previous_stage,
1093 &user_sgpr_idx);
1094 else
1095 set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
1096 &user_sgpr_idx, 1);
1097 }
1098 set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
1099 &user_sgpr_idx, 2);
1100 if (ctx->abi.view_index)
1101 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1102 if (has_previous_stage)
1103 ac_declare_lds_as_pointer(&ctx->ac);
1104 break;
1105 case MESA_SHADER_FRAGMENT:
1106 if (ctx->shader_info->info.ps.needs_sample_positions) {
1107 set_loc_shader(ctx, AC_UD_PS_SAMPLE_POS_OFFSET,
1108 &user_sgpr_idx, 1);
1109 }
1110 break;
1111 default:
1112 unreachable("Shader stage not implemented");
1113 }
1114
1115 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1116 }
1117
1118 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
1119 LLVMValueRef value, unsigned count)
1120 {
1121 unsigned num_components = ac_get_llvm_num_components(value);
1122 if (count == num_components)
1123 return value;
1124
1125 LLVMValueRef masks[] = {
1126 LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
1127 LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
1128
1129 if (count == 1)
1130 return LLVMBuildExtractElement(ctx->builder, value, masks[0],
1131 "");
1132
1133 LLVMValueRef swizzle = LLVMConstVector(masks, count);
1134 return LLVMBuildShuffleVector(ctx->builder, value, value, swizzle, "");
1135 }
1136
1137 static void
1138 build_store_values_extended(struct ac_llvm_context *ac,
1139 LLVMValueRef *values,
1140 unsigned value_count,
1141 unsigned value_stride,
1142 LLVMValueRef vec)
1143 {
1144 LLVMBuilderRef builder = ac->builder;
1145 unsigned i;
1146
1147 for (i = 0; i < value_count; i++) {
1148 LLVMValueRef ptr = values[i * value_stride];
1149 LLVMValueRef index = LLVMConstInt(ac->i32, i, false);
1150 LLVMValueRef value = LLVMBuildExtractElement(builder, vec, index, "");
1151 LLVMBuildStore(builder, value, ptr);
1152 }
1153 }
1154
1155 static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
1156 const nir_ssa_def *def)
1157 {
1158 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, def->bit_size);
1159 if (def->num_components > 1) {
1160 type = LLVMVectorType(type, def->num_components);
1161 }
1162 return type;
1163 }
1164
1165 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
1166 {
1167 assert(src.is_ssa);
1168 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
1169 return (LLVMValueRef)entry->data;
1170 }
1171
1172 static LLVMValueRef
1173 get_memory_ptr(struct ac_nir_context *ctx, nir_src src)
1174 {
1175 LLVMValueRef ptr = get_src(ctx, src);
1176 ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ac.lds, &ptr, 1, "");
1177 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
1178
1179 return LLVMBuildBitCast(ctx->ac.builder, ptr,
1180 LLVMPointerType(ctx->ac.i32, addr_space), "");
1181 }
1182
1183 static LLVMBasicBlockRef get_block(struct ac_nir_context *nir,
1184 const struct nir_block *b)
1185 {
1186 struct hash_entry *entry = _mesa_hash_table_search(nir->defs, b);
1187 return (LLVMBasicBlockRef)entry->data;
1188 }
1189
1190 static LLVMValueRef get_alu_src(struct ac_nir_context *ctx,
1191 nir_alu_src src,
1192 unsigned num_components)
1193 {
1194 LLVMValueRef value = get_src(ctx, src.src);
1195 bool need_swizzle = false;
1196
1197 assert(value);
1198 LLVMTypeRef type = LLVMTypeOf(value);
1199 unsigned src_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
1200 ? LLVMGetVectorSize(type)
1201 : 1;
1202
1203 for (unsigned i = 0; i < num_components; ++i) {
1204 assert(src.swizzle[i] < src_components);
1205 if (src.swizzle[i] != i)
1206 need_swizzle = true;
1207 }
1208
1209 if (need_swizzle || num_components != src_components) {
1210 LLVMValueRef masks[] = {
1211 LLVMConstInt(ctx->ac.i32, src.swizzle[0], false),
1212 LLVMConstInt(ctx->ac.i32, src.swizzle[1], false),
1213 LLVMConstInt(ctx->ac.i32, src.swizzle[2], false),
1214 LLVMConstInt(ctx->ac.i32, src.swizzle[3], false)};
1215
1216 if (src_components > 1 && num_components == 1) {
1217 value = LLVMBuildExtractElement(ctx->ac.builder, value,
1218 masks[0], "");
1219 } else if (src_components == 1 && num_components > 1) {
1220 LLVMValueRef values[] = {value, value, value, value};
1221 value = ac_build_gather_values(&ctx->ac, values, num_components);
1222 } else {
1223 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
1224 value = LLVMBuildShuffleVector(ctx->ac.builder, value, value,
1225 swizzle, "");
1226 }
1227 }
1228 assert(!src.negate);
1229 assert(!src.abs);
1230 return value;
1231 }
1232
1233 static LLVMValueRef emit_int_cmp(struct ac_llvm_context *ctx,
1234 LLVMIntPredicate pred, LLVMValueRef src0,
1235 LLVMValueRef src1)
1236 {
1237 LLVMValueRef result = LLVMBuildICmp(ctx->builder, pred, src0, src1, "");
1238 return LLVMBuildSelect(ctx->builder, result,
1239 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1240 ctx->i32_0, "");
1241 }
1242
1243 static LLVMValueRef emit_float_cmp(struct ac_llvm_context *ctx,
1244 LLVMRealPredicate pred, LLVMValueRef src0,
1245 LLVMValueRef src1)
1246 {
1247 LLVMValueRef result;
1248 src0 = ac_to_float(ctx, src0);
1249 src1 = ac_to_float(ctx, src1);
1250 result = LLVMBuildFCmp(ctx->builder, pred, src0, src1, "");
1251 return LLVMBuildSelect(ctx->builder, result,
1252 LLVMConstInt(ctx->i32, 0xFFFFFFFF, false),
1253 ctx->i32_0, "");
1254 }
1255
1256 static LLVMValueRef emit_intrin_1f_param(struct ac_llvm_context *ctx,
1257 const char *intrin,
1258 LLVMTypeRef result_type,
1259 LLVMValueRef src0)
1260 {
1261 char name[64];
1262 LLVMValueRef params[] = {
1263 ac_to_float(ctx, src0),
1264 };
1265
1266 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1267 ac_get_elem_bits(ctx, result_type));
1268 assert(length < sizeof(name));
1269 return ac_build_intrinsic(ctx, name, result_type, params, 1, AC_FUNC_ATTR_READNONE);
1270 }
1271
1272 static LLVMValueRef emit_intrin_2f_param(struct ac_llvm_context *ctx,
1273 const char *intrin,
1274 LLVMTypeRef result_type,
1275 LLVMValueRef src0, LLVMValueRef src1)
1276 {
1277 char name[64];
1278 LLVMValueRef params[] = {
1279 ac_to_float(ctx, src0),
1280 ac_to_float(ctx, src1),
1281 };
1282
1283 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1284 ac_get_elem_bits(ctx, result_type));
1285 assert(length < sizeof(name));
1286 return ac_build_intrinsic(ctx, name, result_type, params, 2, AC_FUNC_ATTR_READNONE);
1287 }
1288
1289 static LLVMValueRef emit_intrin_3f_param(struct ac_llvm_context *ctx,
1290 const char *intrin,
1291 LLVMTypeRef result_type,
1292 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1293 {
1294 char name[64];
1295 LLVMValueRef params[] = {
1296 ac_to_float(ctx, src0),
1297 ac_to_float(ctx, src1),
1298 ac_to_float(ctx, src2),
1299 };
1300
1301 MAYBE_UNUSED const int length = snprintf(name, sizeof(name), "%s.f%d", intrin,
1302 ac_get_elem_bits(ctx, result_type));
1303 assert(length < sizeof(name));
1304 return ac_build_intrinsic(ctx, name, result_type, params, 3, AC_FUNC_ATTR_READNONE);
1305 }
1306
1307 static LLVMValueRef emit_bcsel(struct ac_llvm_context *ctx,
1308 LLVMValueRef src0, LLVMValueRef src1, LLVMValueRef src2)
1309 {
1310 LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
1311 ctx->i32_0, "");
1312 return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
1313 }
1314
1315 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,
1316 LLVMIntPredicate pred,
1317 LLVMValueRef src0, LLVMValueRef src1)
1318 {
1319 return LLVMBuildSelect(ctx->builder,
1320 LLVMBuildICmp(ctx->builder, pred, src0, src1, ""),
1321 src0,
1322 src1, "");
1323
1324 }
1325 static LLVMValueRef emit_iabs(struct ac_llvm_context *ctx,
1326 LLVMValueRef src0)
1327 {
1328 return emit_minmax_int(ctx, LLVMIntSGT, src0,
1329 LLVMBuildNeg(ctx->builder, src0, ""));
1330 }
1331
1332 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
1333 LLVMValueRef src0,
1334 unsigned bitsize)
1335 {
1336 LLVMValueRef cmp, val, zero, one;
1337 LLVMTypeRef type;
1338
1339 if (bitsize == 32) {
1340 type = ctx->f32;
1341 zero = ctx->f32_0;
1342 one = ctx->f32_1;
1343 } else {
1344 type = ctx->f64;
1345 zero = ctx->f64_0;
1346 one = ctx->f64_1;
1347 }
1348
1349 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
1350 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1351 cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
1352 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, -1.0), "");
1353 return val;
1354 }
1355
1356 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
1357 LLVMValueRef src0, unsigned bitsize)
1358 {
1359 LLVMValueRef cmp, val, zero, one;
1360 LLVMTypeRef type;
1361
1362 if (bitsize == 32) {
1363 type = ctx->i32;
1364 zero = ctx->i32_0;
1365 one = ctx->i32_1;
1366 } else {
1367 type = ctx->i64;
1368 zero = ctx->i64_0;
1369 one = ctx->i64_1;
1370 }
1371
1372 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
1373 val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
1374 cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
1375 val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, true), "");
1376 return val;
1377 }
1378
1379 static LLVMValueRef emit_ffract(struct ac_llvm_context *ctx,
1380 LLVMValueRef src0, unsigned bitsize)
1381 {
1382 LLVMTypeRef type;
1383 char *intr;
1384
1385 if (bitsize == 32) {
1386 intr = "llvm.floor.f32";
1387 type = ctx->f32;
1388 } else {
1389 intr = "llvm.floor.f64";
1390 type = ctx->f64;
1391 }
1392
1393 LLVMValueRef fsrc0 = ac_to_float(ctx, src0);
1394 LLVMValueRef params[] = {
1395 fsrc0,
1396 };
1397 LLVMValueRef floor = ac_build_intrinsic(ctx, intr, type, params, 1,
1398 AC_FUNC_ATTR_READNONE);
1399 return LLVMBuildFSub(ctx->builder, fsrc0, floor, "");
1400 }
1401
1402 static LLVMValueRef emit_uint_carry(struct ac_llvm_context *ctx,
1403 const char *intrin,
1404 LLVMValueRef src0, LLVMValueRef src1)
1405 {
1406 LLVMTypeRef ret_type;
1407 LLVMTypeRef types[] = { ctx->i32, ctx->i1 };
1408 LLVMValueRef res;
1409 LLVMValueRef params[] = { src0, src1 };
1410 ret_type = LLVMStructTypeInContext(ctx->context, types,
1411 2, true);
1412
1413 res = ac_build_intrinsic(ctx, intrin, ret_type,
1414 params, 2, AC_FUNC_ATTR_READNONE);
1415
1416 res = LLVMBuildExtractValue(ctx->builder, res, 1, "");
1417 res = LLVMBuildZExt(ctx->builder, res, ctx->i32, "");
1418 return res;
1419 }
1420
1421 static LLVMValueRef emit_b2f(struct ac_llvm_context *ctx,
1422 LLVMValueRef src0)
1423 {
1424 return LLVMBuildAnd(ctx->builder, src0, LLVMBuildBitCast(ctx->builder, LLVMConstReal(ctx->f32, 1.0), ctx->i32, ""), "");
1425 }
1426
1427 static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
1428 LLVMValueRef src0)
1429 {
1430 src0 = ac_to_float(ctx, src0);
1431 return LLVMBuildSExt(ctx->builder,
1432 LLVMBuildFCmp(ctx->builder, LLVMRealUNE, src0, ctx->f32_0, ""),
1433 ctx->i32, "");
1434 }
1435
1436 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
1437 LLVMValueRef src0,
1438 unsigned bitsize)
1439 {
1440 LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
1441
1442 if (bitsize == 32)
1443 return result;
1444
1445 return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
1446 }
1447
1448 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
1449 LLVMValueRef src0)
1450 {
1451 return LLVMBuildSExt(ctx->builder,
1452 LLVMBuildICmp(ctx->builder, LLVMIntNE, src0, ctx->i32_0, ""),
1453 ctx->i32, "");
1454 }
1455
1456 static LLVMValueRef emit_f2f16(struct ac_llvm_context *ctx,
1457 LLVMValueRef src0)
1458 {
1459 LLVMValueRef result;
1460 LLVMValueRef cond = NULL;
1461
1462 src0 = ac_to_float(ctx, src0);
1463 result = LLVMBuildFPTrunc(ctx->builder, src0, ctx->f16, "");
1464
1465 if (ctx->chip_class >= VI) {
1466 LLVMValueRef args[2];
1467 /* Check if the result is a denormal - and flush to 0 if so. */
1468 args[0] = result;
1469 args[1] = LLVMConstInt(ctx->i32, N_SUBNORMAL | P_SUBNORMAL, false);
1470 cond = ac_build_intrinsic(ctx, "llvm.amdgcn.class.f16", ctx->i1, args, 2, AC_FUNC_ATTR_READNONE);
1471 }
1472
1473 /* need to convert back up to f32 */
1474 result = LLVMBuildFPExt(ctx->builder, result, ctx->f32, "");
1475
1476 if (ctx->chip_class >= VI)
1477 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1478 else {
1479 /* for SI/CIK */
1480 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
1481 * so compare the result and flush to 0 if it's smaller.
1482 */
1483 LLVMValueRef temp, cond2;
1484 temp = emit_intrin_1f_param(ctx, "llvm.fabs", ctx->f32, result);
1485 cond = LLVMBuildFCmp(ctx->builder, LLVMRealUGT,
1486 LLVMBuildBitCast(ctx->builder, LLVMConstInt(ctx->i32, 0x38800000, false), ctx->f32, ""),
1487 temp, "");
1488 cond2 = LLVMBuildFCmp(ctx->builder, LLVMRealUNE,
1489 temp, ctx->f32_0, "");
1490 cond = LLVMBuildAnd(ctx->builder, cond, cond2, "");
1491 result = LLVMBuildSelect(ctx->builder, cond, ctx->f32_0, result, "");
1492 }
1493 return result;
1494 }
1495
1496 static LLVMValueRef emit_umul_high(struct ac_llvm_context *ctx,
1497 LLVMValueRef src0, LLVMValueRef src1)
1498 {
1499 LLVMValueRef dst64, result;
1500 src0 = LLVMBuildZExt(ctx->builder, src0, ctx->i64, "");
1501 src1 = LLVMBuildZExt(ctx->builder, src1, ctx->i64, "");
1502
1503 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1504 dst64 = LLVMBuildLShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1505 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1506 return result;
1507 }
1508
1509 static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
1510 LLVMValueRef src0, LLVMValueRef src1)
1511 {
1512 LLVMValueRef dst64, result;
1513 src0 = LLVMBuildSExt(ctx->builder, src0, ctx->i64, "");
1514 src1 = LLVMBuildSExt(ctx->builder, src1, ctx->i64, "");
1515
1516 dst64 = LLVMBuildMul(ctx->builder, src0, src1, "");
1517 dst64 = LLVMBuildAShr(ctx->builder, dst64, LLVMConstInt(ctx->i64, 32, false), "");
1518 result = LLVMBuildTrunc(ctx->builder, dst64, ctx->i32, "");
1519 return result;
1520 }
1521
1522 static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
1523 bool is_signed,
1524 const LLVMValueRef srcs[3])
1525 {
1526 LLVMValueRef result;
1527 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
1528
1529 result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
1530 result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
1531 return result;
1532 }
1533
1534 static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
1535 LLVMValueRef src0, LLVMValueRef src1,
1536 LLVMValueRef src2, LLVMValueRef src3)
1537 {
1538 LLVMValueRef bfi_args[3], result;
1539
1540 bfi_args[0] = LLVMBuildShl(ctx->builder,
1541 LLVMBuildSub(ctx->builder,
1542 LLVMBuildShl(ctx->builder,
1543 ctx->i32_1,
1544 src3, ""),
1545 ctx->i32_1, ""),
1546 src2, "");
1547 bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
1548 bfi_args[2] = src0;
1549
1550 LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
1551
1552 /* Calculate:
1553 * (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
1554 * Use the right-hand side, which the LLVM backend can convert to V_BFI.
1555 */
1556 result = LLVMBuildXor(ctx->builder, bfi_args[2],
1557 LLVMBuildAnd(ctx->builder, bfi_args[0],
1558 LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
1559
1560 result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
1561 return result;
1562 }
1563
1564 static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
1565 LLVMValueRef src0)
1566 {
1567 LLVMValueRef comp[2];
1568
1569 src0 = ac_to_float(ctx, src0);
1570 comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
1571 comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
1572
1573 return ac_build_cvt_pkrtz_f16(ctx, comp);
1574 }
1575
1576 static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
1577 LLVMValueRef src0)
1578 {
1579 LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
1580 LLVMValueRef temps[2], result, val;
1581 int i;
1582
1583 for (i = 0; i < 2; i++) {
1584 val = i == 1 ? LLVMBuildLShr(ctx->builder, src0, const16, "") : src0;
1585 val = LLVMBuildTrunc(ctx->builder, val, ctx->i16, "");
1586 val = LLVMBuildBitCast(ctx->builder, val, ctx->f16, "");
1587 temps[i] = LLVMBuildFPExt(ctx->builder, val, ctx->f32, "");
1588 }
1589
1590 result = LLVMBuildInsertElement(ctx->builder, LLVMGetUndef(ctx->v2f32), temps[0],
1591 ctx->i32_0, "");
1592 result = LLVMBuildInsertElement(ctx->builder, result, temps[1],
1593 ctx->i32_1, "");
1594 return result;
1595 }
1596
1597 static LLVMValueRef emit_ddxy(struct ac_nir_context *ctx,
1598 nir_op op,
1599 LLVMValueRef src0)
1600 {
1601 unsigned mask;
1602 int idx;
1603 LLVMValueRef result;
1604
1605 if (op == nir_op_fddx_fine || op == nir_op_fddx)
1606 mask = AC_TID_MASK_LEFT;
1607 else if (op == nir_op_fddy_fine || op == nir_op_fddy)
1608 mask = AC_TID_MASK_TOP;
1609 else
1610 mask = AC_TID_MASK_TOP_LEFT;
1611
1612 /* for DDX we want to next X pixel, DDY next Y pixel. */
1613 if (op == nir_op_fddx_fine ||
1614 op == nir_op_fddx_coarse ||
1615 op == nir_op_fddx)
1616 idx = 1;
1617 else
1618 idx = 2;
1619
1620 result = ac_build_ddxy(&ctx->ac, mask, idx, src0);
1621 return result;
1622 }
1623
1624 /*
1625 * this takes an I,J coordinate pair,
1626 * and works out the X and Y derivatives.
1627 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
1628 */
1629 static LLVMValueRef emit_ddxy_interp(
1630 struct ac_nir_context *ctx,
1631 LLVMValueRef interp_ij)
1632 {
1633 LLVMValueRef result[4], a;
1634 unsigned i;
1635
1636 for (i = 0; i < 2; i++) {
1637 a = LLVMBuildExtractElement(ctx->ac.builder, interp_ij,
1638 LLVMConstInt(ctx->ac.i32, i, false), "");
1639 result[i] = emit_ddxy(ctx, nir_op_fddx, a);
1640 result[2+i] = emit_ddxy(ctx, nir_op_fddy, a);
1641 }
1642 return ac_build_gather_values(&ctx->ac, result, 4);
1643 }
1644
1645 static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
1646 {
1647 LLVMValueRef src[4], result = NULL;
1648 unsigned num_components = instr->dest.dest.ssa.num_components;
1649 unsigned src_components;
1650 LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa);
1651
1652 assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src));
1653 switch (instr->op) {
1654 case nir_op_vec2:
1655 case nir_op_vec3:
1656 case nir_op_vec4:
1657 src_components = 1;
1658 break;
1659 case nir_op_pack_half_2x16:
1660 src_components = 2;
1661 break;
1662 case nir_op_unpack_half_2x16:
1663 src_components = 1;
1664 break;
1665 default:
1666 src_components = num_components;
1667 break;
1668 }
1669 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1670 src[i] = get_alu_src(ctx, instr->src[i], src_components);
1671
1672 switch (instr->op) {
1673 case nir_op_fmov:
1674 case nir_op_imov:
1675 result = src[0];
1676 break;
1677 case nir_op_fneg:
1678 src[0] = ac_to_float(&ctx->ac, src[0]);
1679 result = LLVMBuildFNeg(ctx->ac.builder, src[0], "");
1680 break;
1681 case nir_op_ineg:
1682 result = LLVMBuildNeg(ctx->ac.builder, src[0], "");
1683 break;
1684 case nir_op_inot:
1685 result = LLVMBuildNot(ctx->ac.builder, src[0], "");
1686 break;
1687 case nir_op_iadd:
1688 result = LLVMBuildAdd(ctx->ac.builder, src[0], src[1], "");
1689 break;
1690 case nir_op_fadd:
1691 src[0] = ac_to_float(&ctx->ac, src[0]);
1692 src[1] = ac_to_float(&ctx->ac, src[1]);
1693 result = LLVMBuildFAdd(ctx->ac.builder, src[0], src[1], "");
1694 break;
1695 case nir_op_fsub:
1696 src[0] = ac_to_float(&ctx->ac, src[0]);
1697 src[1] = ac_to_float(&ctx->ac, src[1]);
1698 result = LLVMBuildFSub(ctx->ac.builder, src[0], src[1], "");
1699 break;
1700 case nir_op_isub:
1701 result = LLVMBuildSub(ctx->ac.builder, src[0], src[1], "");
1702 break;
1703 case nir_op_imul:
1704 result = LLVMBuildMul(ctx->ac.builder, src[0], src[1], "");
1705 break;
1706 case nir_op_imod:
1707 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1708 break;
1709 case nir_op_umod:
1710 result = LLVMBuildURem(ctx->ac.builder, src[0], src[1], "");
1711 break;
1712 case nir_op_fmod:
1713 src[0] = ac_to_float(&ctx->ac, src[0]);
1714 src[1] = ac_to_float(&ctx->ac, src[1]);
1715 result = ac_build_fdiv(&ctx->ac, src[0], src[1]);
1716 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1717 ac_to_float_type(&ctx->ac, def_type), result);
1718 result = LLVMBuildFMul(ctx->ac.builder, src[1] , result, "");
1719 result = LLVMBuildFSub(ctx->ac.builder, src[0], result, "");
1720 break;
1721 case nir_op_frem:
1722 src[0] = ac_to_float(&ctx->ac, src[0]);
1723 src[1] = ac_to_float(&ctx->ac, src[1]);
1724 result = LLVMBuildFRem(ctx->ac.builder, src[0], src[1], "");
1725 break;
1726 case nir_op_irem:
1727 result = LLVMBuildSRem(ctx->ac.builder, src[0], src[1], "");
1728 break;
1729 case nir_op_idiv:
1730 result = LLVMBuildSDiv(ctx->ac.builder, src[0], src[1], "");
1731 break;
1732 case nir_op_udiv:
1733 result = LLVMBuildUDiv(ctx->ac.builder, src[0], src[1], "");
1734 break;
1735 case nir_op_fmul:
1736 src[0] = ac_to_float(&ctx->ac, src[0]);
1737 src[1] = ac_to_float(&ctx->ac, src[1]);
1738 result = LLVMBuildFMul(ctx->ac.builder, src[0], src[1], "");
1739 break;
1740 case nir_op_frcp:
1741 src[0] = ac_to_float(&ctx->ac, src[0]);
1742 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1743 src[0]);
1744 break;
1745 case nir_op_iand:
1746 result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");
1747 break;
1748 case nir_op_ior:
1749 result = LLVMBuildOr(ctx->ac.builder, src[0], src[1], "");
1750 break;
1751 case nir_op_ixor:
1752 result = LLVMBuildXor(ctx->ac.builder, src[0], src[1], "");
1753 break;
1754 case nir_op_ishl:
1755 result = LLVMBuildShl(ctx->ac.builder, src[0],
1756 LLVMBuildZExt(ctx->ac.builder, src[1],
1757 LLVMTypeOf(src[0]), ""),
1758 "");
1759 break;
1760 case nir_op_ishr:
1761 result = LLVMBuildAShr(ctx->ac.builder, src[0],
1762 LLVMBuildZExt(ctx->ac.builder, src[1],
1763 LLVMTypeOf(src[0]), ""),
1764 "");
1765 break;
1766 case nir_op_ushr:
1767 result = LLVMBuildLShr(ctx->ac.builder, src[0],
1768 LLVMBuildZExt(ctx->ac.builder, src[1],
1769 LLVMTypeOf(src[0]), ""),
1770 "");
1771 break;
1772 case nir_op_ilt:
1773 result = emit_int_cmp(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1774 break;
1775 case nir_op_ine:
1776 result = emit_int_cmp(&ctx->ac, LLVMIntNE, src[0], src[1]);
1777 break;
1778 case nir_op_ieq:
1779 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, src[0], src[1]);
1780 break;
1781 case nir_op_ige:
1782 result = emit_int_cmp(&ctx->ac, LLVMIntSGE, src[0], src[1]);
1783 break;
1784 case nir_op_ult:
1785 result = emit_int_cmp(&ctx->ac, LLVMIntULT, src[0], src[1]);
1786 break;
1787 case nir_op_uge:
1788 result = emit_int_cmp(&ctx->ac, LLVMIntUGE, src[0], src[1]);
1789 break;
1790 case nir_op_feq:
1791 result = emit_float_cmp(&ctx->ac, LLVMRealUEQ, src[0], src[1]);
1792 break;
1793 case nir_op_fne:
1794 result = emit_float_cmp(&ctx->ac, LLVMRealUNE, src[0], src[1]);
1795 break;
1796 case nir_op_flt:
1797 result = emit_float_cmp(&ctx->ac, LLVMRealULT, src[0], src[1]);
1798 break;
1799 case nir_op_fge:
1800 result = emit_float_cmp(&ctx->ac, LLVMRealUGE, src[0], src[1]);
1801 break;
1802 case nir_op_fabs:
1803 result = emit_intrin_1f_param(&ctx->ac, "llvm.fabs",
1804 ac_to_float_type(&ctx->ac, def_type), src[0]);
1805 break;
1806 case nir_op_iabs:
1807 result = emit_iabs(&ctx->ac, src[0]);
1808 break;
1809 case nir_op_imax:
1810 result = emit_minmax_int(&ctx->ac, LLVMIntSGT, src[0], src[1]);
1811 break;
1812 case nir_op_imin:
1813 result = emit_minmax_int(&ctx->ac, LLVMIntSLT, src[0], src[1]);
1814 break;
1815 case nir_op_umax:
1816 result = emit_minmax_int(&ctx->ac, LLVMIntUGT, src[0], src[1]);
1817 break;
1818 case nir_op_umin:
1819 result = emit_minmax_int(&ctx->ac, LLVMIntULT, src[0], src[1]);
1820 break;
1821 case nir_op_isign:
1822 result = emit_isign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1823 break;
1824 case nir_op_fsign:
1825 src[0] = ac_to_float(&ctx->ac, src[0]);
1826 result = emit_fsign(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1827 break;
1828 case nir_op_ffloor:
1829 result = emit_intrin_1f_param(&ctx->ac, "llvm.floor",
1830 ac_to_float_type(&ctx->ac, def_type), src[0]);
1831 break;
1832 case nir_op_ftrunc:
1833 result = emit_intrin_1f_param(&ctx->ac, "llvm.trunc",
1834 ac_to_float_type(&ctx->ac, def_type), src[0]);
1835 break;
1836 case nir_op_fceil:
1837 result = emit_intrin_1f_param(&ctx->ac, "llvm.ceil",
1838 ac_to_float_type(&ctx->ac, def_type), src[0]);
1839 break;
1840 case nir_op_fround_even:
1841 result = emit_intrin_1f_param(&ctx->ac, "llvm.rint",
1842 ac_to_float_type(&ctx->ac, def_type),src[0]);
1843 break;
1844 case nir_op_ffract:
1845 result = emit_ffract(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
1846 break;
1847 case nir_op_fsin:
1848 result = emit_intrin_1f_param(&ctx->ac, "llvm.sin",
1849 ac_to_float_type(&ctx->ac, def_type), src[0]);
1850 break;
1851 case nir_op_fcos:
1852 result = emit_intrin_1f_param(&ctx->ac, "llvm.cos",
1853 ac_to_float_type(&ctx->ac, def_type), src[0]);
1854 break;
1855 case nir_op_fsqrt:
1856 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1857 ac_to_float_type(&ctx->ac, def_type), src[0]);
1858 break;
1859 case nir_op_fexp2:
1860 result = emit_intrin_1f_param(&ctx->ac, "llvm.exp2",
1861 ac_to_float_type(&ctx->ac, def_type), src[0]);
1862 break;
1863 case nir_op_flog2:
1864 result = emit_intrin_1f_param(&ctx->ac, "llvm.log2",
1865 ac_to_float_type(&ctx->ac, def_type), src[0]);
1866 break;
1867 case nir_op_frsq:
1868 result = emit_intrin_1f_param(&ctx->ac, "llvm.sqrt",
1869 ac_to_float_type(&ctx->ac, def_type), src[0]);
1870 result = ac_build_fdiv(&ctx->ac, instr->dest.dest.ssa.bit_size == 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
1871 result);
1872 break;
1873 case nir_op_fpow:
1874 result = emit_intrin_2f_param(&ctx->ac, "llvm.pow",
1875 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1876 break;
1877 case nir_op_fmax:
1878 result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum",
1879 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1880 if (ctx->ac.chip_class < GFX9 &&
1881 instr->dest.dest.ssa.bit_size == 32) {
1882 /* Only pre-GFX9 chips do not flush denorms. */
1883 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1884 ac_to_float_type(&ctx->ac, def_type),
1885 result);
1886 }
1887 break;
1888 case nir_op_fmin:
1889 result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum",
1890 ac_to_float_type(&ctx->ac, def_type), src[0], src[1]);
1891 if (ctx->ac.chip_class < GFX9 &&
1892 instr->dest.dest.ssa.bit_size == 32) {
1893 /* Only pre-GFX9 chips do not flush denorms. */
1894 result = emit_intrin_1f_param(&ctx->ac, "llvm.canonicalize",
1895 ac_to_float_type(&ctx->ac, def_type),
1896 result);
1897 }
1898 break;
1899 case nir_op_ffma:
1900 result = emit_intrin_3f_param(&ctx->ac, "llvm.fmuladd",
1901 ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]);
1902 break;
1903 case nir_op_ibitfield_extract:
1904 result = emit_bitfield_extract(&ctx->ac, true, src);
1905 break;
1906 case nir_op_ubitfield_extract:
1907 result = emit_bitfield_extract(&ctx->ac, false, src);
1908 break;
1909 case nir_op_bitfield_insert:
1910 result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
1911 break;
1912 case nir_op_bitfield_reverse:
1913 result = ac_build_intrinsic(&ctx->ac, "llvm.bitreverse.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1914 break;
1915 case nir_op_bit_count:
1916 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) == 32)
1917 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32", ctx->ac.i32, src, 1, AC_FUNC_ATTR_READNONE);
1918 else {
1919 result = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i64", ctx->ac.i64, src, 1, AC_FUNC_ATTR_READNONE);
1920 result = LLVMBuildTrunc(ctx->ac.builder, result, ctx->ac.i32, "");
1921 }
1922 break;
1923 case nir_op_vec2:
1924 case nir_op_vec3:
1925 case nir_op_vec4:
1926 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1927 src[i] = ac_to_integer(&ctx->ac, src[i]);
1928 result = ac_build_gather_values(&ctx->ac, src, num_components);
1929 break;
1930 case nir_op_f2i32:
1931 case nir_op_f2i64:
1932 src[0] = ac_to_float(&ctx->ac, src[0]);
1933 result = LLVMBuildFPToSI(ctx->ac.builder, src[0], def_type, "");
1934 break;
1935 case nir_op_f2u32:
1936 case nir_op_f2u64:
1937 src[0] = ac_to_float(&ctx->ac, src[0]);
1938 result = LLVMBuildFPToUI(ctx->ac.builder, src[0], def_type, "");
1939 break;
1940 case nir_op_i2f32:
1941 case nir_op_i2f64:
1942 src[0] = ac_to_integer(&ctx->ac, src[0]);
1943 result = LLVMBuildSIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1944 break;
1945 case nir_op_u2f32:
1946 case nir_op_u2f64:
1947 src[0] = ac_to_integer(&ctx->ac, src[0]);
1948 result = LLVMBuildUIToFP(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1949 break;
1950 case nir_op_f2f64:
1951 src[0] = ac_to_float(&ctx->ac, src[0]);
1952 result = LLVMBuildFPExt(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1953 break;
1954 case nir_op_f2f32:
1955 src[0] = ac_to_float(&ctx->ac, src[0]);
1956 result = LLVMBuildFPTrunc(ctx->ac.builder, src[0], ac_to_float_type(&ctx->ac, def_type), "");
1957 break;
1958 case nir_op_u2u32:
1959 case nir_op_u2u64:
1960 src[0] = ac_to_integer(&ctx->ac, src[0]);
1961 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1962 result = LLVMBuildZExt(ctx->ac.builder, src[0], def_type, "");
1963 else
1964 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1965 break;
1966 case nir_op_i2i32:
1967 case nir_op_i2i64:
1968 src[0] = ac_to_integer(&ctx->ac, src[0]);
1969 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src[0])) < ac_get_elem_bits(&ctx->ac, def_type))
1970 result = LLVMBuildSExt(ctx->ac.builder, src[0], def_type, "");
1971 else
1972 result = LLVMBuildTrunc(ctx->ac.builder, src[0], def_type, "");
1973 break;
1974 case nir_op_bcsel:
1975 result = emit_bcsel(&ctx->ac, src[0], src[1], src[2]);
1976 break;
1977 case nir_op_find_lsb:
1978 src[0] = ac_to_integer(&ctx->ac, src[0]);
1979 result = ac_find_lsb(&ctx->ac, ctx->ac.i32, src[0]);
1980 break;
1981 case nir_op_ufind_msb:
1982 src[0] = ac_to_integer(&ctx->ac, src[0]);
1983 result = ac_build_umsb(&ctx->ac, src[0], ctx->ac.i32);
1984 break;
1985 case nir_op_ifind_msb:
1986 src[0] = ac_to_integer(&ctx->ac, src[0]);
1987 result = ac_build_imsb(&ctx->ac, src[0], ctx->ac.i32);
1988 break;
1989 case nir_op_uadd_carry:
1990 src[0] = ac_to_integer(&ctx->ac, src[0]);
1991 src[1] = ac_to_integer(&ctx->ac, src[1]);
1992 result = emit_uint_carry(&ctx->ac, "llvm.uadd.with.overflow.i32", src[0], src[1]);
1993 break;
1994 case nir_op_usub_borrow:
1995 src[0] = ac_to_integer(&ctx->ac, src[0]);
1996 src[1] = ac_to_integer(&ctx->ac, src[1]);
1997 result = emit_uint_carry(&ctx->ac, "llvm.usub.with.overflow.i32", src[0], src[1]);
1998 break;
1999 case nir_op_b2f:
2000 result = emit_b2f(&ctx->ac, src[0]);
2001 break;
2002 case nir_op_f2b:
2003 result = emit_f2b(&ctx->ac, src[0]);
2004 break;
2005 case nir_op_b2i:
2006 result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size);
2007 break;
2008 case nir_op_i2b:
2009 src[0] = ac_to_integer(&ctx->ac, src[0]);
2010 result = emit_i2b(&ctx->ac, src[0]);
2011 break;
2012 case nir_op_fquantize2f16:
2013 result = emit_f2f16(&ctx->ac, src[0]);
2014 break;
2015 case nir_op_umul_high:
2016 src[0] = ac_to_integer(&ctx->ac, src[0]);
2017 src[1] = ac_to_integer(&ctx->ac, src[1]);
2018 result = emit_umul_high(&ctx->ac, src[0], src[1]);
2019 break;
2020 case nir_op_imul_high:
2021 src[0] = ac_to_integer(&ctx->ac, src[0]);
2022 src[1] = ac_to_integer(&ctx->ac, src[1]);
2023 result = emit_imul_high(&ctx->ac, src[0], src[1]);
2024 break;
2025 case nir_op_pack_half_2x16:
2026 result = emit_pack_half_2x16(&ctx->ac, src[0]);
2027 break;
2028 case nir_op_unpack_half_2x16:
2029 result = emit_unpack_half_2x16(&ctx->ac, src[0]);
2030 break;
2031 case nir_op_fddx:
2032 case nir_op_fddy:
2033 case nir_op_fddx_fine:
2034 case nir_op_fddy_fine:
2035 case nir_op_fddx_coarse:
2036 case nir_op_fddy_coarse:
2037 result = emit_ddxy(ctx, instr->op, src[0]);
2038 break;
2039
2040 case nir_op_unpack_64_2x32_split_x: {
2041 assert(ac_get_llvm_num_components(src[0]) == 1);
2042 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2043 ctx->ac.v2i32,
2044 "");
2045 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2046 ctx->ac.i32_0, "");
2047 break;
2048 }
2049
2050 case nir_op_unpack_64_2x32_split_y: {
2051 assert(ac_get_llvm_num_components(src[0]) == 1);
2052 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, src[0],
2053 ctx->ac.v2i32,
2054 "");
2055 result = LLVMBuildExtractElement(ctx->ac.builder, tmp,
2056 ctx->ac.i32_1, "");
2057 break;
2058 }
2059
2060 case nir_op_pack_64_2x32_split: {
2061 LLVMValueRef tmp = LLVMGetUndef(ctx->ac.v2i32);
2062 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2063 src[0], ctx->ac.i32_0, "");
2064 tmp = LLVMBuildInsertElement(ctx->ac.builder, tmp,
2065 src[1], ctx->ac.i32_1, "");
2066 result = LLVMBuildBitCast(ctx->ac.builder, tmp, ctx->ac.i64, "");
2067 break;
2068 }
2069
2070 default:
2071 fprintf(stderr, "Unknown NIR alu instr: ");
2072 nir_print_instr(&instr->instr, stderr);
2073 fprintf(stderr, "\n");
2074 abort();
2075 }
2076
2077 if (result) {
2078 assert(instr->dest.dest.is_ssa);
2079 result = ac_to_integer(&ctx->ac, result);
2080 _mesa_hash_table_insert(ctx->defs, &instr->dest.dest.ssa,
2081 result);
2082 }
2083 }
2084
2085 static void visit_load_const(struct ac_nir_context *ctx,
2086 const nir_load_const_instr *instr)
2087 {
2088 LLVMValueRef values[4], value = NULL;
2089 LLVMTypeRef element_type =
2090 LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
2091
2092 for (unsigned i = 0; i < instr->def.num_components; ++i) {
2093 switch (instr->def.bit_size) {
2094 case 32:
2095 values[i] = LLVMConstInt(element_type,
2096 instr->value.u32[i], false);
2097 break;
2098 case 64:
2099 values[i] = LLVMConstInt(element_type,
2100 instr->value.u64[i], false);
2101 break;
2102 default:
2103 fprintf(stderr,
2104 "unsupported nir load_const bit_size: %d\n",
2105 instr->def.bit_size);
2106 abort();
2107 }
2108 }
2109 if (instr->def.num_components > 1) {
2110 value = LLVMConstVector(values, instr->def.num_components);
2111 } else
2112 value = values[0];
2113
2114 _mesa_hash_table_insert(ctx->defs, &instr->def, value);
2115 }
2116
2117 static LLVMValueRef cast_ptr(struct ac_llvm_context *ctx, LLVMValueRef ptr,
2118 LLVMTypeRef type)
2119 {
2120 int addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
2121 return LLVMBuildBitCast(ctx->builder, ptr,
2122 LLVMPointerType(type, addr_space), "");
2123 }
2124
2125 static LLVMValueRef
2126 get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef descriptor, bool in_elements)
2127 {
2128 LLVMValueRef size =
2129 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2130 LLVMConstInt(ctx->ac.i32, 2, false), "");
2131
2132 /* VI only */
2133 if (ctx->ac.chip_class == VI && in_elements) {
2134 /* On VI, the descriptor contains the size in bytes,
2135 * but TXQ must return the size in elements.
2136 * The stride is always non-zero for resources using TXQ.
2137 */
2138 LLVMValueRef stride =
2139 LLVMBuildExtractElement(ctx->ac.builder, descriptor,
2140 ctx->ac.i32_1, "");
2141 stride = LLVMBuildLShr(ctx->ac.builder, stride,
2142 LLVMConstInt(ctx->ac.i32, 16, false), "");
2143 stride = LLVMBuildAnd(ctx->ac.builder, stride,
2144 LLVMConstInt(ctx->ac.i32, 0x3fff, false), "");
2145
2146 size = LLVMBuildUDiv(ctx->ac.builder, size, stride, "");
2147 }
2148 return size;
2149 }
2150
2151 /**
2152 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
2153 * intrinsic names).
2154 */
2155 static void build_int_type_name(
2156 LLVMTypeRef type,
2157 char *buf, unsigned bufsize)
2158 {
2159 assert(bufsize >= 6);
2160
2161 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
2162 snprintf(buf, bufsize, "v%ui32",
2163 LLVMGetVectorSize(type));
2164 else
2165 strcpy(buf, "i32");
2166 }
2167
2168 static LLVMValueRef radv_lower_gather4_integer(struct ac_llvm_context *ctx,
2169 struct ac_image_args *args,
2170 const nir_tex_instr *instr)
2171 {
2172 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2173 LLVMValueRef coord = args->addr;
2174 LLVMValueRef half_texel[2];
2175 LLVMValueRef compare_cube_wa = NULL;
2176 LLVMValueRef result;
2177 int c;
2178 unsigned coord_vgpr_index = (unsigned)args->offset + (unsigned)args->compare;
2179
2180 //TODO Rect
2181 {
2182 struct ac_image_args txq_args = { 0 };
2183
2184 txq_args.da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
2185 txq_args.opcode = ac_image_get_resinfo;
2186 txq_args.dmask = 0xf;
2187 txq_args.addr = ctx->i32_0;
2188 txq_args.resource = args->resource;
2189 LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
2190
2191 for (c = 0; c < 2; c++) {
2192 half_texel[c] = LLVMBuildExtractElement(ctx->builder, size,
2193 LLVMConstInt(ctx->i32, c, false), "");
2194 half_texel[c] = LLVMBuildUIToFP(ctx->builder, half_texel[c], ctx->f32, "");
2195 half_texel[c] = ac_build_fdiv(ctx, ctx->f32_1, half_texel[c]);
2196 half_texel[c] = LLVMBuildFMul(ctx->builder, half_texel[c],
2197 LLVMConstReal(ctx->f32, -0.5), "");
2198 }
2199 }
2200
2201 LLVMValueRef orig_coords = args->addr;
2202
2203 for (c = 0; c < 2; c++) {
2204 LLVMValueRef tmp;
2205 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
2206 tmp = LLVMBuildExtractElement(ctx->builder, coord, index, "");
2207 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2208 tmp = LLVMBuildFAdd(ctx->builder, tmp, half_texel[c], "");
2209 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2210 coord = LLVMBuildInsertElement(ctx->builder, coord, tmp, index, "");
2211 }
2212
2213
2214 /*
2215 * Apparantly cube has issue with integer types that the workaround doesn't solve,
2216 * so this tests if the format is 8_8_8_8 and an integer type do an alternate
2217 * workaround by sampling using a scaled type and converting.
2218 * This is taken from amdgpu-pro shaders.
2219 */
2220 /* NOTE this produces some ugly code compared to amdgpu-pro,
2221 * LLVM ends up dumping SGPRs into VGPRs to deal with the compare/select,
2222 * and then reads them back. -pro generates two selects,
2223 * one s_cmp for the descriptor rewriting
2224 * one v_cmp for the coordinate and result changes.
2225 */
2226 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2227 LLVMValueRef tmp, tmp2;
2228
2229 /* workaround 8/8/8/8 uint/sint cube gather bug */
2230 /* first detect it then change to a scaled read and f2i */
2231 tmp = LLVMBuildExtractElement(ctx->builder, args->resource, ctx->i32_1, "");
2232 tmp2 = tmp;
2233
2234 /* extract the DATA_FORMAT */
2235 tmp = ac_build_bfe(ctx, tmp, LLVMConstInt(ctx->i32, 20, false),
2236 LLVMConstInt(ctx->i32, 6, false), false);
2237
2238 /* is the DATA_FORMAT == 8_8_8_8 */
2239 compare_cube_wa = LLVMBuildICmp(ctx->builder, LLVMIntEQ, tmp, LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false), "");
2240
2241 if (stype == GLSL_TYPE_UINT)
2242 /* Create a NUM FORMAT - 0x2 or 0x4 - USCALED or UINT */
2243 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0x8000000, false),
2244 LLVMConstInt(ctx->i32, 0x10000000, false), "");
2245 else
2246 /* Create a NUM FORMAT - 0x3 or 0x5 - SSCALED or SINT */
2247 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, LLVMConstInt(ctx->i32, 0xc000000, false),
2248 LLVMConstInt(ctx->i32, 0x14000000, false), "");
2249
2250 /* replace the NUM FORMAT in the descriptor */
2251 tmp2 = LLVMBuildAnd(ctx->builder, tmp2, LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false), "");
2252 tmp2 = LLVMBuildOr(ctx->builder, tmp2, tmp, "");
2253
2254 args->resource = LLVMBuildInsertElement(ctx->builder, args->resource, tmp2, ctx->i32_1, "");
2255
2256 /* don't modify the coordinates for this case */
2257 coord = LLVMBuildSelect(ctx->builder, compare_cube_wa, orig_coords, coord, "");
2258 }
2259 args->addr = coord;
2260 result = ac_build_image_opcode(ctx, args);
2261
2262 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
2263 LLVMValueRef tmp, tmp2;
2264
2265 /* if the cube workaround is in place, f2i the result. */
2266 for (c = 0; c < 4; c++) {
2267 tmp = LLVMBuildExtractElement(ctx->builder, result, LLVMConstInt(ctx->i32, c, false), "");
2268 if (stype == GLSL_TYPE_UINT)
2269 tmp2 = LLVMBuildFPToUI(ctx->builder, tmp, ctx->i32, "");
2270 else
2271 tmp2 = LLVMBuildFPToSI(ctx->builder, tmp, ctx->i32, "");
2272 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->i32, "");
2273 tmp2 = LLVMBuildBitCast(ctx->builder, tmp2, ctx->i32, "");
2274 tmp = LLVMBuildSelect(ctx->builder, compare_cube_wa, tmp2, tmp, "");
2275 tmp = LLVMBuildBitCast(ctx->builder, tmp, ctx->f32, "");
2276 result = LLVMBuildInsertElement(ctx->builder, result, tmp, LLVMConstInt(ctx->i32, c, false), "");
2277 }
2278 }
2279 return result;
2280 }
2281
2282 static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx,
2283 const nir_tex_instr *instr,
2284 bool lod_is_zero,
2285 struct ac_image_args *args)
2286 {
2287 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
2288 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
2289
2290 return ac_build_buffer_load_format(&ctx->ac,
2291 args->resource,
2292 args->addr,
2293 ctx->ac.i32_0,
2294 util_last_bit(mask),
2295 false, true);
2296 }
2297
2298 args->opcode = ac_image_sample;
2299 args->compare = instr->is_shadow;
2300
2301 switch (instr->op) {
2302 case nir_texop_txf:
2303 case nir_texop_txf_ms:
2304 case nir_texop_samples_identical:
2305 args->opcode = lod_is_zero ||
2306 instr->sampler_dim == GLSL_SAMPLER_DIM_MS ?
2307 ac_image_load : ac_image_load_mip;
2308 args->compare = false;
2309 args->offset = false;
2310 break;
2311 case nir_texop_txb:
2312 args->bias = true;
2313 break;
2314 case nir_texop_txl:
2315 if (lod_is_zero)
2316 args->level_zero = true;
2317 else
2318 args->lod = true;
2319 break;
2320 case nir_texop_txs:
2321 case nir_texop_query_levels:
2322 args->opcode = ac_image_get_resinfo;
2323 break;
2324 case nir_texop_tex:
2325 if (ctx->stage != MESA_SHADER_FRAGMENT)
2326 args->level_zero = true;
2327 break;
2328 case nir_texop_txd:
2329 args->deriv = true;
2330 break;
2331 case nir_texop_tg4:
2332 args->opcode = ac_image_gather4;
2333 args->level_zero = true;
2334 break;
2335 case nir_texop_lod:
2336 args->opcode = ac_image_get_lod;
2337 args->compare = false;
2338 args->offset = false;
2339 break;
2340 default:
2341 break;
2342 }
2343
2344 if (instr->op == nir_texop_tg4 && ctx->ac.chip_class <= VI) {
2345 enum glsl_base_type stype = glsl_get_sampler_result_type(instr->texture->var->type);
2346 if (stype == GLSL_TYPE_UINT || stype == GLSL_TYPE_INT) {
2347 return radv_lower_gather4_integer(&ctx->ac, args, instr);
2348 }
2349 }
2350 return ac_build_image_opcode(&ctx->ac, args);
2351 }
2352
2353 static LLVMValueRef
2354 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
2355 unsigned desc_set, unsigned binding)
2356 {
2357 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2358 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
2359 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
2360 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
2361 unsigned base_offset = layout->binding[binding].offset;
2362 LLVMValueRef offset, stride;
2363
2364 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
2365 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
2366 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
2367 layout->binding[binding].dynamic_offset_offset;
2368 desc_ptr = ctx->abi.push_constants;
2369 base_offset = pipeline_layout->push_constant_size + 16 * idx;
2370 stride = LLVMConstInt(ctx->ac.i32, 16, false);
2371 } else
2372 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
2373
2374 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
2375 index = LLVMBuildMul(ctx->ac.builder, index, stride, "");
2376 offset = LLVMBuildAdd(ctx->ac.builder, offset, index, "");
2377
2378 desc_ptr = ac_build_gep0(&ctx->ac, desc_ptr, offset);
2379 desc_ptr = cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
2380 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2381
2382 return desc_ptr;
2383 }
2384
2385 static LLVMValueRef visit_vulkan_resource_reindex(struct ac_nir_context *ctx,
2386 nir_intrinsic_instr *instr)
2387 {
2388 LLVMValueRef ptr = get_src(ctx, instr->src[0]);
2389 LLVMValueRef index = get_src(ctx, instr->src[1]);
2390
2391 LLVMValueRef result = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
2392 LLVMSetMetadata(result, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
2393 return result;
2394 }
2395
2396 static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
2397 nir_intrinsic_instr *instr)
2398 {
2399 LLVMValueRef ptr, addr;
2400
2401 addr = LLVMConstInt(ctx->ac.i32, nir_intrinsic_base(instr), 0);
2402 addr = LLVMBuildAdd(ctx->ac.builder, addr,
2403 get_src(ctx, instr->src[0]), "");
2404
2405 ptr = ac_build_gep0(&ctx->ac, ctx->abi->push_constants, addr);
2406 ptr = cast_ptr(&ctx->ac, ptr, get_def_type(ctx, &instr->dest.ssa));
2407
2408 return LLVMBuildLoad(ctx->ac.builder, ptr, "");
2409 }
2410
2411 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
2412 const nir_intrinsic_instr *instr)
2413 {
2414 LLVMValueRef index = get_src(ctx, instr->src[0]);
2415
2416 return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, false), false);
2417 }
2418
2419 static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
2420 {
2421 uint32_t new_mask = 0;
2422 for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
2423 if (mask & (1u << i))
2424 new_mask |= ((1u << multiplier) - 1u) << (i * multiplier);
2425 return new_mask;
2426 }
2427
2428 static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx, LLVMValueRef src,
2429 unsigned start, unsigned count)
2430 {
2431 LLVMTypeRef type = LLVMTypeOf(src);
2432
2433 if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
2434 assert(start == 0);
2435 assert(count == 1);
2436 return src;
2437 }
2438
2439 unsigned src_elements = LLVMGetVectorSize(type);
2440 assert(start < src_elements);
2441 assert(start + count <= src_elements);
2442
2443 if (start == 0 && count == src_elements)
2444 return src;
2445
2446 if (count == 1)
2447 return LLVMBuildExtractElement(ctx->builder, src, LLVMConstInt(ctx->i32, start, false), "");
2448
2449 assert(count <= 8);
2450 LLVMValueRef indices[8];
2451 for (unsigned i = 0; i < count; ++i)
2452 indices[i] = LLVMConstInt(ctx->i32, start + i, false);
2453
2454 LLVMValueRef swizzle = LLVMConstVector(indices, count);
2455 return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
2456 }
2457
2458 static void visit_store_ssbo(struct ac_nir_context *ctx,
2459 nir_intrinsic_instr *instr)
2460 {
2461 const char *store_name;
2462 LLVMValueRef src_data = get_src(ctx, instr->src[0]);
2463 LLVMTypeRef data_type = ctx->ac.f32;
2464 int elem_size_mult = ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src_data)) / 32;
2465 int components_32bit = elem_size_mult * instr->num_components;
2466 unsigned writemask = nir_intrinsic_write_mask(instr);
2467 LLVMValueRef base_data, base_offset;
2468 LLVMValueRef params[6];
2469
2470 params[1] = ctx->abi->load_ssbo(ctx->abi,
2471 get_src(ctx, instr->src[1]), true);
2472 params[2] = ctx->ac.i32_0; /* vindex */
2473 params[4] = ctx->ac.i1false; /* glc */
2474 params[5] = ctx->ac.i1false; /* slc */
2475
2476 if (components_32bit > 1)
2477 data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
2478
2479 writemask = widen_mask(writemask, elem_size_mult);
2480
2481 base_data = ac_to_float(&ctx->ac, src_data);
2482 base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
2483 base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
2484 data_type, "");
2485 base_offset = get_src(ctx, instr->src[2]); /* voffset */
2486 while (writemask) {
2487 int start, count;
2488 LLVMValueRef data;
2489 LLVMValueRef offset;
2490
2491 u_bit_scan_consecutive_range(&writemask, &start, &count);
2492
2493 /* Due to an LLVM limitation, split 3-element writes
2494 * into a 2-element and a 1-element write. */
2495 if (count == 3) {
2496 writemask |= 1 << (start + 2);
2497 count = 2;
2498 }
2499
2500 if (count > 4) {
2501 writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
2502 count = 4;
2503 }
2504
2505 if (count == 4) {
2506 store_name = "llvm.amdgcn.buffer.store.v4f32";
2507 } else if (count == 2) {
2508 store_name = "llvm.amdgcn.buffer.store.v2f32";
2509
2510 } else {
2511 assert(count == 1);
2512 store_name = "llvm.amdgcn.buffer.store.f32";
2513 }
2514 data = extract_vector_range(&ctx->ac, base_data, start, count);
2515
2516 offset = base_offset;
2517 if (start != 0) {
2518 offset = LLVMBuildAdd(ctx->ac.builder, offset, LLVMConstInt(ctx->ac.i32, start * 4, false), "");
2519 }
2520 params[0] = data;
2521 params[3] = offset;
2522 ac_build_intrinsic(&ctx->ac, store_name,
2523 ctx->ac.voidt, params, 6, 0);
2524 }
2525 }
2526
2527 static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
2528 const nir_intrinsic_instr *instr)
2529 {
2530 const char *name;
2531 LLVMValueRef params[6];
2532 int arg_count = 0;
2533
2534 if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
2535 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[3]), 0);
2536 }
2537 params[arg_count++] = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[2]), 0);
2538 params[arg_count++] = ctx->abi->load_ssbo(ctx->abi,
2539 get_src(ctx, instr->src[0]),
2540 true);
2541 params[arg_count++] = ctx->ac.i32_0; /* vindex */
2542 params[arg_count++] = get_src(ctx, instr->src[1]); /* voffset */
2543 params[arg_count++] = LLVMConstInt(ctx->ac.i1, 0, false); /* slc */
2544
2545 switch (instr->intrinsic) {
2546 case nir_intrinsic_ssbo_atomic_add:
2547 name = "llvm.amdgcn.buffer.atomic.add";
2548 break;
2549 case nir_intrinsic_ssbo_atomic_imin:
2550 name = "llvm.amdgcn.buffer.atomic.smin";
2551 break;
2552 case nir_intrinsic_ssbo_atomic_umin:
2553 name = "llvm.amdgcn.buffer.atomic.umin";
2554 break;
2555 case nir_intrinsic_ssbo_atomic_imax:
2556 name = "llvm.amdgcn.buffer.atomic.smax";
2557 break;
2558 case nir_intrinsic_ssbo_atomic_umax:
2559 name = "llvm.amdgcn.buffer.atomic.umax";
2560 break;
2561 case nir_intrinsic_ssbo_atomic_and:
2562 name = "llvm.amdgcn.buffer.atomic.and";
2563 break;
2564 case nir_intrinsic_ssbo_atomic_or:
2565 name = "llvm.amdgcn.buffer.atomic.or";
2566 break;
2567 case nir_intrinsic_ssbo_atomic_xor:
2568 name = "llvm.amdgcn.buffer.atomic.xor";
2569 break;
2570 case nir_intrinsic_ssbo_atomic_exchange:
2571 name = "llvm.amdgcn.buffer.atomic.swap";
2572 break;
2573 case nir_intrinsic_ssbo_atomic_comp_swap:
2574 name = "llvm.amdgcn.buffer.atomic.cmpswap";
2575 break;
2576 default:
2577 abort();
2578 }
2579
2580 return ac_build_intrinsic(&ctx->ac, name, ctx->ac.i32, params, arg_count, 0);
2581 }
2582
2583 static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
2584 const nir_intrinsic_instr *instr)
2585 {
2586 LLVMValueRef results[2];
2587 int load_components;
2588 int num_components = instr->num_components;
2589 if (instr->dest.ssa.bit_size == 64)
2590 num_components *= 2;
2591
2592 for (int i = 0; i < num_components; i += load_components) {
2593 load_components = MIN2(num_components - i, 4);
2594 const char *load_name;
2595 LLVMTypeRef data_type = ctx->ac.f32;
2596 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, i * 4, false);
2597 offset = LLVMBuildAdd(ctx->ac.builder, get_src(ctx, instr->src[1]), offset, "");
2598
2599 if (load_components == 3)
2600 data_type = LLVMVectorType(ctx->ac.f32, 4);
2601 else if (load_components > 1)
2602 data_type = LLVMVectorType(ctx->ac.f32, load_components);
2603
2604 if (load_components >= 3)
2605 load_name = "llvm.amdgcn.buffer.load.v4f32";
2606 else if (load_components == 2)
2607 load_name = "llvm.amdgcn.buffer.load.v2f32";
2608 else if (load_components == 1)
2609 load_name = "llvm.amdgcn.buffer.load.f32";
2610 else
2611 unreachable("unhandled number of components");
2612
2613 LLVMValueRef params[] = {
2614 ctx->abi->load_ssbo(ctx->abi,
2615 get_src(ctx, instr->src[0]),
2616 false),
2617 ctx->ac.i32_0,
2618 offset,
2619 ctx->ac.i1false,
2620 ctx->ac.i1false,
2621 };
2622
2623 results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
2624 }
2625
2626 assume(results[0]);
2627 LLVMValueRef ret = results[0];
2628 if (num_components > 4 || num_components == 3) {
2629 LLVMValueRef masks[] = {
2630 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
2631 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
2632 LLVMConstInt(ctx->ac.i32, 4, false), LLVMConstInt(ctx->ac.i32, 5, false),
2633 LLVMConstInt(ctx->ac.i32, 6, false), LLVMConstInt(ctx->ac.i32, 7, false)
2634 };
2635
2636 LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
2637 ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
2638 results[num_components > 4 ? 1 : 0], swizzle, "");
2639 }
2640
2641 return LLVMBuildBitCast(ctx->ac.builder, ret,
2642 get_def_type(ctx, &instr->dest.ssa), "");
2643 }
2644
2645 static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
2646 const nir_intrinsic_instr *instr)
2647 {
2648 LLVMValueRef ret;
2649 LLVMValueRef rsrc = get_src(ctx, instr->src[0]);
2650 LLVMValueRef offset = get_src(ctx, instr->src[1]);
2651 int num_components = instr->num_components;
2652
2653 if (ctx->abi->load_ubo)
2654 rsrc = ctx->abi->load_ubo(ctx->abi, rsrc);
2655
2656 if (instr->dest.ssa.bit_size == 64)
2657 num_components *= 2;
2658
2659 ret = ac_build_buffer_load(&ctx->ac, rsrc, num_components, NULL, offset,
2660 NULL, 0, false, false, true, true);
2661 ret = trim_vector(&ctx->ac, ret, num_components);
2662 return LLVMBuildBitCast(ctx->ac.builder, ret,
2663 get_def_type(ctx, &instr->dest.ssa), "");
2664 }
2665
2666 static void
2667 get_deref_offset(struct ac_nir_context *ctx, nir_deref_var *deref,
2668 bool vs_in, unsigned *vertex_index_out,
2669 LLVMValueRef *vertex_index_ref,
2670 unsigned *const_out, LLVMValueRef *indir_out)
2671 {
2672 unsigned const_offset = 0;
2673 nir_deref *tail = &deref->deref;
2674 LLVMValueRef offset = NULL;
2675
2676 if (vertex_index_out != NULL || vertex_index_ref != NULL) {
2677 tail = tail->child;
2678 nir_deref_array *deref_array = nir_deref_as_array(tail);
2679 if (vertex_index_out)
2680 *vertex_index_out = deref_array->base_offset;
2681
2682 if (vertex_index_ref) {
2683 LLVMValueRef vtx = LLVMConstInt(ctx->ac.i32, deref_array->base_offset, false);
2684 if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
2685 vtx = LLVMBuildAdd(ctx->ac.builder, vtx, get_src(ctx, deref_array->indirect), "");
2686 }
2687 *vertex_index_ref = vtx;
2688 }
2689 }
2690
2691 if (deref->var->data.compact) {
2692 assert(tail->child->deref_type == nir_deref_type_array);
2693 assert(glsl_type_is_scalar(glsl_without_array(deref->var->type)));
2694 nir_deref_array *deref_array = nir_deref_as_array(tail->child);
2695 /* We always lower indirect dereferences for "compact" array vars. */
2696 assert(deref_array->deref_array_type == nir_deref_array_type_direct);
2697
2698 const_offset = deref_array->base_offset;
2699 goto out;
2700 }
2701
2702 while (tail->child != NULL) {
2703 const struct glsl_type *parent_type = tail->type;
2704 tail = tail->child;
2705
2706 if (tail->deref_type == nir_deref_type_array) {
2707 nir_deref_array *deref_array = nir_deref_as_array(tail);
2708 LLVMValueRef index, stride, local_offset;
2709 unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
2710
2711 const_offset += size * deref_array->base_offset;
2712 if (deref_array->deref_array_type == nir_deref_array_type_direct)
2713 continue;
2714
2715 assert(deref_array->deref_array_type == nir_deref_array_type_indirect);
2716 index = get_src(ctx, deref_array->indirect);
2717 stride = LLVMConstInt(ctx->ac.i32, size, 0);
2718 local_offset = LLVMBuildMul(ctx->ac.builder, stride, index, "");
2719
2720 if (offset)
2721 offset = LLVMBuildAdd(ctx->ac.builder, offset, local_offset, "");
2722 else
2723 offset = local_offset;
2724 } else if (tail->deref_type == nir_deref_type_struct) {
2725 nir_deref_struct *deref_struct = nir_deref_as_struct(tail);
2726
2727 for (unsigned i = 0; i < deref_struct->index; i++) {
2728 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
2729 const_offset += glsl_count_attribute_slots(ft, vs_in);
2730 }
2731 } else
2732 unreachable("unsupported deref type");
2733
2734 }
2735 out:
2736 if (const_offset && offset)
2737 offset = LLVMBuildAdd(ctx->ac.builder, offset,
2738 LLVMConstInt(ctx->ac.i32, const_offset, 0),
2739 "");
2740
2741 *const_out = const_offset;
2742 *indir_out = offset;
2743 }
2744
2745
2746 /* The offchip buffer layout for TCS->TES is
2747 *
2748 * - attribute 0 of patch 0 vertex 0
2749 * - attribute 0 of patch 0 vertex 1
2750 * - attribute 0 of patch 0 vertex 2
2751 * ...
2752 * - attribute 0 of patch 1 vertex 0
2753 * - attribute 0 of patch 1 vertex 1
2754 * ...
2755 * - attribute 1 of patch 0 vertex 0
2756 * - attribute 1 of patch 0 vertex 1
2757 * ...
2758 * - per patch attribute 0 of patch 0
2759 * - per patch attribute 0 of patch 1
2760 * ...
2761 *
2762 * Note that every attribute has 4 components.
2763 */
2764 static LLVMValueRef get_tcs_tes_buffer_address(struct nir_to_llvm_context *ctx,
2765 LLVMValueRef vertex_index,
2766 LLVMValueRef param_index)
2767 {
2768 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
2769 LLVMValueRef param_stride, constant16;
2770 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
2771
2772 vertices_per_patch = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 9, 6);
2773 num_patches = unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 0, 9);
2774 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
2775 num_patches, "");
2776
2777 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
2778 if (vertex_index) {
2779 base_addr = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
2780 vertices_per_patch, "");
2781
2782 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2783 vertex_index, "");
2784
2785 param_stride = total_vertices;
2786 } else {
2787 base_addr = rel_patch_id;
2788 param_stride = num_patches;
2789 }
2790
2791 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2792 LLVMBuildMul(ctx->ac.builder, param_index,
2793 param_stride, ""), "");
2794
2795 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
2796
2797 if (!vertex_index) {
2798 LLVMValueRef patch_data_offset =
2799 unpack_param(&ctx->ac, ctx->tcs_offchip_layout, 16, 16);
2800
2801 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
2802 patch_data_offset, "");
2803 }
2804 return base_addr;
2805 }
2806
2807 static LLVMValueRef get_tcs_tes_buffer_address_params(struct nir_to_llvm_context *ctx,
2808 unsigned param,
2809 unsigned const_index,
2810 bool is_compact,
2811 LLVMValueRef vertex_index,
2812 LLVMValueRef indir_index)
2813 {
2814 LLVMValueRef param_index;
2815
2816 if (indir_index)
2817 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
2818 indir_index, "");
2819 else {
2820 if (const_index && !is_compact)
2821 param += const_index;
2822 param_index = LLVMConstInt(ctx->ac.i32, param, false);
2823 }
2824 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
2825 }
2826
2827 static void
2828 mark_tess_output(struct nir_to_llvm_context *ctx,
2829 bool is_patch, uint32_t param)
2830
2831 {
2832 if (is_patch) {
2833 ctx->tess_patch_outputs_written |= (1ull << param);
2834 } else
2835 ctx->tess_outputs_written |= (1ull << param);
2836 }
2837
2838 static LLVMValueRef
2839 get_dw_address(struct nir_to_llvm_context *ctx,
2840 LLVMValueRef dw_addr,
2841 unsigned param,
2842 unsigned const_index,
2843 bool compact_const_index,
2844 LLVMValueRef vertex_index,
2845 LLVMValueRef stride,
2846 LLVMValueRef indir_index)
2847
2848 {
2849
2850 if (vertex_index) {
2851 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2852 LLVMBuildMul(ctx->ac.builder,
2853 vertex_index,
2854 stride, ""), "");
2855 }
2856
2857 if (indir_index)
2858 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2859 LLVMBuildMul(ctx->ac.builder, indir_index,
2860 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
2861 else if (const_index && !compact_const_index)
2862 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2863 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2864
2865 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2866 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
2867
2868 if (const_index && compact_const_index)
2869 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2870 LLVMConstInt(ctx->ac.i32, const_index, false), "");
2871 return dw_addr;
2872 }
2873
2874 static LLVMValueRef
2875 load_tcs_varyings(struct ac_shader_abi *abi,
2876 LLVMValueRef vertex_index,
2877 LLVMValueRef indir_index,
2878 unsigned const_index,
2879 unsigned location,
2880 unsigned driver_location,
2881 unsigned component,
2882 unsigned num_components,
2883 bool is_patch,
2884 bool is_compact,
2885 bool load_input)
2886 {
2887 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2888 LLVMValueRef dw_addr, stride;
2889 LLVMValueRef value[4], result;
2890 unsigned param = shader_io_get_unique_index(location);
2891
2892 if (load_input) {
2893 stride = unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
2894 dw_addr = get_tcs_in_current_patch_offset(ctx);
2895 } else {
2896 if (!is_patch) {
2897 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2898 dw_addr = get_tcs_out_current_patch_offset(ctx);
2899 } else {
2900 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2901 stride = NULL;
2902 }
2903 }
2904
2905 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2906 indir_index);
2907
2908 for (unsigned i = 0; i < num_components + component; i++) {
2909 value[i] = ac_lds_load(&ctx->ac, dw_addr);
2910 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
2911 ctx->ac.i32_1, "");
2912 }
2913 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
2914 return result;
2915 }
2916
2917 static void
2918 store_tcs_output(struct ac_shader_abi *abi,
2919 LLVMValueRef vertex_index,
2920 LLVMValueRef param_index,
2921 unsigned const_index,
2922 unsigned location,
2923 unsigned driver_location,
2924 LLVMValueRef src,
2925 unsigned component,
2926 bool is_patch,
2927 bool is_compact,
2928 unsigned writemask)
2929 {
2930 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
2931 LLVMValueRef dw_addr;
2932 LLVMValueRef stride = NULL;
2933 LLVMValueRef buf_addr = NULL;
2934 unsigned param;
2935 bool store_lds = true;
2936
2937 if (is_patch) {
2938 if (!(ctx->tcs_patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
2939 store_lds = false;
2940 } else {
2941 if (!(ctx->tcs_outputs_read & (1ULL << location)))
2942 store_lds = false;
2943 }
2944
2945 param = shader_io_get_unique_index(location);
2946 if (location == VARYING_SLOT_CLIP_DIST0 &&
2947 is_compact && const_index > 3) {
2948 const_index -= 3;
2949 param++;
2950 }
2951
2952 if (!is_patch) {
2953 stride = unpack_param(&ctx->ac, ctx->tcs_out_layout, 13, 8);
2954 dw_addr = get_tcs_out_current_patch_offset(ctx);
2955 } else {
2956 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
2957 }
2958
2959 mark_tess_output(ctx, is_patch, param);
2960
2961 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
2962 param_index);
2963 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
2964 vertex_index, param_index);
2965
2966 bool is_tess_factor = false;
2967 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
2968 location == VARYING_SLOT_TESS_LEVEL_OUTER)
2969 is_tess_factor = true;
2970
2971 unsigned base = is_compact ? const_index : 0;
2972 for (unsigned chan = 0; chan < 8; chan++) {
2973 if (!(writemask & (1 << chan)))
2974 continue;
2975 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
2976
2977 if (store_lds || is_tess_factor) {
2978 LLVMValueRef dw_addr_chan =
2979 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2980 LLVMConstInt(ctx->ac.i32, chan, false), "");
2981 ac_lds_store(&ctx->ac, dw_addr_chan, value);
2982 }
2983
2984 if (!is_tess_factor && writemask != 0xF)
2985 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
2986 buf_addr, ctx->oc_lds,
2987 4 * (base + chan), 1, 0, true, false);
2988 }
2989
2990 if (writemask == 0xF) {
2991 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
2992 buf_addr, ctx->oc_lds,
2993 (base * 4), 1, 0, true, false);
2994 }
2995 }
2996
2997 static LLVMValueRef
2998 load_tes_input(struct ac_shader_abi *abi,
2999 LLVMValueRef vertex_index,
3000 LLVMValueRef param_index,
3001 unsigned const_index,
3002 unsigned location,
3003 unsigned driver_location,
3004 unsigned component,
3005 unsigned num_components,
3006 bool is_patch,
3007 bool is_compact,
3008 bool load_input)
3009 {
3010 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3011 LLVMValueRef buf_addr;
3012 LLVMValueRef result;
3013 unsigned param = shader_io_get_unique_index(location);
3014
3015 if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 3) {
3016 const_index -= 3;
3017 param++;
3018 }
3019
3020 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
3021 is_compact, vertex_index, param_index);
3022
3023 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
3024 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
3025
3026 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
3027 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, 1, 0, true, false);
3028 result = trim_vector(&ctx->ac, result, num_components);
3029 return result;
3030 }
3031
3032 static LLVMValueRef
3033 load_gs_input(struct ac_shader_abi *abi,
3034 unsigned location,
3035 unsigned driver_location,
3036 unsigned component,
3037 unsigned num_components,
3038 unsigned vertex_index,
3039 unsigned const_index,
3040 LLVMTypeRef type)
3041 {
3042 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
3043 LLVMValueRef vtx_offset;
3044 unsigned param, vtx_offset_param;
3045 LLVMValueRef value[4], result;
3046
3047 vtx_offset_param = vertex_index;
3048 assert(vtx_offset_param < 6);
3049 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
3050 LLVMConstInt(ctx->ac.i32, 4, false), "");
3051
3052 param = shader_io_get_unique_index(location);
3053
3054 for (unsigned i = component; i < num_components + component; i++) {
3055 if (ctx->ac.chip_class >= GFX9) {
3056 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
3057 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
3058 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
3059 value[i] = ac_lds_load(&ctx->ac, dw_addr);
3060 } else {
3061 LLVMValueRef soffset =
3062 LLVMConstInt(ctx->ac.i32,
3063 (param * 4 + i + const_index) * 256,
3064 false);
3065
3066 value[i] = ac_build_buffer_load(&ctx->ac,
3067 ctx->esgs_ring, 1,
3068 ctx->ac.i32_0,
3069 vtx_offset, soffset,
3070 0, 1, 0, true, false);
3071
3072 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i],
3073 type, "");
3074 }
3075 }
3076 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
3077 result = ac_to_integer(&ctx->ac, result);
3078 return result;
3079 }
3080
3081 static LLVMValueRef
3082 build_gep_for_deref(struct ac_nir_context *ctx,
3083 nir_deref_var *deref)
3084 {
3085 struct hash_entry *entry = _mesa_hash_table_search(ctx->vars, deref->var);
3086 assert(entry->data);
3087 LLVMValueRef val = entry->data;
3088 nir_deref *tail = deref->deref.child;
3089 while (tail != NULL) {
3090 LLVMValueRef offset;
3091 switch (tail->deref_type) {
3092 case nir_deref_type_array: {
3093 nir_deref_array *array = nir_deref_as_array(tail);
3094 offset = LLVMConstInt(ctx->ac.i32, array->base_offset, 0);
3095 if (array->deref_array_type ==
3096 nir_deref_array_type_indirect) {
3097 offset = LLVMBuildAdd(ctx->ac.builder, offset,
3098 get_src(ctx,
3099 array->indirect),
3100 "");
3101 }
3102 break;
3103 }
3104 case nir_deref_type_struct: {
3105 nir_deref_struct *deref_struct =
3106 nir_deref_as_struct(tail);
3107 offset = LLVMConstInt(ctx->ac.i32,
3108 deref_struct->index, 0);
3109 break;
3110 }
3111 default:
3112 unreachable("bad deref type");
3113 }
3114 val = ac_build_gep0(&ctx->ac, val, offset);
3115 tail = tail->child;
3116 }
3117 return val;
3118 }
3119
3120 static LLVMValueRef load_tess_varyings(struct ac_nir_context *ctx,
3121 nir_intrinsic_instr *instr,
3122 bool load_inputs)
3123 {
3124 LLVMValueRef result;
3125 LLVMValueRef vertex_index = NULL;
3126 LLVMValueRef indir_index = NULL;
3127 unsigned const_index = 0;
3128 unsigned location = instr->variables[0]->var->data.location;
3129 unsigned driver_location = instr->variables[0]->var->data.driver_location;
3130 const bool is_patch = instr->variables[0]->var->data.patch;
3131 const bool is_compact = instr->variables[0]->var->data.compact;
3132
3133 get_deref_offset(ctx, instr->variables[0],
3134 false, NULL, is_patch ? NULL : &vertex_index,
3135 &const_index, &indir_index);
3136
3137 result = ctx->abi->load_tess_varyings(ctx->abi, vertex_index, indir_index,
3138 const_index, location, driver_location,
3139 instr->variables[0]->var->data.location_frac,
3140 instr->num_components,
3141 is_patch, is_compact, load_inputs);
3142 return LLVMBuildBitCast(ctx->ac.builder, result, get_def_type(ctx, &instr->dest.ssa), "");
3143 }
3144
3145 static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
3146 nir_intrinsic_instr *instr)
3147 {
3148 LLVMValueRef values[8];
3149 int idx = instr->variables[0]->var->data.driver_location;
3150 int ve = instr->dest.ssa.num_components;
3151 unsigned comp = instr->variables[0]->var->data.location_frac;
3152 LLVMValueRef indir_index;
3153 LLVMValueRef ret;
3154 unsigned const_index;
3155 unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
3156 bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
3157 instr->variables[0]->var->data.mode == nir_var_shader_in;
3158 get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
3159 &const_index, &indir_index);
3160
3161 if (instr->dest.ssa.bit_size == 64)
3162 ve *= 2;
3163
3164 switch (instr->variables[0]->var->data.mode) {
3165 case nir_var_shader_in:
3166 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3167 ctx->stage == MESA_SHADER_TESS_EVAL) {
3168 return load_tess_varyings(ctx, instr, true);
3169 }
3170
3171 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3172 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
3173 LLVMValueRef indir_index;
3174 unsigned const_index, vertex_index;
3175 get_deref_offset(ctx, instr->variables[0],
3176 false, &vertex_index, NULL,
3177 &const_index, &indir_index);
3178
3179 return ctx->abi->load_inputs(ctx->abi, instr->variables[0]->var->data.location,
3180 instr->variables[0]->var->data.driver_location,
3181 instr->variables[0]->var->data.location_frac, ve,
3182 vertex_index, const_index, type);
3183 }
3184
3185 for (unsigned chan = comp; chan < ve + comp; chan++) {
3186 if (indir_index) {
3187 unsigned count = glsl_count_attribute_slots(
3188 instr->variables[0]->var->type,
3189 ctx->stage == MESA_SHADER_VERTEX);
3190 count -= chan / 4;
3191 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3192 &ctx->ac, ctx->abi->inputs + idx + chan, count,
3193 stride, false, true);
3194
3195 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3196 tmp_vec,
3197 indir_index, "");
3198 } else
3199 values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
3200 }
3201 break;
3202 case nir_var_local:
3203 for (unsigned chan = 0; chan < ve; chan++) {
3204 if (indir_index) {
3205 unsigned count = glsl_count_attribute_slots(
3206 instr->variables[0]->var->type, false);
3207 count -= chan / 4;
3208 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3209 &ctx->ac, ctx->locals + idx + chan, count,
3210 stride, true, true);
3211
3212 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3213 tmp_vec,
3214 indir_index, "");
3215 } else {
3216 values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
3217 }
3218 }
3219 break;
3220 case nir_var_shared: {
3221 LLVMValueRef address = build_gep_for_deref(ctx,
3222 instr->variables[0]);
3223 LLVMValueRef val = LLVMBuildLoad(ctx->ac.builder, address, "");
3224 return LLVMBuildBitCast(ctx->ac.builder, val,
3225 get_def_type(ctx, &instr->dest.ssa),
3226 "");
3227 }
3228 case nir_var_shader_out:
3229 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3230 return load_tess_varyings(ctx, instr, false);
3231 }
3232
3233 for (unsigned chan = comp; chan < ve + comp; chan++) {
3234 if (indir_index) {
3235 unsigned count = glsl_count_attribute_slots(
3236 instr->variables[0]->var->type, false);
3237 count -= chan / 4;
3238 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3239 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3240 stride, true, true);
3241
3242 values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
3243 tmp_vec,
3244 indir_index, "");
3245 } else {
3246 values[chan] = LLVMBuildLoad(ctx->ac.builder,
3247 ctx->abi->outputs[idx + chan + const_index * stride],
3248 "");
3249 }
3250 }
3251 break;
3252 default:
3253 unreachable("unhandle variable mode");
3254 }
3255 ret = ac_build_varying_gather_values(&ctx->ac, values, ve, comp);
3256 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3257 }
3258
3259 static void
3260 visit_store_var(struct ac_nir_context *ctx,
3261 nir_intrinsic_instr *instr)
3262 {
3263 LLVMValueRef temp_ptr, value;
3264 int idx = instr->variables[0]->var->data.driver_location;
3265 unsigned comp = instr->variables[0]->var->data.location_frac;
3266 LLVMValueRef src = ac_to_float(&ctx->ac, get_src(ctx, instr->src[0]));
3267 int writemask = instr->const_index[0] << comp;
3268 LLVMValueRef indir_index;
3269 unsigned const_index;
3270 get_deref_offset(ctx, instr->variables[0], false,
3271 NULL, NULL, &const_index, &indir_index);
3272
3273 if (ac_get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
3274
3275 src = LLVMBuildBitCast(ctx->ac.builder, src,
3276 LLVMVectorType(ctx->ac.f32, ac_get_llvm_num_components(src) * 2),
3277 "");
3278
3279 writemask = widen_mask(writemask, 2);
3280 }
3281
3282 switch (instr->variables[0]->var->data.mode) {
3283 case nir_var_shader_out:
3284
3285 if (ctx->stage == MESA_SHADER_TESS_CTRL) {
3286 LLVMValueRef vertex_index = NULL;
3287 LLVMValueRef indir_index = NULL;
3288 unsigned const_index = 0;
3289 const unsigned location = instr->variables[0]->var->data.location;
3290 const unsigned driver_location = instr->variables[0]->var->data.driver_location;
3291 const unsigned comp = instr->variables[0]->var->data.location_frac;
3292 const bool is_patch = instr->variables[0]->var->data.patch;
3293 const bool is_compact = instr->variables[0]->var->data.compact;
3294
3295 get_deref_offset(ctx, instr->variables[0],
3296 false, NULL, is_patch ? NULL : &vertex_index,
3297 &const_index, &indir_index);
3298
3299 ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, indir_index,
3300 const_index, location, driver_location,
3301 src, comp, is_patch, is_compact, writemask);
3302 return;
3303 }
3304
3305 for (unsigned chan = 0; chan < 8; chan++) {
3306 int stride = 4;
3307 if (!(writemask & (1 << chan)))
3308 continue;
3309
3310 value = ac_llvm_extract_elem(&ctx->ac, src, chan - comp);
3311
3312 if (instr->variables[0]->var->data.compact)
3313 stride = 1;
3314 if (indir_index) {
3315 unsigned count = glsl_count_attribute_slots(
3316 instr->variables[0]->var->type, false);
3317 count -= chan / 4;
3318 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3319 &ctx->ac, ctx->abi->outputs + idx + chan, count,
3320 stride, true, true);
3321
3322 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3323 value, indir_index, "");
3324 build_store_values_extended(&ctx->ac, ctx->abi->outputs + idx + chan,
3325 count, stride, tmp_vec);
3326
3327 } else {
3328 temp_ptr = ctx->abi->outputs[idx + chan + const_index * stride];
3329
3330 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3331 }
3332 }
3333 break;
3334 case nir_var_local:
3335 for (unsigned chan = 0; chan < 8; chan++) {
3336 if (!(writemask & (1 << chan)))
3337 continue;
3338
3339 value = ac_llvm_extract_elem(&ctx->ac, src, chan);
3340 if (indir_index) {
3341 unsigned count = glsl_count_attribute_slots(
3342 instr->variables[0]->var->type, false);
3343 count -= chan / 4;
3344 LLVMValueRef tmp_vec = ac_build_gather_values_extended(
3345 &ctx->ac, ctx->locals + idx + chan, count,
3346 4, true, true);
3347
3348 tmp_vec = LLVMBuildInsertElement(ctx->ac.builder, tmp_vec,
3349 value, indir_index, "");
3350 build_store_values_extended(&ctx->ac, ctx->locals + idx + chan,
3351 count, 4, tmp_vec);
3352 } else {
3353 temp_ptr = ctx->locals[idx + chan + const_index * 4];
3354
3355 LLVMBuildStore(ctx->ac.builder, value, temp_ptr);
3356 }
3357 }
3358 break;
3359 case nir_var_shared: {
3360 int writemask = instr->const_index[0];
3361 LLVMValueRef address = build_gep_for_deref(ctx,
3362 instr->variables[0]);
3363 LLVMValueRef val = get_src(ctx, instr->src[0]);
3364 unsigned components =
3365 glsl_get_vector_elements(
3366 nir_deref_tail(&instr->variables[0]->deref)->type);
3367 if (writemask == (1 << components) - 1) {
3368 val = LLVMBuildBitCast(
3369 ctx->ac.builder, val,
3370 LLVMGetElementType(LLVMTypeOf(address)), "");
3371 LLVMBuildStore(ctx->ac.builder, val, address);
3372 } else {
3373 for (unsigned chan = 0; chan < 4; chan++) {
3374 if (!(writemask & (1 << chan)))
3375 continue;
3376 LLVMValueRef ptr =
3377 LLVMBuildStructGEP(ctx->ac.builder,
3378 address, chan, "");
3379 LLVMValueRef src = ac_llvm_extract_elem(&ctx->ac, val,
3380 chan);
3381 src = LLVMBuildBitCast(
3382 ctx->ac.builder, src,
3383 LLVMGetElementType(LLVMTypeOf(ptr)), "");
3384 LLVMBuildStore(ctx->ac.builder, src, ptr);
3385 }
3386 }
3387 break;
3388 }
3389 default:
3390 break;
3391 }
3392 }
3393
3394 static int image_type_to_components_count(enum glsl_sampler_dim dim, bool array)
3395 {
3396 switch (dim) {
3397 case GLSL_SAMPLER_DIM_BUF:
3398 return 1;
3399 case GLSL_SAMPLER_DIM_1D:
3400 return array ? 2 : 1;
3401 case GLSL_SAMPLER_DIM_2D:
3402 return array ? 3 : 2;
3403 case GLSL_SAMPLER_DIM_MS:
3404 return array ? 4 : 3;
3405 case GLSL_SAMPLER_DIM_3D:
3406 case GLSL_SAMPLER_DIM_CUBE:
3407 return 3;
3408 case GLSL_SAMPLER_DIM_RECT:
3409 case GLSL_SAMPLER_DIM_SUBPASS:
3410 return 2;
3411 case GLSL_SAMPLER_DIM_SUBPASS_MS:
3412 return 3;
3413 default:
3414 break;
3415 }
3416 return 0;
3417 }
3418
3419
3420
3421 /* Adjust the sample index according to FMASK.
3422 *
3423 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
3424 * which is the identity mapping. Each nibble says which physical sample
3425 * should be fetched to get that sample.
3426 *
3427 * For example, 0x11111100 means there are only 2 samples stored and
3428 * the second sample covers 3/4 of the pixel. When reading samples 0
3429 * and 1, return physical sample 0 (determined by the first two 0s
3430 * in FMASK), otherwise return physical sample 1.
3431 *
3432 * The sample index should be adjusted as follows:
3433 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
3434 */
3435 static LLVMValueRef adjust_sample_index_using_fmask(struct ac_llvm_context *ctx,
3436 LLVMValueRef coord_x, LLVMValueRef coord_y,
3437 LLVMValueRef coord_z,
3438 LLVMValueRef sample_index,
3439 LLVMValueRef fmask_desc_ptr)
3440 {
3441 LLVMValueRef fmask_load_address[4];
3442 LLVMValueRef res;
3443
3444 fmask_load_address[0] = coord_x;
3445 fmask_load_address[1] = coord_y;
3446 if (coord_z) {
3447 fmask_load_address[2] = coord_z;
3448 fmask_load_address[3] = LLVMGetUndef(ctx->i32);
3449 }
3450
3451 struct ac_image_args args = {0};
3452
3453 args.opcode = ac_image_load;
3454 args.da = coord_z ? true : false;
3455 args.resource = fmask_desc_ptr;
3456 args.dmask = 0xf;
3457 args.addr = ac_build_gather_values(ctx, fmask_load_address, coord_z ? 4 : 2);
3458
3459 res = ac_build_image_opcode(ctx, &args);
3460
3461 res = ac_to_integer(ctx, res);
3462 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, false);
3463 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xf, false);
3464
3465 LLVMValueRef fmask = LLVMBuildExtractElement(ctx->builder,
3466 res,
3467 ctx->i32_0, "");
3468
3469 LLVMValueRef sample_index4 =
3470 LLVMBuildMul(ctx->builder, sample_index, four, "");
3471 LLVMValueRef shifted_fmask =
3472 LLVMBuildLShr(ctx->builder, fmask, sample_index4, "");
3473 LLVMValueRef final_sample =
3474 LLVMBuildAnd(ctx->builder, shifted_fmask, F, "");
3475
3476 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
3477 * resource descriptor is 0 (invalid),
3478 */
3479 LLVMValueRef fmask_desc =
3480 LLVMBuildBitCast(ctx->builder, fmask_desc_ptr,
3481 ctx->v8i32, "");
3482
3483 LLVMValueRef fmask_word1 =
3484 LLVMBuildExtractElement(ctx->builder, fmask_desc,
3485 ctx->i32_1, "");
3486
3487 LLVMValueRef word1_is_nonzero =
3488 LLVMBuildICmp(ctx->builder, LLVMIntNE,
3489 fmask_word1, ctx->i32_0, "");
3490
3491 /* Replace the MSAA sample index. */
3492 sample_index =
3493 LLVMBuildSelect(ctx->builder, word1_is_nonzero,
3494 final_sample, sample_index, "");
3495 return sample_index;
3496 }
3497
3498 static LLVMValueRef get_image_coords(struct ac_nir_context *ctx,
3499 const nir_intrinsic_instr *instr)
3500 {
3501 const struct glsl_type *type = glsl_without_array(instr->variables[0]->var->type);
3502
3503 LLVMValueRef src0 = get_src(ctx, instr->src[0]);
3504 LLVMValueRef coords[4];
3505 LLVMValueRef masks[] = {
3506 LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
3507 LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
3508 };
3509 LLVMValueRef res;
3510 LLVMValueRef sample_index = ac_llvm_extract_elem(&ctx->ac, get_src(ctx, instr->src[1]), 0);
3511
3512 int count;
3513 enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3514 bool is_array = glsl_sampler_type_is_array(type);
3515 bool add_frag_pos = (dim == GLSL_SAMPLER_DIM_SUBPASS ||
3516 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3517 bool is_ms = (dim == GLSL_SAMPLER_DIM_MS ||
3518 dim == GLSL_SAMPLER_DIM_SUBPASS_MS);
3519 bool gfx9_1d = ctx->ac.chip_class >= GFX9 && dim == GLSL_SAMPLER_DIM_1D;
3520 count = image_type_to_components_count(dim, is_array);
3521
3522 if (is_ms) {
3523 LLVMValueRef fmask_load_address[3];
3524 int chan;
3525
3526 fmask_load_address[0] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3527 fmask_load_address[1] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[1], "");
3528 if (is_array)
3529 fmask_load_address[2] = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[2], "");
3530 else
3531 fmask_load_address[2] = NULL;
3532 if (add_frag_pos) {
3533 for (chan = 0; chan < 2; ++chan)
3534 fmask_load_address[chan] =
3535 LLVMBuildAdd(ctx->ac.builder, fmask_load_address[chan],
3536 LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3537 ctx->ac.i32, ""), "");
3538 fmask_load_address[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3539 }
3540 sample_index = adjust_sample_index_using_fmask(&ctx->ac,
3541 fmask_load_address[0],
3542 fmask_load_address[1],
3543 fmask_load_address[2],
3544 sample_index,
3545 get_sampler_desc(ctx, instr->variables[0], AC_DESC_FMASK, NULL, true, false));
3546 }
3547 if (count == 1 && !gfx9_1d) {
3548 if (instr->src[0].ssa->num_components)
3549 res = LLVMBuildExtractElement(ctx->ac.builder, src0, masks[0], "");
3550 else
3551 res = src0;
3552 } else {
3553 int chan;
3554 if (is_ms)
3555 count--;
3556 for (chan = 0; chan < count; ++chan) {
3557 coords[chan] = ac_llvm_extract_elem(&ctx->ac, src0, chan);
3558 }
3559 if (add_frag_pos) {
3560 for (chan = 0; chan < 2; ++chan)
3561 coords[chan] = LLVMBuildAdd(ctx->ac.builder, coords[chan], LLVMBuildFPToUI(ctx->ac.builder, ctx->abi->frag_pos[chan],
3562 ctx->ac.i32, ""), "");
3563 coords[2] = ac_to_integer(&ctx->ac, ctx->abi->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)]);
3564 count++;
3565 }
3566
3567 if (gfx9_1d) {
3568 if (is_array) {
3569 coords[2] = coords[1];
3570 coords[1] = ctx->ac.i32_0;
3571 } else
3572 coords[1] = ctx->ac.i32_0;
3573 count++;
3574 }
3575
3576 if (is_ms) {
3577 coords[count] = sample_index;
3578 count++;
3579 }
3580
3581 if (count == 3) {
3582 coords[3] = LLVMGetUndef(ctx->ac.i32);
3583 count = 4;
3584 }
3585 res = ac_build_gather_values(&ctx->ac, coords, count);
3586 }
3587 return res;
3588 }
3589
3590 static LLVMValueRef visit_image_load(struct ac_nir_context *ctx,
3591 const nir_intrinsic_instr *instr)
3592 {
3593 LLVMValueRef params[7];
3594 LLVMValueRef res;
3595 char intrinsic_name[64];
3596 const nir_variable *var = instr->variables[0]->var;
3597 const struct glsl_type *type = var->type;
3598
3599 if(instr->variables[0]->deref.child)
3600 type = instr->variables[0]->deref.child->type;
3601
3602 type = glsl_without_array(type);
3603
3604 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3605 if (dim == GLSL_SAMPLER_DIM_BUF) {
3606 unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa);
3607 unsigned num_channels = util_last_bit(mask);
3608 LLVMValueRef rsrc, vindex;
3609
3610 rsrc = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, false);
3611 vindex = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3612 ctx->ac.i32_0, "");
3613
3614 /* TODO: set "glc" and "can_speculate" when OpenGL needs it. */
3615 res = ac_build_buffer_load_format(&ctx->ac, rsrc, vindex,
3616 ctx->ac.i32_0, num_channels,
3617 false, false);
3618 res = ac_build_expand_to_vec4(&ctx->ac, res, num_channels);
3619
3620 res = trim_vector(&ctx->ac, res, instr->dest.ssa.num_components);
3621 res = ac_to_integer(&ctx->ac, res);
3622 } else {
3623 bool is_da = glsl_sampler_type_is_array(type) ||
3624 dim == GLSL_SAMPLER_DIM_CUBE ||
3625 dim == GLSL_SAMPLER_DIM_3D ||
3626 dim == GLSL_SAMPLER_DIM_SUBPASS ||
3627 dim == GLSL_SAMPLER_DIM_SUBPASS_MS;
3628 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3629 LLVMValueRef glc = ctx->ac.i1false;
3630 LLVMValueRef slc = ctx->ac.i1false;
3631
3632 params[0] = get_image_coords(ctx, instr);
3633 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3634 params[2] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3635 params[3] = glc;
3636 params[4] = slc;
3637 params[5] = ctx->ac.i1false;
3638 params[6] = da;
3639
3640 ac_get_image_intr_name("llvm.amdgcn.image.load",
3641 ctx->ac.v4f32, /* vdata */
3642 LLVMTypeOf(params[0]), /* coords */
3643 LLVMTypeOf(params[1]), /* rsrc */
3644 intrinsic_name, sizeof(intrinsic_name));
3645
3646 res = ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.v4f32,
3647 params, 7, AC_FUNC_ATTR_READONLY);
3648 }
3649 return ac_to_integer(&ctx->ac, res);
3650 }
3651
3652 static void visit_image_store(struct ac_nir_context *ctx,
3653 nir_intrinsic_instr *instr)
3654 {
3655 LLVMValueRef params[8];
3656 char intrinsic_name[64];
3657 const nir_variable *var = instr->variables[0]->var;
3658 const struct glsl_type *type = glsl_without_array(var->type);
3659 const enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
3660 LLVMValueRef glc = ctx->ac.i1false;
3661 bool force_glc = ctx->ac.chip_class == SI;
3662 if (force_glc)
3663 glc = ctx->ac.i1true;
3664
3665 if (dim == GLSL_SAMPLER_DIM_BUF) {
3666 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2])); /* data */
3667 params[1] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER, NULL, true, true);
3668 params[2] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3669 ctx->ac.i32_0, ""); /* vindex */
3670 params[3] = ctx->ac.i32_0; /* voffset */
3671 params[4] = glc; /* glc */
3672 params[5] = ctx->ac.i1false; /* slc */
3673 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32", ctx->ac.voidt,
3674 params, 6, 0);
3675 } else {
3676 bool is_da = glsl_sampler_type_is_array(type) ||
3677 dim == GLSL_SAMPLER_DIM_CUBE ||
3678 dim == GLSL_SAMPLER_DIM_3D;
3679 LLVMValueRef da = is_da ? ctx->ac.i1true : ctx->ac.i1false;
3680 LLVMValueRef slc = ctx->ac.i1false;
3681
3682 params[0] = ac_to_float(&ctx->ac, get_src(ctx, instr->src[2]));
3683 params[1] = get_image_coords(ctx, instr); /* coords */
3684 params[2] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, true);
3685 params[3] = LLVMConstInt(ctx->ac.i32, 15, false); /* dmask */
3686 params[4] = glc;
3687 params[5] = slc;
3688 params[6] = ctx->ac.i1false;
3689 params[7] = da;
3690
3691 ac_get_image_intr_name("llvm.amdgcn.image.store",
3692 LLVMTypeOf(params[0]), /* vdata */
3693 LLVMTypeOf(params[1]), /* coords */
3694 LLVMTypeOf(params[2]), /* rsrc */
3695 intrinsic_name, sizeof(intrinsic_name));
3696
3697 ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.voidt,
3698 params, 8, 0);
3699 }
3700
3701 }
3702
3703 static LLVMValueRef visit_image_atomic(struct ac_nir_context *ctx,
3704 const nir_intrinsic_instr *instr)
3705 {
3706 LLVMValueRef params[7];
3707 int param_count = 0;
3708 const nir_variable *var = instr->variables[0]->var;
3709
3710 const char *atomic_name;
3711 char intrinsic_name[41];
3712 const struct glsl_type *type = glsl_without_array(var->type);
3713 MAYBE_UNUSED int length;
3714
3715 bool is_unsigned = glsl_get_sampler_result_type(type) == GLSL_TYPE_UINT;
3716
3717 switch (instr->intrinsic) {
3718 case nir_intrinsic_image_atomic_add:
3719 atomic_name = "add";
3720 break;
3721 case nir_intrinsic_image_atomic_min:
3722 atomic_name = is_unsigned ? "umin" : "smin";
3723 break;
3724 case nir_intrinsic_image_atomic_max:
3725 atomic_name = is_unsigned ? "umax" : "smax";
3726 break;
3727 case nir_intrinsic_image_atomic_and:
3728 atomic_name = "and";
3729 break;
3730 case nir_intrinsic_image_atomic_or:
3731 atomic_name = "or";
3732 break;
3733 case nir_intrinsic_image_atomic_xor:
3734 atomic_name = "xor";
3735 break;
3736 case nir_intrinsic_image_atomic_exchange:
3737 atomic_name = "swap";
3738 break;
3739 case nir_intrinsic_image_atomic_comp_swap:
3740 atomic_name = "cmpswap";
3741 break;
3742 default:
3743 abort();
3744 }
3745
3746 if (instr->intrinsic == nir_intrinsic_image_atomic_comp_swap)
3747 params[param_count++] = get_src(ctx, instr->src[3]);
3748 params[param_count++] = get_src(ctx, instr->src[2]);
3749
3750 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF) {
3751 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_BUFFER,
3752 NULL, true, true);
3753 params[param_count++] = LLVMBuildExtractElement(ctx->ac.builder, get_src(ctx, instr->src[0]),
3754 ctx->ac.i32_0, ""); /* vindex */
3755 params[param_count++] = ctx->ac.i32_0; /* voffset */
3756 params[param_count++] = ctx->ac.i1false; /* slc */
3757
3758 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3759 "llvm.amdgcn.buffer.atomic.%s", atomic_name);
3760 } else {
3761 char coords_type[8];
3762
3763 bool da = glsl_sampler_type_is_array(type) ||
3764 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE;
3765
3766 LLVMValueRef coords = params[param_count++] = get_image_coords(ctx, instr);
3767 params[param_count++] = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE,
3768 NULL, true, true);
3769 params[param_count++] = ctx->ac.i1false; /* r128 */
3770 params[param_count++] = da ? ctx->ac.i1true : ctx->ac.i1false; /* da */
3771 params[param_count++] = ctx->ac.i1false; /* slc */
3772
3773 build_int_type_name(LLVMTypeOf(coords),
3774 coords_type, sizeof(coords_type));
3775
3776 length = snprintf(intrinsic_name, sizeof(intrinsic_name),
3777 "llvm.amdgcn.image.atomic.%s.%s", atomic_name, coords_type);
3778 }
3779
3780 assert(length < sizeof(intrinsic_name));
3781 return ac_build_intrinsic(&ctx->ac, intrinsic_name, ctx->ac.i32, params, param_count, 0);
3782 }
3783
3784 static LLVMValueRef visit_image_size(struct ac_nir_context *ctx,
3785 const nir_intrinsic_instr *instr)
3786 {
3787 LLVMValueRef res;
3788 const nir_variable *var = instr->variables[0]->var;
3789 const struct glsl_type *type = instr->variables[0]->var->type;
3790 bool da = glsl_sampler_type_is_array(var->type) ||
3791 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_CUBE ||
3792 glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_3D;
3793 if(instr->variables[0]->deref.child)
3794 type = instr->variables[0]->deref.child->type;
3795
3796 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_BUF)
3797 return get_buffer_size(ctx,
3798 get_sampler_desc(ctx, instr->variables[0],
3799 AC_DESC_BUFFER, NULL, true, false), true);
3800
3801 struct ac_image_args args = { 0 };
3802
3803 args.da = da;
3804 args.dmask = 0xf;
3805 args.resource = get_sampler_desc(ctx, instr->variables[0], AC_DESC_IMAGE, NULL, true, false);
3806 args.opcode = ac_image_get_resinfo;
3807 args.addr = ctx->ac.i32_0;
3808
3809 res = ac_build_image_opcode(&ctx->ac, &args);
3810
3811 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
3812
3813 if (glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_CUBE &&
3814 glsl_sampler_type_is_array(type)) {
3815 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
3816 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3817 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
3818 res = LLVMBuildInsertElement(ctx->ac.builder, res, z, two, "");
3819 }
3820 if (ctx->ac.chip_class >= GFX9 &&
3821 glsl_get_sampler_dim(type) == GLSL_SAMPLER_DIM_1D &&
3822 glsl_sampler_type_is_array(type)) {
3823 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, res, two, "");
3824 res = LLVMBuildInsertElement(ctx->ac.builder, res, layers,
3825 ctx->ac.i32_1, "");
3826
3827 }
3828 return res;
3829 }
3830
3831 #define NOOP_WAITCNT 0xf7f
3832 #define LGKM_CNT 0x07f
3833 #define VM_CNT 0xf70
3834
3835 static void emit_membar(struct ac_llvm_context *ac,
3836 const nir_intrinsic_instr *instr)
3837 {
3838 unsigned waitcnt = NOOP_WAITCNT;
3839
3840 switch (instr->intrinsic) {
3841 case nir_intrinsic_memory_barrier:
3842 case nir_intrinsic_group_memory_barrier:
3843 waitcnt &= VM_CNT & LGKM_CNT;
3844 break;
3845 case nir_intrinsic_memory_barrier_atomic_counter:
3846 case nir_intrinsic_memory_barrier_buffer:
3847 case nir_intrinsic_memory_barrier_image:
3848 waitcnt &= VM_CNT;
3849 break;
3850 case nir_intrinsic_memory_barrier_shared:
3851 waitcnt &= LGKM_CNT;
3852 break;
3853 default:
3854 break;
3855 }
3856 if (waitcnt != NOOP_WAITCNT)
3857 ac_build_waitcnt(ac, waitcnt);
3858 }
3859
3860 static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
3861 {
3862 /* SI only (thanks to a hw bug workaround):
3863 * The real barrier instruction isn’t needed, because an entire patch
3864 * always fits into a single wave.
3865 */
3866 if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
3867 ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
3868 return;
3869 }
3870 ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
3871 ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
3872 }
3873
3874 static void emit_discard(struct ac_nir_context *ctx,
3875 const nir_intrinsic_instr *instr)
3876 {
3877 LLVMValueRef cond;
3878
3879 if (instr->intrinsic == nir_intrinsic_discard_if) {
3880 cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3881 get_src(ctx, instr->src[0]),
3882 ctx->ac.i32_0, "");
3883 } else {
3884 assert(instr->intrinsic == nir_intrinsic_discard);
3885 cond = LLVMConstInt(ctx->ac.i1, false, 0);
3886 }
3887
3888 ac_build_kill_if_false(&ctx->ac, cond);
3889 }
3890
3891 static LLVMValueRef
3892 visit_load_helper_invocation(struct ac_nir_context *ctx)
3893 {
3894 LLVMValueRef result = ac_build_intrinsic(&ctx->ac,
3895 "llvm.amdgcn.ps.live",
3896 ctx->ac.i1, NULL, 0,
3897 AC_FUNC_ATTR_READNONE);
3898 result = LLVMBuildNot(ctx->ac.builder, result, "");
3899 return LLVMBuildSExt(ctx->ac.builder, result, ctx->ac.i32, "");
3900 }
3901
3902 static LLVMValueRef
3903 visit_load_local_invocation_index(struct ac_nir_context *ctx)
3904 {
3905 LLVMValueRef result;
3906 LLVMValueRef thread_id = ac_get_thread_id(&ctx->ac);
3907 result = LLVMBuildAnd(ctx->ac.builder, ctx->abi->tg_size,
3908 LLVMConstInt(ctx->ac.i32, 0xfc0, false), "");
3909
3910 return LLVMBuildAdd(ctx->ac.builder, result, thread_id, "");
3911 }
3912
3913 static LLVMValueRef
3914 visit_load_shared(struct ac_nir_context *ctx,
3915 const nir_intrinsic_instr *instr)
3916 {
3917 LLVMValueRef values[4], derived_ptr, index, ret;
3918
3919 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
3920
3921 for (int chan = 0; chan < instr->num_components; chan++) {
3922 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3923 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
3924 values[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
3925 }
3926
3927 ret = ac_build_gather_values(&ctx->ac, values, instr->num_components);
3928 return LLVMBuildBitCast(ctx->ac.builder, ret, get_def_type(ctx, &instr->dest.ssa), "");
3929 }
3930
3931 static void
3932 visit_store_shared(struct ac_nir_context *ctx,
3933 const nir_intrinsic_instr *instr)
3934 {
3935 LLVMValueRef derived_ptr, data,index;
3936 LLVMBuilderRef builder = ctx->ac.builder;
3937
3938 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
3939 LLVMValueRef src = get_src(ctx, instr->src[0]);
3940
3941 int writemask = nir_intrinsic_write_mask(instr);
3942 for (int chan = 0; chan < 4; chan++) {
3943 if (!(writemask & (1 << chan))) {
3944 continue;
3945 }
3946 data = ac_llvm_extract_elem(&ctx->ac, src, chan);
3947 index = LLVMConstInt(ctx->ac.i32, chan, 0);
3948 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3949 LLVMBuildStore(builder, data, derived_ptr);
3950 }
3951 }
3952
3953 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
3954 const nir_intrinsic_instr *instr,
3955 LLVMValueRef ptr)
3956 {
3957 LLVMValueRef result;
3958 LLVMValueRef src = get_src(ctx, instr->src[0]);
3959
3960 if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
3961 instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
3962 LLVMValueRef src1 = get_src(ctx, instr->src[1]);
3963 result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
3964 ptr, src, src1,
3965 LLVMAtomicOrderingSequentiallyConsistent,
3966 LLVMAtomicOrderingSequentiallyConsistent,
3967 false);
3968 } else {
3969 LLVMAtomicRMWBinOp op;
3970 switch (instr->intrinsic) {
3971 case nir_intrinsic_var_atomic_add:
3972 case nir_intrinsic_shared_atomic_add:
3973 op = LLVMAtomicRMWBinOpAdd;
3974 break;
3975 case nir_intrinsic_var_atomic_umin:
3976 case nir_intrinsic_shared_atomic_umin:
3977 op = LLVMAtomicRMWBinOpUMin;
3978 break;
3979 case nir_intrinsic_var_atomic_umax:
3980 case nir_intrinsic_shared_atomic_umax:
3981 op = LLVMAtomicRMWBinOpUMax;
3982 break;
3983 case nir_intrinsic_var_atomic_imin:
3984 case nir_intrinsic_shared_atomic_imin:
3985 op = LLVMAtomicRMWBinOpMin;
3986 break;
3987 case nir_intrinsic_var_atomic_imax:
3988 case nir_intrinsic_shared_atomic_imax:
3989 op = LLVMAtomicRMWBinOpMax;
3990 break;
3991 case nir_intrinsic_var_atomic_and:
3992 case nir_intrinsic_shared_atomic_and:
3993 op = LLVMAtomicRMWBinOpAnd;
3994 break;
3995 case nir_intrinsic_var_atomic_or:
3996 case nir_intrinsic_shared_atomic_or:
3997 op = LLVMAtomicRMWBinOpOr;
3998 break;
3999 case nir_intrinsic_var_atomic_xor:
4000 case nir_intrinsic_shared_atomic_xor:
4001 op = LLVMAtomicRMWBinOpXor;
4002 break;
4003 case nir_intrinsic_var_atomic_exchange:
4004 case nir_intrinsic_shared_atomic_exchange:
4005 op = LLVMAtomicRMWBinOpXchg;
4006 break;
4007 default:
4008 return NULL;
4009 }
4010
4011 result = LLVMBuildAtomicRMW(ctx->ac.builder, op, ptr, ac_to_integer(&ctx->ac, src),
4012 LLVMAtomicOrderingSequentiallyConsistent,
4013 false);
4014 }
4015 return result;
4016 }
4017
4018 static LLVMValueRef lookup_interp_param(struct ac_shader_abi *abi,
4019 enum glsl_interp_mode interp, unsigned location)
4020 {
4021 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4022
4023 switch (interp) {
4024 case INTERP_MODE_FLAT:
4025 default:
4026 return NULL;
4027 case INTERP_MODE_SMOOTH:
4028 case INTERP_MODE_NONE:
4029 if (location == INTERP_CENTER)
4030 return ctx->persp_center;
4031 else if (location == INTERP_CENTROID)
4032 return ctx->persp_centroid;
4033 else if (location == INTERP_SAMPLE)
4034 return ctx->persp_sample;
4035 break;
4036 case INTERP_MODE_NOPERSPECTIVE:
4037 if (location == INTERP_CENTER)
4038 return ctx->linear_center;
4039 else if (location == INTERP_CENTROID)
4040 return ctx->linear_centroid;
4041 else if (location == INTERP_SAMPLE)
4042 return ctx->linear_sample;
4043 break;
4044 }
4045 return NULL;
4046 }
4047
4048 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
4049 LLVMValueRef sample_id)
4050 {
4051 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4052
4053 LLVMValueRef result;
4054 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false));
4055
4056 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
4057 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
4058
4059 sample_id = LLVMBuildAdd(ctx->ac.builder, sample_id, ctx->sample_pos_offset, "");
4060 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
4061
4062 return result;
4063 }
4064
4065 static LLVMValueRef load_sample_pos(struct ac_nir_context *ctx)
4066 {
4067 LLVMValueRef values[2];
4068
4069 values[0] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[0], 32);
4070 values[1] = emit_ffract(&ctx->ac, ctx->abi->frag_pos[1], 32);
4071 return ac_build_gather_values(&ctx->ac, values, 2);
4072 }
4073
4074 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
4075 {
4076 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4077 uint8_t log2_ps_iter_samples = ctx->shader_info->info.ps.force_persample ?
4078 ctx->options->key.fs.log2_num_samples :
4079 ctx->options->key.fs.log2_ps_iter_samples;
4080
4081 /* The bit pattern matches that used by fixed function fragment
4082 * processing. */
4083 static const uint16_t ps_iter_masks[] = {
4084 0xffff, /* not used */
4085 0x5555,
4086 0x1111,
4087 0x0101,
4088 0x0001,
4089 };
4090 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
4091
4092 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
4093
4094 LLVMValueRef result, sample_id;
4095 sample_id = unpack_param(&ctx->ac, abi->ancillary, 8, 4);
4096 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
4097 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
4098 return result;
4099 }
4100
4101 static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
4102 const nir_intrinsic_instr *instr)
4103 {
4104 LLVMValueRef result[4];
4105 LLVMValueRef interp_param, attr_number;
4106 unsigned location;
4107 unsigned chan;
4108 LLVMValueRef src_c0 = NULL;
4109 LLVMValueRef src_c1 = NULL;
4110 LLVMValueRef src0 = NULL;
4111 int input_index = instr->variables[0]->var->data.location - VARYING_SLOT_VAR0;
4112 switch (instr->intrinsic) {
4113 case nir_intrinsic_interp_var_at_centroid:
4114 location = INTERP_CENTROID;
4115 break;
4116 case nir_intrinsic_interp_var_at_sample:
4117 case nir_intrinsic_interp_var_at_offset:
4118 location = INTERP_CENTER;
4119 src0 = get_src(ctx, instr->src[0]);
4120 break;
4121 default:
4122 break;
4123 }
4124
4125 if (instr->intrinsic == nir_intrinsic_interp_var_at_offset) {
4126 src_c0 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_0, ""));
4127 src_c1 = ac_to_float(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder, src0, ctx->ac.i32_1, ""));
4128 } else if (instr->intrinsic == nir_intrinsic_interp_var_at_sample) {
4129 LLVMValueRef sample_position;
4130 LLVMValueRef halfval = LLVMConstReal(ctx->ac.f32, 0.5f);
4131
4132 /* fetch sample ID */
4133 sample_position = ctx->abi->load_sample_position(ctx->abi, src0);
4134
4135 src_c0 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_0, "");
4136 src_c0 = LLVMBuildFSub(ctx->ac.builder, src_c0, halfval, "");
4137 src_c1 = LLVMBuildExtractElement(ctx->ac.builder, sample_position, ctx->ac.i32_1, "");
4138 src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
4139 }
4140 interp_param = ctx->abi->lookup_interp_param(ctx->abi, instr->variables[0]->var->data.interpolation, location);
4141 attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
4142
4143 if (location == INTERP_CENTER) {
4144 LLVMValueRef ij_out[2];
4145 LLVMValueRef ddxy_out = emit_ddxy_interp(ctx, interp_param);
4146
4147 /*
4148 * take the I then J parameters, and the DDX/Y for it, and
4149 * calculate the IJ inputs for the interpolator.
4150 * temp1 = ddx * offset/sample.x + I;
4151 * interp_param.I = ddy * offset/sample.y + temp1;
4152 * temp1 = ddx * offset/sample.x + J;
4153 * interp_param.J = ddy * offset/sample.y + temp1;
4154 */
4155 for (unsigned i = 0; i < 2; i++) {
4156 LLVMValueRef ix_ll = LLVMConstInt(ctx->ac.i32, i, false);
4157 LLVMValueRef iy_ll = LLVMConstInt(ctx->ac.i32, i + 2, false);
4158 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4159 ddxy_out, ix_ll, "");
4160 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4161 ddxy_out, iy_ll, "");
4162 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4163 interp_param, ix_ll, "");
4164 LLVMValueRef temp1, temp2;
4165
4166 interp_el = LLVMBuildBitCast(ctx->ac.builder, interp_el,
4167 ctx->ac.f32, "");
4168
4169 temp1 = LLVMBuildFMul(ctx->ac.builder, ddx_el, src_c0, "");
4170 temp1 = LLVMBuildFAdd(ctx->ac.builder, temp1, interp_el, "");
4171
4172 temp2 = LLVMBuildFMul(ctx->ac.builder, ddy_el, src_c1, "");
4173 temp2 = LLVMBuildFAdd(ctx->ac.builder, temp2, temp1, "");
4174
4175 ij_out[i] = LLVMBuildBitCast(ctx->ac.builder,
4176 temp2, ctx->ac.i32, "");
4177 }
4178 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4179
4180 }
4181
4182 for (chan = 0; chan < 4; chan++) {
4183 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
4184
4185 if (interp_param) {
4186 interp_param = LLVMBuildBitCast(ctx->ac.builder,
4187 interp_param, ctx->ac.v2f32, "");
4188 LLVMValueRef i = LLVMBuildExtractElement(
4189 ctx->ac.builder, interp_param, ctx->ac.i32_0, "");
4190 LLVMValueRef j = LLVMBuildExtractElement(
4191 ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
4192
4193 result[chan] = ac_build_fs_interp(&ctx->ac,
4194 llvm_chan, attr_number,
4195 ctx->abi->prim_mask, i, j);
4196 } else {
4197 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
4198 LLVMConstInt(ctx->ac.i32, 2, false),
4199 llvm_chan, attr_number,
4200 ctx->abi->prim_mask);
4201 }
4202 }
4203 return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
4204 instr->variables[0]->var->data.location_frac);
4205 }
4206
4207 static void
4208 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
4209 {
4210 LLVMValueRef gs_next_vertex;
4211 LLVMValueRef can_emit;
4212 int idx;
4213 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4214
4215 assert(stream == 0);
4216
4217 /* Write vertex attribute values to GSVS ring */
4218 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4219 ctx->gs_next_vertex,
4220 "");
4221
4222 /* If this thread has already emitted the declared maximum number of
4223 * vertices, kill it: excessive vertex emissions are not supposed to
4224 * have any effect, and GS threads have no externally observable
4225 * effects other than emitting vertices.
4226 */
4227 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4228 LLVMConstInt(ctx->ac.i32, ctx->gs_max_out_vertices, false), "");
4229 ac_build_kill_if_false(&ctx->ac, can_emit);
4230
4231 /* loop num outputs */
4232 idx = 0;
4233 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4234 LLVMValueRef *out_ptr = &addrs[i * 4];
4235 int length = 4;
4236 int slot = idx;
4237 int slot_inc = 1;
4238
4239 if (!(ctx->output_mask & (1ull << i)))
4240 continue;
4241
4242 if (i == VARYING_SLOT_CLIP_DIST0) {
4243 /* pack clip and cull into a single set of slots */
4244 length = ctx->num_output_clips + ctx->num_output_culls;
4245 if (length > 4)
4246 slot_inc = 2;
4247 }
4248 for (unsigned j = 0; j < length; j++) {
4249 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4250 out_ptr[j], "");
4251 LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot * 4 + j) * ctx->gs_max_out_vertices, false);
4252 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4253 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
4254
4255 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4256
4257 ac_build_buffer_store_dword(&ctx->ac, ctx->gsvs_ring,
4258 out_val, 1,
4259 voffset, ctx->gs2vs_offset, 0,
4260 1, 1, true, true);
4261 }
4262 idx += slot_inc;
4263 }
4264
4265 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
4266 ctx->ac.i32_1, "");
4267 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex);
4268
4269 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (0 << 8), ctx->gs_wave_id);
4270 }
4271
4272 static void
4273 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
4274 {
4275 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4276 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
4277 }
4278
4279 static LLVMValueRef
4280 load_tess_coord(struct ac_shader_abi *abi)
4281 {
4282 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4283
4284 LLVMValueRef coord[4] = {
4285 ctx->tes_u,
4286 ctx->tes_v,
4287 ctx->ac.f32_0,
4288 ctx->ac.f32_0,
4289 };
4290
4291 if (ctx->tes_primitive_mode == GL_TRIANGLES)
4292 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
4293 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
4294
4295 return ac_build_gather_values(&ctx->ac, coord, 3);
4296 }
4297
4298 static LLVMValueRef
4299 load_patch_vertices_in(struct ac_shader_abi *abi)
4300 {
4301 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4302 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
4303 }
4304
4305 static void visit_intrinsic(struct ac_nir_context *ctx,
4306 nir_intrinsic_instr *instr)
4307 {
4308 LLVMValueRef result = NULL;
4309
4310 switch (instr->intrinsic) {
4311 case nir_intrinsic_ballot:
4312 result = ac_build_ballot(&ctx->ac, get_src(ctx, instr->src[0]));
4313 break;
4314 case nir_intrinsic_read_invocation:
4315 case nir_intrinsic_read_first_invocation: {
4316 LLVMValueRef args[2];
4317
4318 /* Value */
4319 args[0] = get_src(ctx, instr->src[0]);
4320
4321 unsigned num_args;
4322 const char *intr_name;
4323 if (instr->intrinsic == nir_intrinsic_read_invocation) {
4324 num_args = 2;
4325 intr_name = "llvm.amdgcn.readlane";
4326
4327 /* Invocation */
4328 args[1] = get_src(ctx, instr->src[1]);
4329 } else {
4330 num_args = 1;
4331 intr_name = "llvm.amdgcn.readfirstlane";
4332 }
4333
4334 /* We currently have no other way to prevent LLVM from lifting the icmp
4335 * calls to a dominating basic block.
4336 */
4337 ac_build_optimization_barrier(&ctx->ac, &args[0]);
4338
4339 result = ac_build_intrinsic(&ctx->ac, intr_name,
4340 ctx->ac.i32, args, num_args,
4341 AC_FUNC_ATTR_READNONE |
4342 AC_FUNC_ATTR_CONVERGENT);
4343 break;
4344 }
4345 case nir_intrinsic_load_subgroup_invocation:
4346 result = ac_get_thread_id(&ctx->ac);
4347 break;
4348 case nir_intrinsic_load_work_group_id: {
4349 LLVMValueRef values[3];
4350
4351 for (int i = 0; i < 3; i++) {
4352 values[i] = ctx->abi->workgroup_ids[i] ?
4353 ctx->abi->workgroup_ids[i] : ctx->ac.i32_0;
4354 }
4355
4356 result = ac_build_gather_values(&ctx->ac, values, 3);
4357 break;
4358 }
4359 case nir_intrinsic_load_base_vertex: {
4360 result = ctx->abi->base_vertex;
4361 break;
4362 }
4363 case nir_intrinsic_load_local_group_size:
4364 result = ctx->abi->load_local_group_size(ctx->abi);
4365 break;
4366 case nir_intrinsic_load_vertex_id_zero_base: {
4367 result = ctx->abi->vertex_id;
4368 break;
4369 }
4370 case nir_intrinsic_load_local_invocation_id: {
4371 result = ctx->abi->local_invocation_ids;
4372 break;
4373 }
4374 case nir_intrinsic_load_base_instance:
4375 result = ctx->abi->start_instance;
4376 break;
4377 case nir_intrinsic_load_draw_id:
4378 result = ctx->abi->draw_id;
4379 break;
4380 case nir_intrinsic_load_view_index:
4381 result = ctx->abi->view_index;
4382 break;
4383 case nir_intrinsic_load_invocation_id:
4384 if (ctx->stage == MESA_SHADER_TESS_CTRL)
4385 result = unpack_param(&ctx->ac, ctx->abi->tcs_rel_ids, 8, 5);
4386 else
4387 result = ctx->abi->gs_invocation_id;
4388 break;
4389 case nir_intrinsic_load_primitive_id:
4390 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4391 result = ctx->abi->gs_prim_id;
4392 } else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
4393 result = ctx->abi->tcs_patch_id;
4394 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
4395 result = ctx->abi->tes_patch_id;
4396 } else
4397 fprintf(stderr, "Unknown primitive id intrinsic: %d", ctx->stage);
4398 break;
4399 case nir_intrinsic_load_sample_id:
4400 result = unpack_param(&ctx->ac, ctx->abi->ancillary, 8, 4);
4401 break;
4402 case nir_intrinsic_load_sample_pos:
4403 result = load_sample_pos(ctx);
4404 break;
4405 case nir_intrinsic_load_sample_mask_in:
4406 result = ctx->abi->load_sample_mask_in(ctx->abi);
4407 break;
4408 case nir_intrinsic_load_frag_coord: {
4409 LLVMValueRef values[4] = {
4410 ctx->abi->frag_pos[0],
4411 ctx->abi->frag_pos[1],
4412 ctx->abi->frag_pos[2],
4413 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, ctx->abi->frag_pos[3])
4414 };
4415 result = ac_build_gather_values(&ctx->ac, values, 4);
4416 break;
4417 }
4418 case nir_intrinsic_load_front_face:
4419 result = ctx->abi->front_face;
4420 break;
4421 case nir_intrinsic_load_helper_invocation:
4422 result = visit_load_helper_invocation(ctx);
4423 break;
4424 case nir_intrinsic_load_instance_id:
4425 result = ctx->abi->instance_id;
4426 break;
4427 case nir_intrinsic_load_num_work_groups:
4428 result = ctx->abi->num_work_groups;
4429 break;
4430 case nir_intrinsic_load_local_invocation_index:
4431 result = visit_load_local_invocation_index(ctx);
4432 break;
4433 case nir_intrinsic_load_push_constant:
4434 result = visit_load_push_constant(ctx, instr);
4435 break;
4436 case nir_intrinsic_vulkan_resource_index: {
4437 LLVMValueRef index = get_src(ctx, instr->src[0]);
4438 unsigned desc_set = nir_intrinsic_desc_set(instr);
4439 unsigned binding = nir_intrinsic_binding(instr);
4440
4441 result = ctx->abi->load_resource(ctx->abi, index, desc_set,
4442 binding);
4443 break;
4444 }
4445 case nir_intrinsic_vulkan_resource_reindex:
4446 result = visit_vulkan_resource_reindex(ctx, instr);
4447 break;
4448 case nir_intrinsic_store_ssbo:
4449 visit_store_ssbo(ctx, instr);
4450 break;
4451 case nir_intrinsic_load_ssbo:
4452 result = visit_load_buffer(ctx, instr);
4453 break;
4454 case nir_intrinsic_ssbo_atomic_add:
4455 case nir_intrinsic_ssbo_atomic_imin:
4456 case nir_intrinsic_ssbo_atomic_umin:
4457 case nir_intrinsic_ssbo_atomic_imax:
4458 case nir_intrinsic_ssbo_atomic_umax:
4459 case nir_intrinsic_ssbo_atomic_and:
4460 case nir_intrinsic_ssbo_atomic_or:
4461 case nir_intrinsic_ssbo_atomic_xor:
4462 case nir_intrinsic_ssbo_atomic_exchange:
4463 case nir_intrinsic_ssbo_atomic_comp_swap:
4464 result = visit_atomic_ssbo(ctx, instr);
4465 break;
4466 case nir_intrinsic_load_ubo:
4467 result = visit_load_ubo_buffer(ctx, instr);
4468 break;
4469 case nir_intrinsic_get_buffer_size:
4470 result = visit_get_buffer_size(ctx, instr);
4471 break;
4472 case nir_intrinsic_load_var:
4473 result = visit_load_var(ctx, instr);
4474 break;
4475 case nir_intrinsic_store_var:
4476 visit_store_var(ctx, instr);
4477 break;
4478 case nir_intrinsic_load_shared:
4479 result = visit_load_shared(ctx, instr);
4480 break;
4481 case nir_intrinsic_store_shared:
4482 visit_store_shared(ctx, instr);
4483 break;
4484 case nir_intrinsic_image_load:
4485 result = visit_image_load(ctx, instr);
4486 break;
4487 case nir_intrinsic_image_store:
4488 visit_image_store(ctx, instr);
4489 break;
4490 case nir_intrinsic_image_atomic_add:
4491 case nir_intrinsic_image_atomic_min:
4492 case nir_intrinsic_image_atomic_max:
4493 case nir_intrinsic_image_atomic_and:
4494 case nir_intrinsic_image_atomic_or:
4495 case nir_intrinsic_image_atomic_xor:
4496 case nir_intrinsic_image_atomic_exchange:
4497 case nir_intrinsic_image_atomic_comp_swap:
4498 result = visit_image_atomic(ctx, instr);
4499 break;
4500 case nir_intrinsic_image_size:
4501 result = visit_image_size(ctx, instr);
4502 break;
4503 case nir_intrinsic_shader_clock:
4504 result = ac_build_shader_clock(&ctx->ac);
4505 break;
4506 case nir_intrinsic_discard:
4507 case nir_intrinsic_discard_if:
4508 emit_discard(ctx, instr);
4509 break;
4510 case nir_intrinsic_memory_barrier:
4511 case nir_intrinsic_group_memory_barrier:
4512 case nir_intrinsic_memory_barrier_atomic_counter:
4513 case nir_intrinsic_memory_barrier_buffer:
4514 case nir_intrinsic_memory_barrier_image:
4515 case nir_intrinsic_memory_barrier_shared:
4516 emit_membar(&ctx->ac, instr);
4517 break;
4518 case nir_intrinsic_barrier:
4519 emit_barrier(&ctx->ac, ctx->stage);
4520 break;
4521 case nir_intrinsic_shared_atomic_add:
4522 case nir_intrinsic_shared_atomic_imin:
4523 case nir_intrinsic_shared_atomic_umin:
4524 case nir_intrinsic_shared_atomic_imax:
4525 case nir_intrinsic_shared_atomic_umax:
4526 case nir_intrinsic_shared_atomic_and:
4527 case nir_intrinsic_shared_atomic_or:
4528 case nir_intrinsic_shared_atomic_xor:
4529 case nir_intrinsic_shared_atomic_exchange:
4530 case nir_intrinsic_shared_atomic_comp_swap: {
4531 LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
4532 result = visit_var_atomic(ctx, instr, ptr);
4533 break;
4534 }
4535 case nir_intrinsic_var_atomic_add:
4536 case nir_intrinsic_var_atomic_imin:
4537 case nir_intrinsic_var_atomic_umin:
4538 case nir_intrinsic_var_atomic_imax:
4539 case nir_intrinsic_var_atomic_umax:
4540 case nir_intrinsic_var_atomic_and:
4541 case nir_intrinsic_var_atomic_or:
4542 case nir_intrinsic_var_atomic_xor:
4543 case nir_intrinsic_var_atomic_exchange:
4544 case nir_intrinsic_var_atomic_comp_swap: {
4545 LLVMValueRef ptr = build_gep_for_deref(ctx, instr->variables[0]);
4546 result = visit_var_atomic(ctx, instr, ptr);
4547 break;
4548 }
4549 case nir_intrinsic_interp_var_at_centroid:
4550 case nir_intrinsic_interp_var_at_sample:
4551 case nir_intrinsic_interp_var_at_offset:
4552 result = visit_interp(ctx, instr);
4553 break;
4554 case nir_intrinsic_emit_vertex:
4555 ctx->abi->emit_vertex(ctx->abi, nir_intrinsic_stream_id(instr), ctx->abi->outputs);
4556 break;
4557 case nir_intrinsic_end_primitive:
4558 ctx->abi->emit_primitive(ctx->abi, nir_intrinsic_stream_id(instr));
4559 break;
4560 case nir_intrinsic_load_tess_coord:
4561 result = ctx->abi->load_tess_coord(ctx->abi);
4562 break;
4563 case nir_intrinsic_load_tess_level_outer:
4564 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_OUTER);
4565 break;
4566 case nir_intrinsic_load_tess_level_inner:
4567 result = ctx->abi->load_tess_level(ctx->abi, VARYING_SLOT_TESS_LEVEL_INNER);
4568 break;
4569 case nir_intrinsic_load_patch_vertices_in:
4570 result = ctx->abi->load_patch_vertices_in(ctx->abi);
4571 break;
4572 case nir_intrinsic_vote_all: {
4573 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, get_src(ctx, instr->src[0]));
4574 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4575 break;
4576 }
4577 case nir_intrinsic_vote_any: {
4578 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, get_src(ctx, instr->src[0]));
4579 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4580 break;
4581 }
4582 case nir_intrinsic_vote_eq: {
4583 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, get_src(ctx, instr->src[0]));
4584 result = LLVMBuildSExt(ctx->ac.builder, tmp, ctx->ac.i32, "");
4585 break;
4586 }
4587 default:
4588 fprintf(stderr, "Unknown intrinsic: ");
4589 nir_print_instr(&instr->instr, stderr);
4590 fprintf(stderr, "\n");
4591 break;
4592 }
4593 if (result) {
4594 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
4595 }
4596 }
4597
4598 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
4599 LLVMValueRef buffer_ptr, bool write)
4600 {
4601 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4602 LLVMValueRef result;
4603
4604 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4605
4606 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4607 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4608
4609 return result;
4610 }
4611
4612 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
4613 {
4614 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4615 LLVMValueRef result;
4616
4617 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
4618
4619 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
4620 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
4621
4622 return result;
4623 }
4624
4625 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
4626 unsigned descriptor_set,
4627 unsigned base_index,
4628 unsigned constant_index,
4629 LLVMValueRef index,
4630 enum ac_descriptor_type desc_type,
4631 bool image, bool write)
4632 {
4633 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
4634 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
4635 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
4636 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
4637 unsigned offset = binding->offset;
4638 unsigned stride = binding->size;
4639 unsigned type_size;
4640 LLVMBuilderRef builder = ctx->ac.builder;
4641 LLVMTypeRef type;
4642
4643 assert(base_index < layout->binding_count);
4644
4645 switch (desc_type) {
4646 case AC_DESC_IMAGE:
4647 type = ctx->ac.v8i32;
4648 type_size = 32;
4649 break;
4650 case AC_DESC_FMASK:
4651 type = ctx->ac.v8i32;
4652 offset += 32;
4653 type_size = 32;
4654 break;
4655 case AC_DESC_SAMPLER:
4656 type = ctx->ac.v4i32;
4657 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER)
4658 offset += 64;
4659
4660 type_size = 16;
4661 break;
4662 case AC_DESC_BUFFER:
4663 type = ctx->ac.v4i32;
4664 type_size = 16;
4665 break;
4666 default:
4667 unreachable("invalid desc_type\n");
4668 }
4669
4670 offset += constant_index * stride;
4671
4672 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
4673 (!index || binding->immutable_samplers_equal)) {
4674 if (binding->immutable_samplers_equal)
4675 constant_index = 0;
4676
4677 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
4678
4679 LLVMValueRef constants[] = {
4680 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
4681 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
4682 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
4683 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
4684 };
4685 return ac_build_gather_values(&ctx->ac, constants, 4);
4686 }
4687
4688 assert(stride % type_size == 0);
4689
4690 if (!index)
4691 index = ctx->ac.i32_0;
4692
4693 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
4694
4695 list = ac_build_gep0(&ctx->ac, list, LLVMConstInt(ctx->ac.i32, offset, 0));
4696 list = LLVMBuildPointerCast(builder, list, ac_array_in_const_addr_space(type), "");
4697
4698 return ac_build_load_to_sgpr(&ctx->ac, list, index);
4699 }
4700
4701 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
4702 const nir_deref_var *deref,
4703 enum ac_descriptor_type desc_type,
4704 const nir_tex_instr *tex_instr,
4705 bool image, bool write)
4706 {
4707 LLVMValueRef index = NULL;
4708 unsigned constant_index = 0;
4709 unsigned descriptor_set;
4710 unsigned base_index;
4711
4712 if (!deref) {
4713 assert(tex_instr && !image);
4714 descriptor_set = 0;
4715 base_index = tex_instr->sampler_index;
4716 } else {
4717 const nir_deref *tail = &deref->deref;
4718 while (tail->child) {
4719 const nir_deref_array *child = nir_deref_as_array(tail->child);
4720 unsigned array_size = glsl_get_aoa_size(tail->child->type);
4721
4722 if (!array_size)
4723 array_size = 1;
4724
4725 assert(child->deref_array_type != nir_deref_array_type_wildcard);
4726
4727 if (child->deref_array_type == nir_deref_array_type_indirect) {
4728 LLVMValueRef indirect = get_src(ctx, child->indirect);
4729
4730 indirect = LLVMBuildMul(ctx->ac.builder, indirect,
4731 LLVMConstInt(ctx->ac.i32, array_size, false), "");
4732
4733 if (!index)
4734 index = indirect;
4735 else
4736 index = LLVMBuildAdd(ctx->ac.builder, index, indirect, "");
4737 }
4738
4739 constant_index += child->base_offset * array_size;
4740
4741 tail = &child->deref;
4742 }
4743 descriptor_set = deref->var->data.descriptor_set;
4744 base_index = deref->var->data.binding;
4745 }
4746
4747 return ctx->abi->load_sampler_desc(ctx->abi,
4748 descriptor_set,
4749 base_index,
4750 constant_index, index,
4751 desc_type, image, write);
4752 }
4753
4754 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
4755 struct ac_image_args *args,
4756 const nir_tex_instr *instr,
4757 nir_texop op,
4758 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4759 LLVMValueRef *param, unsigned count,
4760 unsigned dmask)
4761 {
4762 unsigned is_rect = 0;
4763 bool da = instr->is_array || instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE;
4764
4765 if (op == nir_texop_lod)
4766 da = false;
4767 /* Pad to power of two vector */
4768 while (count < util_next_power_of_two(count))
4769 param[count++] = LLVMGetUndef(ctx->i32);
4770
4771 if (count > 1)
4772 args->addr = ac_build_gather_values(ctx, param, count);
4773 else
4774 args->addr = param[0];
4775
4776 args->resource = res_ptr;
4777 args->sampler = samp_ptr;
4778
4779 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF && op == nir_texop_txf) {
4780 args->addr = param[0];
4781 return;
4782 }
4783
4784 args->dmask = dmask;
4785 args->unorm = is_rect;
4786 args->da = da;
4787 }
4788
4789 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4790 *
4791 * SI-CI:
4792 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4793 * filtering manually. The driver sets img7 to a mask clearing
4794 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4795 * s_and_b32 samp0, samp0, img7
4796 *
4797 * VI:
4798 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4799 */
4800 static LLVMValueRef sici_fix_sampler_aniso(struct ac_nir_context *ctx,
4801 LLVMValueRef res, LLVMValueRef samp)
4802 {
4803 LLVMBuilderRef builder = ctx->ac.builder;
4804 LLVMValueRef img7, samp0;
4805
4806 if (ctx->ac.chip_class >= VI)
4807 return samp;
4808
4809 img7 = LLVMBuildExtractElement(builder, res,
4810 LLVMConstInt(ctx->ac.i32, 7, 0), "");
4811 samp0 = LLVMBuildExtractElement(builder, samp,
4812 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4813 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4814 return LLVMBuildInsertElement(builder, samp, samp0,
4815 LLVMConstInt(ctx->ac.i32, 0, 0), "");
4816 }
4817
4818 static void tex_fetch_ptrs(struct ac_nir_context *ctx,
4819 nir_tex_instr *instr,
4820 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
4821 LLVMValueRef *fmask_ptr)
4822 {
4823 if (instr->sampler_dim == GLSL_SAMPLER_DIM_BUF)
4824 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_BUFFER, instr, false, false);
4825 else
4826 *res_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_IMAGE, instr, false, false);
4827 if (samp_ptr) {
4828 if (instr->sampler)
4829 *samp_ptr = get_sampler_desc(ctx, instr->sampler, AC_DESC_SAMPLER, instr, false, false);
4830 else
4831 *samp_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_SAMPLER, instr, false, false);
4832 if (instr->sampler_dim < GLSL_SAMPLER_DIM_RECT)
4833 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4834 }
4835 if (fmask_ptr && !instr->sampler && (instr->op == nir_texop_txf_ms ||
4836 instr->op == nir_texop_samples_identical))
4837 *fmask_ptr = get_sampler_desc(ctx, instr->texture, AC_DESC_FMASK, instr, false, false);
4838 }
4839
4840 static LLVMValueRef apply_round_slice(struct ac_llvm_context *ctx,
4841 LLVMValueRef coord)
4842 {
4843 coord = ac_to_float(ctx, coord);
4844 coord = ac_build_intrinsic(ctx, "llvm.rint.f32", ctx->f32, &coord, 1, 0);
4845 coord = ac_to_integer(ctx, coord);
4846 return coord;
4847 }
4848
4849 static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
4850 {
4851 LLVMValueRef result = NULL;
4852 struct ac_image_args args = { 0 };
4853 unsigned dmask = 0xf;
4854 LLVMValueRef address[16];
4855 LLVMValueRef coords[5];
4856 LLVMValueRef coord = NULL, lod = NULL, comparator = NULL;
4857 LLVMValueRef bias = NULL, offsets = NULL;
4858 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL, sample_index = NULL;
4859 LLVMValueRef ddx = NULL, ddy = NULL;
4860 LLVMValueRef derivs[6];
4861 unsigned chan, count = 0;
4862 unsigned const_src = 0, num_deriv_comp = 0;
4863 bool lod_is_zero = false;
4864
4865 tex_fetch_ptrs(ctx, instr, &res_ptr, &samp_ptr, &fmask_ptr);
4866
4867 for (unsigned i = 0; i < instr->num_srcs; i++) {
4868 switch (instr->src[i].src_type) {
4869 case nir_tex_src_coord:
4870 coord = get_src(ctx, instr->src[i].src);
4871 break;
4872 case nir_tex_src_projector:
4873 break;
4874 case nir_tex_src_comparator:
4875 comparator = get_src(ctx, instr->src[i].src);
4876 break;
4877 case nir_tex_src_offset:
4878 offsets = get_src(ctx, instr->src[i].src);
4879 const_src = i;
4880 break;
4881 case nir_tex_src_bias:
4882 bias = get_src(ctx, instr->src[i].src);
4883 break;
4884 case nir_tex_src_lod: {
4885 nir_const_value *val = nir_src_as_const_value(instr->src[i].src);
4886
4887 if (val && val->i32[0] == 0)
4888 lod_is_zero = true;
4889 lod = get_src(ctx, instr->src[i].src);
4890 break;
4891 }
4892 case nir_tex_src_ms_index:
4893 sample_index = get_src(ctx, instr->src[i].src);
4894 break;
4895 case nir_tex_src_ms_mcs:
4896 break;
4897 case nir_tex_src_ddx:
4898 ddx = get_src(ctx, instr->src[i].src);
4899 num_deriv_comp = instr->src[i].src.ssa->num_components;
4900 break;
4901 case nir_tex_src_ddy:
4902 ddy = get_src(ctx, instr->src[i].src);
4903 break;
4904 case nir_tex_src_texture_offset:
4905 case nir_tex_src_sampler_offset:
4906 case nir_tex_src_plane:
4907 default:
4908 break;
4909 }
4910 }
4911
4912 if (instr->op == nir_texop_txs && instr->sampler_dim == GLSL_SAMPLER_DIM_BUF) {
4913 result = get_buffer_size(ctx, res_ptr, true);
4914 goto write_result;
4915 }
4916
4917 if (instr->op == nir_texop_texture_samples) {
4918 LLVMValueRef res, samples, is_msaa;
4919 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->ac.v8i32, "");
4920 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
4921 LLVMConstInt(ctx->ac.i32, 3, false), "");
4922 is_msaa = LLVMBuildLShr(ctx->ac.builder, samples,
4923 LLVMConstInt(ctx->ac.i32, 28, false), "");
4924 is_msaa = LLVMBuildAnd(ctx->ac.builder, is_msaa,
4925 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4926 is_msaa = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, is_msaa,
4927 LLVMConstInt(ctx->ac.i32, 0xe, false), "");
4928
4929 samples = LLVMBuildLShr(ctx->ac.builder, samples,
4930 LLVMConstInt(ctx->ac.i32, 16, false), "");
4931 samples = LLVMBuildAnd(ctx->ac.builder, samples,
4932 LLVMConstInt(ctx->ac.i32, 0xf, false), "");
4933 samples = LLVMBuildShl(ctx->ac.builder, ctx->ac.i32_1,
4934 samples, "");
4935 samples = LLVMBuildSelect(ctx->ac.builder, is_msaa, samples,
4936 ctx->ac.i32_1, "");
4937 result = samples;
4938 goto write_result;
4939 }
4940
4941 if (coord)
4942 for (chan = 0; chan < instr->coord_components; chan++)
4943 coords[chan] = ac_llvm_extract_elem(&ctx->ac, coord, chan);
4944
4945 if (offsets && instr->op != nir_texop_txf) {
4946 LLVMValueRef offset[3], pack;
4947 for (chan = 0; chan < 3; ++chan)
4948 offset[chan] = ctx->ac.i32_0;
4949
4950 args.offset = true;
4951 for (chan = 0; chan < ac_get_llvm_num_components(offsets); chan++) {
4952 offset[chan] = ac_llvm_extract_elem(&ctx->ac, offsets, chan);
4953 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
4954 LLVMConstInt(ctx->ac.i32, 0x3f, false), "");
4955 if (chan)
4956 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
4957 LLVMConstInt(ctx->ac.i32, chan * 8, false), "");
4958 }
4959 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
4960 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
4961 address[count++] = pack;
4962
4963 }
4964 /* pack LOD bias value */
4965 if (instr->op == nir_texop_txb && bias) {
4966 address[count++] = bias;
4967 }
4968
4969 /* Pack depth comparison value */
4970 if (instr->is_shadow && comparator) {
4971 LLVMValueRef z = ac_to_float(&ctx->ac,
4972 ac_llvm_extract_elem(&ctx->ac, comparator, 0));
4973
4974 /* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
4975 * so the depth comparison value isn't clamped for Z16 and
4976 * Z24 anymore. Do it manually here.
4977 *
4978 * It's unnecessary if the original texture format was
4979 * Z32_FLOAT, but we don't know that here.
4980 */
4981 if (ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
4982 z = ac_build_clamp(&ctx->ac, z);
4983
4984 address[count++] = z;
4985 }
4986
4987 /* pack derivatives */
4988 if (ddx || ddy) {
4989 int num_src_deriv_channels, num_dest_deriv_channels;
4990 switch (instr->sampler_dim) {
4991 case GLSL_SAMPLER_DIM_3D:
4992 case GLSL_SAMPLER_DIM_CUBE:
4993 num_deriv_comp = 3;
4994 num_src_deriv_channels = 3;
4995 num_dest_deriv_channels = 3;
4996 break;
4997 case GLSL_SAMPLER_DIM_2D:
4998 default:
4999 num_src_deriv_channels = 2;
5000 num_dest_deriv_channels = 2;
5001 num_deriv_comp = 2;
5002 break;
5003 case GLSL_SAMPLER_DIM_1D:
5004 num_src_deriv_channels = 1;
5005 if (ctx->ac.chip_class >= GFX9) {
5006 num_dest_deriv_channels = 2;
5007 num_deriv_comp = 2;
5008 } else {
5009 num_dest_deriv_channels = 1;
5010 num_deriv_comp = 1;
5011 }
5012 break;
5013 }
5014
5015 for (unsigned i = 0; i < num_src_deriv_channels; i++) {
5016 derivs[i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddx, i));
5017 derivs[num_dest_deriv_channels + i] = ac_to_float(&ctx->ac, ac_llvm_extract_elem(&ctx->ac, ddy, i));
5018 }
5019 for (unsigned i = num_src_deriv_channels; i < num_dest_deriv_channels; i++) {
5020 derivs[i] = ctx->ac.f32_0;
5021 derivs[num_dest_deriv_channels + i] = ctx->ac.f32_0;
5022 }
5023 }
5024
5025 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && coord) {
5026 for (chan = 0; chan < instr->coord_components; chan++)
5027 coords[chan] = ac_to_float(&ctx->ac, coords[chan]);
5028 if (instr->coord_components == 3)
5029 coords[3] = LLVMGetUndef(ctx->ac.f32);
5030 ac_prepare_cube_coords(&ctx->ac,
5031 instr->op == nir_texop_txd, instr->is_array,
5032 instr->op == nir_texop_lod, coords, derivs);
5033 if (num_deriv_comp)
5034 num_deriv_comp--;
5035 }
5036
5037 if (ddx || ddy) {
5038 for (unsigned i = 0; i < num_deriv_comp * 2; i++)
5039 address[count++] = derivs[i];
5040 }
5041
5042 /* Pack texture coordinates */
5043 if (coord) {
5044 address[count++] = coords[0];
5045 if (instr->coord_components > 1) {
5046 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D && instr->is_array && instr->op != nir_texop_txf) {
5047 coords[1] = apply_round_slice(&ctx->ac, coords[1]);
5048 }
5049 address[count++] = coords[1];
5050 }
5051 if (instr->coord_components > 2) {
5052 /* This seems like a bit of a hack - but it passes Vulkan CTS with it */
5053 if (instr->sampler_dim != GLSL_SAMPLER_DIM_3D &&
5054 instr->sampler_dim != GLSL_SAMPLER_DIM_CUBE &&
5055 instr->op != nir_texop_txf) {
5056 coords[2] = apply_round_slice(&ctx->ac, coords[2]);
5057 }
5058 address[count++] = coords[2];
5059 }
5060
5061 if (ctx->ac.chip_class >= GFX9) {
5062 LLVMValueRef filler;
5063 if (instr->op == nir_texop_txf)
5064 filler = ctx->ac.i32_0;
5065 else
5066 filler = LLVMConstReal(ctx->ac.f32, 0.5);
5067
5068 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D) {
5069 /* No nir_texop_lod, because it does not take a slice
5070 * even with array textures. */
5071 if (instr->is_array && instr->op != nir_texop_lod ) {
5072 address[count] = address[count - 1];
5073 address[count - 1] = filler;
5074 count++;
5075 } else
5076 address[count++] = filler;
5077 }
5078 }
5079 }
5080
5081 /* Pack LOD */
5082 if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
5083 instr->op == nir_texop_txf)) {
5084 address[count++] = lod;
5085 } else if (instr->op == nir_texop_txf_ms && sample_index) {
5086 address[count++] = sample_index;
5087 } else if(instr->op == nir_texop_txs) {
5088 count = 0;
5089 if (lod)
5090 address[count++] = lod;
5091 else
5092 address[count++] = ctx->ac.i32_0;
5093 }
5094
5095 for (chan = 0; chan < count; chan++) {
5096 address[chan] = LLVMBuildBitCast(ctx->ac.builder,
5097 address[chan], ctx->ac.i32, "");
5098 }
5099
5100 if (instr->op == nir_texop_samples_identical) {
5101 LLVMValueRef txf_address[4];
5102 struct ac_image_args txf_args = { 0 };
5103 unsigned txf_count = count;
5104 memcpy(txf_address, address, sizeof(txf_address));
5105
5106 if (!instr->is_array)
5107 txf_address[2] = ctx->ac.i32_0;
5108 txf_address[3] = ctx->ac.i32_0;
5109
5110 set_tex_fetch_args(&ctx->ac, &txf_args, instr, nir_texop_txf,
5111 fmask_ptr, NULL,
5112 txf_address, txf_count, 0xf);
5113
5114 result = build_tex_intrinsic(ctx, instr, false, &txf_args);
5115
5116 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5117 result = emit_int_cmp(&ctx->ac, LLVMIntEQ, result, ctx->ac.i32_0);
5118 goto write_result;
5119 }
5120
5121 if (instr->sampler_dim == GLSL_SAMPLER_DIM_MS &&
5122 instr->op != nir_texop_txs) {
5123 unsigned sample_chan = instr->is_array ? 3 : 2;
5124 address[sample_chan] = adjust_sample_index_using_fmask(&ctx->ac,
5125 address[0],
5126 address[1],
5127 instr->is_array ? address[2] : NULL,
5128 address[sample_chan],
5129 fmask_ptr);
5130 }
5131
5132 if (offsets && instr->op == nir_texop_txf) {
5133 nir_const_value *const_offset =
5134 nir_src_as_const_value(instr->src[const_src].src);
5135 int num_offsets = instr->src[const_src].src.ssa->num_components;
5136 assert(const_offset);
5137 num_offsets = MIN2(num_offsets, instr->coord_components);
5138 if (num_offsets > 2)
5139 address[2] = LLVMBuildAdd(ctx->ac.builder,
5140 address[2], LLVMConstInt(ctx->ac.i32, const_offset->i32[2], false), "");
5141 if (num_offsets > 1)
5142 address[1] = LLVMBuildAdd(ctx->ac.builder,
5143 address[1], LLVMConstInt(ctx->ac.i32, const_offset->i32[1], false), "");
5144 address[0] = LLVMBuildAdd(ctx->ac.builder,
5145 address[0], LLVMConstInt(ctx->ac.i32, const_offset->i32[0], false), "");
5146
5147 }
5148
5149 /* TODO TG4 support */
5150 if (instr->op == nir_texop_tg4) {
5151 if (instr->is_shadow)
5152 dmask = 1;
5153 else
5154 dmask = 1 << instr->component;
5155 }
5156 set_tex_fetch_args(&ctx->ac, &args, instr, instr->op,
5157 res_ptr, samp_ptr, address, count, dmask);
5158
5159 result = build_tex_intrinsic(ctx, instr, lod_is_zero, &args);
5160
5161 if (instr->op == nir_texop_query_levels)
5162 result = LLVMBuildExtractElement(ctx->ac.builder, result, LLVMConstInt(ctx->ac.i32, 3, false), "");
5163 else if (instr->is_shadow && instr->is_new_style_shadow &&
5164 instr->op != nir_texop_txs && instr->op != nir_texop_lod &&
5165 instr->op != nir_texop_tg4)
5166 result = LLVMBuildExtractElement(ctx->ac.builder, result, ctx->ac.i32_0, "");
5167 else if (instr->op == nir_texop_txs &&
5168 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
5169 instr->is_array) {
5170 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5171 LLVMValueRef six = LLVMConstInt(ctx->ac.i32, 6, false);
5172 LLVMValueRef z = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5173 z = LLVMBuildSDiv(ctx->ac.builder, z, six, "");
5174 result = LLVMBuildInsertElement(ctx->ac.builder, result, z, two, "");
5175 } else if (ctx->ac.chip_class >= GFX9 &&
5176 instr->op == nir_texop_txs &&
5177 instr->sampler_dim == GLSL_SAMPLER_DIM_1D &&
5178 instr->is_array) {
5179 LLVMValueRef two = LLVMConstInt(ctx->ac.i32, 2, false);
5180 LLVMValueRef layers = LLVMBuildExtractElement(ctx->ac.builder, result, two, "");
5181 result = LLVMBuildInsertElement(ctx->ac.builder, result, layers,
5182 ctx->ac.i32_1, "");
5183 } else if (instr->dest.ssa.num_components != 4)
5184 result = trim_vector(&ctx->ac, result, instr->dest.ssa.num_components);
5185
5186 write_result:
5187 if (result) {
5188 assert(instr->dest.is_ssa);
5189 result = ac_to_integer(&ctx->ac, result);
5190 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5191 }
5192 }
5193
5194
5195 static void visit_phi(struct ac_nir_context *ctx, nir_phi_instr *instr)
5196 {
5197 LLVMTypeRef type = get_def_type(ctx, &instr->dest.ssa);
5198 LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
5199
5200 _mesa_hash_table_insert(ctx->defs, &instr->dest.ssa, result);
5201 _mesa_hash_table_insert(ctx->phis, instr, result);
5202 }
5203
5204 static void visit_post_phi(struct ac_nir_context *ctx,
5205 nir_phi_instr *instr,
5206 LLVMValueRef llvm_phi)
5207 {
5208 nir_foreach_phi_src(src, instr) {
5209 LLVMBasicBlockRef block = get_block(ctx, src->pred);
5210 LLVMValueRef llvm_src = get_src(ctx, src->src);
5211
5212 LLVMAddIncoming(llvm_phi, &llvm_src, &block, 1);
5213 }
5214 }
5215
5216 static void phi_post_pass(struct ac_nir_context *ctx)
5217 {
5218 struct hash_entry *entry;
5219 hash_table_foreach(ctx->phis, entry) {
5220 visit_post_phi(ctx, (nir_phi_instr*)entry->key,
5221 (LLVMValueRef)entry->data);
5222 }
5223 }
5224
5225
5226 static void visit_ssa_undef(struct ac_nir_context *ctx,
5227 const nir_ssa_undef_instr *instr)
5228 {
5229 unsigned num_components = instr->def.num_components;
5230 LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, instr->def.bit_size);
5231 LLVMValueRef undef;
5232
5233 if (num_components == 1)
5234 undef = LLVMGetUndef(type);
5235 else {
5236 undef = LLVMGetUndef(LLVMVectorType(type, num_components));
5237 }
5238 _mesa_hash_table_insert(ctx->defs, &instr->def, undef);
5239 }
5240
5241 static void visit_jump(struct ac_nir_context *ctx,
5242 const nir_jump_instr *instr)
5243 {
5244 switch (instr->type) {
5245 case nir_jump_break:
5246 LLVMBuildBr(ctx->ac.builder, ctx->break_block);
5247 LLVMClearInsertionPosition(ctx->ac.builder);
5248 break;
5249 case nir_jump_continue:
5250 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5251 LLVMClearInsertionPosition(ctx->ac.builder);
5252 break;
5253 default:
5254 fprintf(stderr, "Unknown NIR jump instr: ");
5255 nir_print_instr(&instr->instr, stderr);
5256 fprintf(stderr, "\n");
5257 abort();
5258 }
5259 }
5260
5261 static void visit_cf_list(struct ac_nir_context *ctx,
5262 struct exec_list *list);
5263
5264 static void visit_block(struct ac_nir_context *ctx, nir_block *block)
5265 {
5266 LLVMBasicBlockRef llvm_block = LLVMGetInsertBlock(ctx->ac.builder);
5267 nir_foreach_instr(instr, block)
5268 {
5269 switch (instr->type) {
5270 case nir_instr_type_alu:
5271 visit_alu(ctx, nir_instr_as_alu(instr));
5272 break;
5273 case nir_instr_type_load_const:
5274 visit_load_const(ctx, nir_instr_as_load_const(instr));
5275 break;
5276 case nir_instr_type_intrinsic:
5277 visit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
5278 break;
5279 case nir_instr_type_tex:
5280 visit_tex(ctx, nir_instr_as_tex(instr));
5281 break;
5282 case nir_instr_type_phi:
5283 visit_phi(ctx, nir_instr_as_phi(instr));
5284 break;
5285 case nir_instr_type_ssa_undef:
5286 visit_ssa_undef(ctx, nir_instr_as_ssa_undef(instr));
5287 break;
5288 case nir_instr_type_jump:
5289 visit_jump(ctx, nir_instr_as_jump(instr));
5290 break;
5291 default:
5292 fprintf(stderr, "Unknown NIR instr type: ");
5293 nir_print_instr(instr, stderr);
5294 fprintf(stderr, "\n");
5295 abort();
5296 }
5297 }
5298
5299 _mesa_hash_table_insert(ctx->defs, block, llvm_block);
5300 }
5301
5302 static void visit_if(struct ac_nir_context *ctx, nir_if *if_stmt)
5303 {
5304 LLVMValueRef value = get_src(ctx, if_stmt->condition);
5305
5306 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5307 LLVMBasicBlockRef merge_block =
5308 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5309 LLVMBasicBlockRef if_block =
5310 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5311 LLVMBasicBlockRef else_block = merge_block;
5312 if (!exec_list_is_empty(&if_stmt->else_list))
5313 else_block = LLVMAppendBasicBlockInContext(
5314 ctx->ac.context, fn, "");
5315
5316 LLVMValueRef cond = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE, value,
5317 ctx->ac.i32_0, "");
5318 LLVMBuildCondBr(ctx->ac.builder, cond, if_block, else_block);
5319
5320 LLVMPositionBuilderAtEnd(ctx->ac.builder, if_block);
5321 visit_cf_list(ctx, &if_stmt->then_list);
5322 if (LLVMGetInsertBlock(ctx->ac.builder))
5323 LLVMBuildBr(ctx->ac.builder, merge_block);
5324
5325 if (!exec_list_is_empty(&if_stmt->else_list)) {
5326 LLVMPositionBuilderAtEnd(ctx->ac.builder, else_block);
5327 visit_cf_list(ctx, &if_stmt->else_list);
5328 if (LLVMGetInsertBlock(ctx->ac.builder))
5329 LLVMBuildBr(ctx->ac.builder, merge_block);
5330 }
5331
5332 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
5333 }
5334
5335 static void visit_loop(struct ac_nir_context *ctx, nir_loop *loop)
5336 {
5337 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
5338 LLVMBasicBlockRef continue_parent = ctx->continue_block;
5339 LLVMBasicBlockRef break_parent = ctx->break_block;
5340
5341 ctx->continue_block =
5342 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5343 ctx->break_block =
5344 LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
5345
5346 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5347 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->continue_block);
5348 visit_cf_list(ctx, &loop->body);
5349
5350 if (LLVMGetInsertBlock(ctx->ac.builder))
5351 LLVMBuildBr(ctx->ac.builder, ctx->continue_block);
5352 LLVMPositionBuilderAtEnd(ctx->ac.builder, ctx->break_block);
5353
5354 ctx->continue_block = continue_parent;
5355 ctx->break_block = break_parent;
5356 }
5357
5358 static void visit_cf_list(struct ac_nir_context *ctx,
5359 struct exec_list *list)
5360 {
5361 foreach_list_typed(nir_cf_node, node, node, list)
5362 {
5363 switch (node->type) {
5364 case nir_cf_node_block:
5365 visit_block(ctx, nir_cf_node_as_block(node));
5366 break;
5367
5368 case nir_cf_node_if:
5369 visit_if(ctx, nir_cf_node_as_if(node));
5370 break;
5371
5372 case nir_cf_node_loop:
5373 visit_loop(ctx, nir_cf_node_as_loop(node));
5374 break;
5375
5376 default:
5377 assert(0);
5378 }
5379 }
5380 }
5381
5382 static void
5383 handle_vs_input_decl(struct nir_to_llvm_context *ctx,
5384 struct nir_variable *variable)
5385 {
5386 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
5387 LLVMValueRef t_offset;
5388 LLVMValueRef t_list;
5389 LLVMValueRef input;
5390 LLVMValueRef buffer_index;
5391 int index = variable->data.location - VERT_ATTRIB_GENERIC0;
5392 int idx = variable->data.location;
5393 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
5394 uint8_t input_usage_mask =
5395 ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
5396 unsigned num_channels = util_last_bit(input_usage_mask);
5397
5398 variable->data.driver_location = idx * 4;
5399
5400 for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
5401 if (ctx->options->key.vs.instance_rate_inputs & (1u << (index + i))) {
5402 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
5403 ctx->abi.start_instance, "");
5404 if (ctx->options->key.vs.as_ls) {
5405 ctx->shader_info->vs.vgpr_comp_cnt =
5406 MAX2(2, ctx->shader_info->vs.vgpr_comp_cnt);
5407 } else {
5408 ctx->shader_info->vs.vgpr_comp_cnt =
5409 MAX2(1, ctx->shader_info->vs.vgpr_comp_cnt);
5410 }
5411 } else
5412 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
5413 ctx->abi.base_vertex, "");
5414 t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
5415
5416 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
5417
5418 input = ac_build_buffer_load_format(&ctx->ac, t_list,
5419 buffer_index,
5420 ctx->ac.i32_0,
5421 num_channels, false, true);
5422
5423 input = ac_build_expand_to_vec4(&ctx->ac, input, num_channels);
5424
5425 for (unsigned chan = 0; chan < 4; chan++) {
5426 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5427 ctx->inputs[radeon_llvm_reg_index_soa(idx, chan)] =
5428 ac_to_integer(&ctx->ac, LLVMBuildExtractElement(ctx->ac.builder,
5429 input, llvm_chan, ""));
5430 }
5431 }
5432 }
5433
5434 static void interp_fs_input(struct nir_to_llvm_context *ctx,
5435 unsigned attr,
5436 LLVMValueRef interp_param,
5437 LLVMValueRef prim_mask,
5438 LLVMValueRef result[4])
5439 {
5440 LLVMValueRef attr_number;
5441 unsigned chan;
5442 LLVMValueRef i, j;
5443 bool interp = interp_param != NULL;
5444
5445 attr_number = LLVMConstInt(ctx->ac.i32, attr, false);
5446
5447 /* fs.constant returns the param from the middle vertex, so it's not
5448 * really useful for flat shading. It's meant to be used for custom
5449 * interpolation (but the intrinsic can't fetch from the other two
5450 * vertices).
5451 *
5452 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
5453 * to do the right thing. The only reason we use fs.constant is that
5454 * fs.interp cannot be used on integers, because they can be equal
5455 * to NaN.
5456 */
5457 if (interp) {
5458 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
5459 ctx->ac.v2f32, "");
5460
5461 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5462 ctx->ac.i32_0, "");
5463 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
5464 ctx->ac.i32_1, "");
5465 }
5466
5467 for (chan = 0; chan < 4; chan++) {
5468 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
5469
5470 if (interp) {
5471 result[chan] = ac_build_fs_interp(&ctx->ac,
5472 llvm_chan,
5473 attr_number,
5474 prim_mask, i, j);
5475 } else {
5476 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
5477 LLVMConstInt(ctx->ac.i32, 2, false),
5478 llvm_chan,
5479 attr_number,
5480 prim_mask);
5481 }
5482 }
5483 }
5484
5485 static void
5486 handle_fs_input_decl(struct nir_to_llvm_context *ctx,
5487 struct nir_variable *variable)
5488 {
5489 int idx = variable->data.location;
5490 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5491 LLVMValueRef interp;
5492
5493 variable->data.driver_location = idx * 4;
5494 ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
5495
5496 if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
5497 unsigned interp_type;
5498 if (variable->data.sample)
5499 interp_type = INTERP_SAMPLE;
5500 else if (variable->data.centroid)
5501 interp_type = INTERP_CENTROID;
5502 else
5503 interp_type = INTERP_CENTER;
5504
5505 interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
5506 } else
5507 interp = NULL;
5508
5509 for (unsigned i = 0; i < attrib_count; ++i)
5510 ctx->inputs[radeon_llvm_reg_index_soa(idx + i, 0)] = interp;
5511
5512 }
5513
5514 static void
5515 handle_vs_inputs(struct nir_to_llvm_context *ctx,
5516 struct nir_shader *nir) {
5517 nir_foreach_variable(variable, &nir->inputs)
5518 handle_vs_input_decl(ctx, variable);
5519 }
5520
5521 static void
5522 prepare_interp_optimize(struct nir_to_llvm_context *ctx,
5523 struct nir_shader *nir)
5524 {
5525 if (!ctx->options->key.fs.multisample)
5526 return;
5527
5528 bool uses_center = false;
5529 bool uses_centroid = false;
5530 nir_foreach_variable(variable, &nir->inputs) {
5531 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
5532 variable->data.sample)
5533 continue;
5534
5535 if (variable->data.centroid)
5536 uses_centroid = true;
5537 else
5538 uses_center = true;
5539 }
5540
5541 if (uses_center && uses_centroid) {
5542 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
5543 ctx->persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->persp_center, ctx->persp_centroid, "");
5544 ctx->linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->linear_center, ctx->linear_centroid, "");
5545 }
5546 }
5547
5548 static void
5549 handle_fs_inputs(struct nir_to_llvm_context *ctx,
5550 struct nir_shader *nir)
5551 {
5552 prepare_interp_optimize(ctx, nir);
5553
5554 nir_foreach_variable(variable, &nir->inputs)
5555 handle_fs_input_decl(ctx, variable);
5556
5557 unsigned index = 0;
5558
5559 if (ctx->shader_info->info.ps.uses_input_attachments ||
5560 ctx->shader_info->info.needs_multiview_view_index)
5561 ctx->input_mask |= 1ull << VARYING_SLOT_LAYER;
5562
5563 for (unsigned i = 0; i < RADEON_LLVM_MAX_INPUTS; ++i) {
5564 LLVMValueRef interp_param;
5565 LLVMValueRef *inputs = ctx->inputs +radeon_llvm_reg_index_soa(i, 0);
5566
5567 if (!(ctx->input_mask & (1ull << i)))
5568 continue;
5569
5570 if (i >= VARYING_SLOT_VAR0 || i == VARYING_SLOT_PNTC ||
5571 i == VARYING_SLOT_PRIMITIVE_ID || i == VARYING_SLOT_LAYER) {
5572 interp_param = *inputs;
5573 interp_fs_input(ctx, index, interp_param, ctx->abi.prim_mask,
5574 inputs);
5575
5576 if (!interp_param)
5577 ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
5578 ++index;
5579 } else if (i == VARYING_SLOT_POS) {
5580 for(int i = 0; i < 3; ++i)
5581 inputs[i] = ctx->abi.frag_pos[i];
5582
5583 inputs[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
5584 ctx->abi.frag_pos[3]);
5585 }
5586 }
5587 ctx->shader_info->fs.num_interp = index;
5588 if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
5589 ctx->shader_info->fs.has_pcoord = true;
5590 if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
5591 ctx->shader_info->fs.prim_id_input = true;
5592 if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
5593 ctx->shader_info->fs.layer_input = true;
5594 ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
5595
5596 if (ctx->shader_info->info.needs_multiview_view_index)
5597 ctx->abi.view_index = ctx->inputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5598 }
5599
5600 static LLVMValueRef
5601 ac_build_alloca(struct ac_llvm_context *ac,
5602 LLVMTypeRef type,
5603 const char *name)
5604 {
5605 LLVMBuilderRef builder = ac->builder;
5606 LLVMBasicBlockRef current_block = LLVMGetInsertBlock(builder);
5607 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
5608 LLVMBasicBlockRef first_block = LLVMGetEntryBasicBlock(function);
5609 LLVMValueRef first_instr = LLVMGetFirstInstruction(first_block);
5610 LLVMBuilderRef first_builder = LLVMCreateBuilderInContext(ac->context);
5611 LLVMValueRef res;
5612
5613 if (first_instr) {
5614 LLVMPositionBuilderBefore(first_builder, first_instr);
5615 } else {
5616 LLVMPositionBuilderAtEnd(first_builder, first_block);
5617 }
5618
5619 res = LLVMBuildAlloca(first_builder, type, name);
5620 LLVMBuildStore(builder, LLVMConstNull(type), res);
5621
5622 LLVMDisposeBuilder(first_builder);
5623
5624 return res;
5625 }
5626
5627 static LLVMValueRef si_build_alloca_undef(struct ac_llvm_context *ac,
5628 LLVMTypeRef type,
5629 const char *name)
5630 {
5631 LLVMValueRef ptr = ac_build_alloca(ac, type, name);
5632 LLVMBuildStore(ac->builder, LLVMGetUndef(type), ptr);
5633 return ptr;
5634 }
5635
5636 static void
5637 scan_shader_output_decl(struct nir_to_llvm_context *ctx,
5638 struct nir_variable *variable,
5639 struct nir_shader *shader,
5640 gl_shader_stage stage)
5641 {
5642 int idx = variable->data.location + variable->data.index;
5643 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5644 uint64_t mask_attribs;
5645
5646 variable->data.driver_location = idx * 4;
5647
5648 /* tess ctrl has it's own load/store paths for outputs */
5649 if (stage == MESA_SHADER_TESS_CTRL)
5650 return;
5651
5652 mask_attribs = ((1ull << attrib_count) - 1) << idx;
5653 if (stage == MESA_SHADER_VERTEX ||
5654 stage == MESA_SHADER_TESS_EVAL ||
5655 stage == MESA_SHADER_GEOMETRY) {
5656 if (idx == VARYING_SLOT_CLIP_DIST0) {
5657 int length = shader->info.clip_distance_array_size +
5658 shader->info.cull_distance_array_size;
5659 if (stage == MESA_SHADER_VERTEX) {
5660 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5661 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5662 }
5663 if (stage == MESA_SHADER_TESS_EVAL) {
5664 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
5665 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
5666 }
5667
5668 if (length > 4)
5669 attrib_count = 2;
5670 else
5671 attrib_count = 1;
5672 mask_attribs = 1ull << idx;
5673 }
5674 }
5675
5676 ctx->output_mask |= mask_attribs;
5677 }
5678
5679 static void
5680 handle_shader_output_decl(struct ac_nir_context *ctx,
5681 struct nir_shader *nir,
5682 struct nir_variable *variable)
5683 {
5684 unsigned output_loc = variable->data.driver_location / 4;
5685 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5686
5687 /* tess ctrl has it's own load/store paths for outputs */
5688 if (ctx->stage == MESA_SHADER_TESS_CTRL)
5689 return;
5690
5691 if (ctx->stage == MESA_SHADER_VERTEX ||
5692 ctx->stage == MESA_SHADER_TESS_EVAL ||
5693 ctx->stage == MESA_SHADER_GEOMETRY) {
5694 int idx = variable->data.location + variable->data.index;
5695 if (idx == VARYING_SLOT_CLIP_DIST0) {
5696 int length = nir->info.clip_distance_array_size +
5697 nir->info.cull_distance_array_size;
5698
5699 if (length > 4)
5700 attrib_count = 2;
5701 else
5702 attrib_count = 1;
5703 }
5704 }
5705
5706 for (unsigned i = 0; i < attrib_count; ++i) {
5707 for (unsigned chan = 0; chan < 4; chan++) {
5708 ctx->abi->outputs[radeon_llvm_reg_index_soa(output_loc + i, chan)] =
5709 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5710 }
5711 }
5712 }
5713
5714 static LLVMTypeRef
5715 glsl_base_to_llvm_type(struct ac_llvm_context *ac,
5716 enum glsl_base_type type)
5717 {
5718 switch (type) {
5719 case GLSL_TYPE_INT:
5720 case GLSL_TYPE_UINT:
5721 case GLSL_TYPE_BOOL:
5722 case GLSL_TYPE_SUBROUTINE:
5723 return ac->i32;
5724 case GLSL_TYPE_FLOAT: /* TODO handle mediump */
5725 return ac->f32;
5726 case GLSL_TYPE_INT64:
5727 case GLSL_TYPE_UINT64:
5728 return ac->i64;
5729 case GLSL_TYPE_DOUBLE:
5730 return ac->f64;
5731 default:
5732 unreachable("unknown GLSL type");
5733 }
5734 }
5735
5736 static LLVMTypeRef
5737 glsl_to_llvm_type(struct ac_llvm_context *ac,
5738 const struct glsl_type *type)
5739 {
5740 if (glsl_type_is_scalar(type)) {
5741 return glsl_base_to_llvm_type(ac, glsl_get_base_type(type));
5742 }
5743
5744 if (glsl_type_is_vector(type)) {
5745 return LLVMVectorType(
5746 glsl_base_to_llvm_type(ac, glsl_get_base_type(type)),
5747 glsl_get_vector_elements(type));
5748 }
5749
5750 if (glsl_type_is_matrix(type)) {
5751 return LLVMArrayType(
5752 glsl_to_llvm_type(ac, glsl_get_column_type(type)),
5753 glsl_get_matrix_columns(type));
5754 }
5755
5756 if (glsl_type_is_array(type)) {
5757 return LLVMArrayType(
5758 glsl_to_llvm_type(ac, glsl_get_array_element(type)),
5759 glsl_get_length(type));
5760 }
5761
5762 assert(glsl_type_is_struct(type));
5763
5764 LLVMTypeRef member_types[glsl_get_length(type)];
5765
5766 for (unsigned i = 0; i < glsl_get_length(type); i++) {
5767 member_types[i] =
5768 glsl_to_llvm_type(ac,
5769 glsl_get_struct_field(type, i));
5770 }
5771
5772 return LLVMStructTypeInContext(ac->context, member_types,
5773 glsl_get_length(type), false);
5774 }
5775
5776 static void
5777 setup_locals(struct ac_nir_context *ctx,
5778 struct nir_function *func)
5779 {
5780 int i, j;
5781 ctx->num_locals = 0;
5782 nir_foreach_variable(variable, &func->impl->locals) {
5783 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
5784 variable->data.driver_location = ctx->num_locals * 4;
5785 variable->data.location_frac = 0;
5786 ctx->num_locals += attrib_count;
5787 }
5788 ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
5789 if (!ctx->locals)
5790 return;
5791
5792 for (i = 0; i < ctx->num_locals; i++) {
5793 for (j = 0; j < 4; j++) {
5794 ctx->locals[i * 4 + j] =
5795 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "temp");
5796 }
5797 }
5798 }
5799
5800 static void
5801 setup_shared(struct ac_nir_context *ctx,
5802 struct nir_shader *nir)
5803 {
5804 nir_foreach_variable(variable, &nir->shared) {
5805 LLVMValueRef shared =
5806 LLVMAddGlobalInAddressSpace(
5807 ctx->ac.module, glsl_to_llvm_type(&ctx->ac, variable->type),
5808 variable->name ? variable->name : "",
5809 AC_LOCAL_ADDR_SPACE);
5810 _mesa_hash_table_insert(ctx->vars, variable, shared);
5811 }
5812 }
5813
5814 /* Initialize arguments for the shader export intrinsic */
5815 static void
5816 si_llvm_init_export_args(struct nir_to_llvm_context *ctx,
5817 LLVMValueRef *values,
5818 unsigned target,
5819 struct ac_export_args *args)
5820 {
5821 /* Default is 0xf. Adjusted below depending on the format. */
5822 args->enabled_channels = 0xf;
5823
5824 /* Specify whether the EXEC mask represents the valid mask */
5825 args->valid_mask = 0;
5826
5827 /* Specify whether this is the last export */
5828 args->done = 0;
5829
5830 /* Specify the target we are exporting */
5831 args->target = target;
5832
5833 args->compr = false;
5834 args->out[0] = LLVMGetUndef(ctx->ac.f32);
5835 args->out[1] = LLVMGetUndef(ctx->ac.f32);
5836 args->out[2] = LLVMGetUndef(ctx->ac.f32);
5837 args->out[3] = LLVMGetUndef(ctx->ac.f32);
5838
5839 if (ctx->stage == MESA_SHADER_FRAGMENT && target >= V_008DFC_SQ_EXP_MRT) {
5840 unsigned index = target - V_008DFC_SQ_EXP_MRT;
5841 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
5842 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
5843 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
5844 unsigned chan;
5845
5846 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
5847 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
5848 unsigned bits, bool hi) = NULL;
5849
5850 switch(col_format) {
5851 case V_028714_SPI_SHADER_ZERO:
5852 args->enabled_channels = 0; /* writemask */
5853 args->target = V_008DFC_SQ_EXP_NULL;
5854 break;
5855
5856 case V_028714_SPI_SHADER_32_R:
5857 args->enabled_channels = 1;
5858 args->out[0] = values[0];
5859 break;
5860
5861 case V_028714_SPI_SHADER_32_GR:
5862 args->enabled_channels = 0x3;
5863 args->out[0] = values[0];
5864 args->out[1] = values[1];
5865 break;
5866
5867 case V_028714_SPI_SHADER_32_AR:
5868 args->enabled_channels = 0x9;
5869 args->out[0] = values[0];
5870 args->out[3] = values[3];
5871 break;
5872
5873 case V_028714_SPI_SHADER_FP16_ABGR:
5874 packf = ac_build_cvt_pkrtz_f16;
5875 break;
5876
5877 case V_028714_SPI_SHADER_UNORM16_ABGR:
5878 packf = ac_build_cvt_pknorm_u16;
5879 break;
5880
5881 case V_028714_SPI_SHADER_SNORM16_ABGR:
5882 packf = ac_build_cvt_pknorm_i16;
5883 break;
5884
5885 case V_028714_SPI_SHADER_UINT16_ABGR:
5886 packi = ac_build_cvt_pk_u16;
5887 break;
5888
5889 case V_028714_SPI_SHADER_SINT16_ABGR:
5890 packi = ac_build_cvt_pk_i16;
5891 break;
5892
5893 default:
5894 case V_028714_SPI_SHADER_32_ABGR:
5895 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5896 break;
5897 }
5898
5899 /* Pack f16 or norm_i16/u16. */
5900 if (packf) {
5901 for (chan = 0; chan < 2; chan++) {
5902 LLVMValueRef pack_args[2] = {
5903 values[2 * chan],
5904 values[2 * chan + 1]
5905 };
5906 LLVMValueRef packed;
5907
5908 packed = packf(&ctx->ac, pack_args);
5909 args->out[chan] = ac_to_float(&ctx->ac, packed);
5910 }
5911 args->compr = 1; /* COMPR flag */
5912 }
5913
5914 /* Pack i16/u16. */
5915 if (packi) {
5916 for (chan = 0; chan < 2; chan++) {
5917 LLVMValueRef pack_args[2] = {
5918 ac_to_integer(&ctx->ac, values[2 * chan]),
5919 ac_to_integer(&ctx->ac, values[2 * chan + 1])
5920 };
5921 LLVMValueRef packed;
5922
5923 packed = packi(&ctx->ac, pack_args,
5924 is_int8 ? 8 : is_int10 ? 10 : 16,
5925 chan == 1);
5926 args->out[chan] = ac_to_float(&ctx->ac, packed);
5927 }
5928 args->compr = 1; /* COMPR flag */
5929 }
5930 return;
5931 }
5932
5933 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
5934
5935 for (unsigned i = 0; i < 4; ++i)
5936 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
5937 }
5938
5939 static void
5940 radv_export_param(struct nir_to_llvm_context *ctx, unsigned index,
5941 LLVMValueRef *values)
5942 {
5943 struct ac_export_args args;
5944
5945 si_llvm_init_export_args(ctx, values,
5946 V_008DFC_SQ_EXP_PARAM + index, &args);
5947 ac_build_export(&ctx->ac, &args);
5948 }
5949
5950 static LLVMValueRef
5951 radv_load_output(struct nir_to_llvm_context *ctx, unsigned index, unsigned chan)
5952 {
5953 LLVMValueRef output =
5954 ctx->abi.outputs[radeon_llvm_reg_index_soa(index, chan)];
5955
5956 return LLVMBuildLoad(ctx->ac.builder, output, "");
5957 }
5958
5959 static void
5960 handle_vs_outputs_post(struct nir_to_llvm_context *ctx,
5961 bool export_prim_id,
5962 struct ac_vs_output_info *outinfo)
5963 {
5964 uint32_t param_count = 0;
5965 unsigned target;
5966 unsigned pos_idx, num_pos_exports = 0;
5967 struct ac_export_args args, pos_args[4] = {};
5968 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_index_value = NULL;
5969 int i;
5970
5971 if (ctx->options->key.has_multiview_view_index) {
5972 LLVMValueRef* tmp_out = &ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
5973 if(!*tmp_out) {
5974 for(unsigned i = 0; i < 4; ++i)
5975 ctx->abi.outputs[radeon_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
5976 si_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
5977 }
5978
5979 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
5980 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
5981 }
5982
5983 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
5984 sizeof(outinfo->vs_output_param_offset));
5985
5986 if (ctx->output_mask & (1ull << VARYING_SLOT_CLIP_DIST0)) {
5987 LLVMValueRef slots[8];
5988 unsigned j;
5989
5990 if (outinfo->cull_dist_mask)
5991 outinfo->cull_dist_mask <<= ctx->num_output_clips;
5992
5993 i = VARYING_SLOT_CLIP_DIST0;
5994 for (j = 0; j < ctx->num_output_clips + ctx->num_output_culls; j++)
5995 slots[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
5996
5997 for (i = ctx->num_output_clips + ctx->num_output_culls; i < 8; i++)
5998 slots[i] = LLVMGetUndef(ctx->ac.f32);
5999
6000 if (ctx->num_output_clips + ctx->num_output_culls > 4) {
6001 target = V_008DFC_SQ_EXP_POS + 3;
6002 si_llvm_init_export_args(ctx, &slots[4], target, &args);
6003 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6004 &args, sizeof(args));
6005 }
6006
6007 target = V_008DFC_SQ_EXP_POS + 2;
6008 si_llvm_init_export_args(ctx, &slots[0], target, &args);
6009 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
6010 &args, sizeof(args));
6011
6012 }
6013
6014 LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
6015 if (ctx->output_mask & (1ull << VARYING_SLOT_POS)) {
6016 for (unsigned j = 0; j < 4; j++)
6017 pos_values[j] = radv_load_output(ctx, VARYING_SLOT_POS, j);
6018 }
6019 si_llvm_init_export_args(ctx, pos_values, V_008DFC_SQ_EXP_POS, &pos_args[0]);
6020
6021 if (ctx->output_mask & (1ull << VARYING_SLOT_PSIZ)) {
6022 outinfo->writes_pointsize = true;
6023 psize_value = radv_load_output(ctx, VARYING_SLOT_PSIZ, 0);
6024 }
6025
6026 if (ctx->output_mask & (1ull << VARYING_SLOT_LAYER)) {
6027 outinfo->writes_layer = true;
6028 layer_value = radv_load_output(ctx, VARYING_SLOT_LAYER, 0);
6029 }
6030
6031 if (ctx->output_mask & (1ull << VARYING_SLOT_VIEWPORT)) {
6032 outinfo->writes_viewport_index = true;
6033 viewport_index_value = radv_load_output(ctx, VARYING_SLOT_VIEWPORT, 0);
6034 }
6035
6036 if (outinfo->writes_pointsize ||
6037 outinfo->writes_layer ||
6038 outinfo->writes_viewport_index) {
6039 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
6040 (outinfo->writes_layer == true ? 4 : 0));
6041 pos_args[1].valid_mask = 0;
6042 pos_args[1].done = 0;
6043 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
6044 pos_args[1].compr = 0;
6045 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
6046 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
6047 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
6048 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
6049
6050 if (outinfo->writes_pointsize == true)
6051 pos_args[1].out[0] = psize_value;
6052 if (outinfo->writes_layer == true)
6053 pos_args[1].out[2] = layer_value;
6054 if (outinfo->writes_viewport_index == true) {
6055 if (ctx->options->chip_class >= GFX9) {
6056 /* GFX9 has the layer in out.z[10:0] and the viewport
6057 * index in out.z[19:16].
6058 */
6059 LLVMValueRef v = viewport_index_value;
6060 v = ac_to_integer(&ctx->ac, v);
6061 v = LLVMBuildShl(ctx->ac.builder, v,
6062 LLVMConstInt(ctx->ac.i32, 16, false),
6063 "");
6064 v = LLVMBuildOr(ctx->ac.builder, v,
6065 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
6066
6067 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
6068 pos_args[1].enabled_channels |= 1 << 2;
6069 } else {
6070 pos_args[1].out[3] = viewport_index_value;
6071 pos_args[1].enabled_channels |= 1 << 3;
6072 }
6073 }
6074 }
6075 for (i = 0; i < 4; i++) {
6076 if (pos_args[i].out[0])
6077 num_pos_exports++;
6078 }
6079
6080 pos_idx = 0;
6081 for (i = 0; i < 4; i++) {
6082 if (!pos_args[i].out[0])
6083 continue;
6084
6085 /* Specify the target we are exporting */
6086 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
6087 if (pos_idx == num_pos_exports)
6088 pos_args[i].done = 1;
6089 ac_build_export(&ctx->ac, &pos_args[i]);
6090 }
6091
6092 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6093 LLVMValueRef values[4];
6094 if (!(ctx->output_mask & (1ull << i)))
6095 continue;
6096
6097 if (i != VARYING_SLOT_LAYER &&
6098 i != VARYING_SLOT_PRIMITIVE_ID &&
6099 i < VARYING_SLOT_VAR0)
6100 continue;
6101
6102 for (unsigned j = 0; j < 4; j++)
6103 values[j] = ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
6104
6105 radv_export_param(ctx, param_count, values);
6106
6107 outinfo->vs_output_param_offset[i] = param_count++;
6108 }
6109
6110 if (export_prim_id) {
6111 LLVMValueRef values[4];
6112
6113 values[0] = ctx->vs_prim_id;
6114 ctx->shader_info->vs.vgpr_comp_cnt = MAX2(2,
6115 ctx->shader_info->vs.vgpr_comp_cnt);
6116 for (unsigned j = 1; j < 4; j++)
6117 values[j] = ctx->ac.f32_0;
6118
6119 radv_export_param(ctx, param_count, values);
6120
6121 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
6122 outinfo->export_prim_id = true;
6123 }
6124
6125 outinfo->pos_exports = num_pos_exports;
6126 outinfo->param_exports = param_count;
6127 }
6128
6129 static void
6130 handle_es_outputs_post(struct nir_to_llvm_context *ctx,
6131 struct ac_es_output_info *outinfo)
6132 {
6133 int j;
6134 uint64_t max_output_written = 0;
6135 LLVMValueRef lds_base = NULL;
6136
6137 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6138 int param_index;
6139 int length = 4;
6140
6141 if (!(ctx->output_mask & (1ull << i)))
6142 continue;
6143
6144 if (i == VARYING_SLOT_CLIP_DIST0)
6145 length = ctx->num_output_clips + ctx->num_output_culls;
6146
6147 param_index = shader_io_get_unique_index(i);
6148
6149 max_output_written = MAX2(param_index + (length > 4), max_output_written);
6150 }
6151
6152 outinfo->esgs_itemsize = (max_output_written + 1) * 16;
6153
6154 if (ctx->ac.chip_class >= GFX9) {
6155 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
6156 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
6157 LLVMValueRef wave_idx = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6158 LLVMConstInt(ctx->ac.i32, 24, false),
6159 LLVMConstInt(ctx->ac.i32, 4, false), false);
6160 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
6161 LLVMBuildMul(ctx->ac.builder, wave_idx,
6162 LLVMConstInt(ctx->ac.i32, 64, false), ""), "");
6163 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
6164 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
6165 }
6166
6167 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6168 LLVMValueRef dw_addr = NULL;
6169 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6170 int param_index;
6171 int length = 4;
6172
6173 if (!(ctx->output_mask & (1ull << i)))
6174 continue;
6175
6176 if (i == VARYING_SLOT_CLIP_DIST0)
6177 length = ctx->num_output_clips + ctx->num_output_culls;
6178
6179 param_index = shader_io_get_unique_index(i);
6180
6181 if (lds_base) {
6182 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
6183 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
6184 "");
6185 }
6186 for (j = 0; j < length; j++) {
6187 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
6188 out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
6189
6190 if (ctx->ac.chip_class >= GFX9) {
6191 ac_lds_store(&ctx->ac, dw_addr,
6192 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6193 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6194 } else {
6195 ac_build_buffer_store_dword(&ctx->ac,
6196 ctx->esgs_ring,
6197 out_val, 1,
6198 NULL, ctx->es2gs_offset,
6199 (4 * param_index + j) * 4,
6200 1, 1, true, true);
6201 }
6202 }
6203 }
6204 }
6205
6206 static void
6207 handle_ls_outputs_post(struct nir_to_llvm_context *ctx)
6208 {
6209 LLVMValueRef vertex_id = ctx->rel_auto_id;
6210 LLVMValueRef vertex_dw_stride = unpack_param(&ctx->ac, ctx->ls_out_layout, 13, 8);
6211 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
6212 vertex_dw_stride, "");
6213
6214 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6215 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
6216 int length = 4;
6217
6218 if (!(ctx->output_mask & (1ull << i)))
6219 continue;
6220
6221 if (i == VARYING_SLOT_CLIP_DIST0)
6222 length = ctx->num_output_clips + ctx->num_output_culls;
6223 int param = shader_io_get_unique_index(i);
6224 mark_tess_output(ctx, false, param);
6225 if (length > 4)
6226 mark_tess_output(ctx, false, param + 1);
6227 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
6228 LLVMConstInt(ctx->ac.i32, param * 4, false),
6229 "");
6230 for (unsigned j = 0; j < length; j++) {
6231 ac_lds_store(&ctx->ac, dw_addr,
6232 LLVMBuildLoad(ctx->ac.builder, out_ptr[j], ""));
6233 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
6234 }
6235 }
6236 }
6237
6238 struct ac_build_if_state
6239 {
6240 struct nir_to_llvm_context *ctx;
6241 LLVMValueRef condition;
6242 LLVMBasicBlockRef entry_block;
6243 LLVMBasicBlockRef true_block;
6244 LLVMBasicBlockRef false_block;
6245 LLVMBasicBlockRef merge_block;
6246 };
6247
6248 static LLVMBasicBlockRef
6249 ac_build_insert_new_block(struct nir_to_llvm_context *ctx, const char *name)
6250 {
6251 LLVMBasicBlockRef current_block;
6252 LLVMBasicBlockRef next_block;
6253 LLVMBasicBlockRef new_block;
6254
6255 /* get current basic block */
6256 current_block = LLVMGetInsertBlock(ctx->ac.builder);
6257
6258 /* chqeck if there's another block after this one */
6259 next_block = LLVMGetNextBasicBlock(current_block);
6260 if (next_block) {
6261 /* insert the new block before the next block */
6262 new_block = LLVMInsertBasicBlockInContext(ctx->context, next_block, name);
6263 }
6264 else {
6265 /* append new block after current block */
6266 LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
6267 new_block = LLVMAppendBasicBlockInContext(ctx->context, function, name);
6268 }
6269 return new_block;
6270 }
6271
6272 static void
6273 ac_nir_build_if(struct ac_build_if_state *ifthen,
6274 struct nir_to_llvm_context *ctx,
6275 LLVMValueRef condition)
6276 {
6277 LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
6278
6279 memset(ifthen, 0, sizeof *ifthen);
6280 ifthen->ctx = ctx;
6281 ifthen->condition = condition;
6282 ifthen->entry_block = block;
6283
6284 /* create endif/merge basic block for the phi functions */
6285 ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
6286
6287 /* create/insert true_block before merge_block */
6288 ifthen->true_block =
6289 LLVMInsertBasicBlockInContext(ctx->context,
6290 ifthen->merge_block,
6291 "if-true-block");
6292
6293 /* successive code goes into the true block */
6294 LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
6295 }
6296
6297 /**
6298 * End a conditional.
6299 */
6300 static void
6301 ac_nir_build_endif(struct ac_build_if_state *ifthen)
6302 {
6303 LLVMBuilderRef builder = ifthen->ctx->ac.builder;
6304
6305 /* Insert branch to the merge block from current block */
6306 LLVMBuildBr(builder, ifthen->merge_block);
6307
6308 /*
6309 * Now patch in the various branch instructions.
6310 */
6311
6312 /* Insert the conditional branch instruction at the end of entry_block */
6313 LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
6314 if (ifthen->false_block) {
6315 /* we have an else clause */
6316 LLVMBuildCondBr(builder, ifthen->condition,
6317 ifthen->true_block, ifthen->false_block);
6318 }
6319 else {
6320 /* no else clause */
6321 LLVMBuildCondBr(builder, ifthen->condition,
6322 ifthen->true_block, ifthen->merge_block);
6323 }
6324
6325 /* Resume building code at end of the ifthen->merge_block */
6326 LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
6327 }
6328
6329 static void
6330 write_tess_factors(struct nir_to_llvm_context *ctx)
6331 {
6332 unsigned stride, outer_comps, inner_comps;
6333 struct ac_build_if_state if_ctx, inner_if_ctx;
6334 LLVMValueRef invocation_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
6335 LLVMValueRef rel_patch_id = unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
6336 unsigned tess_inner_index, tess_outer_index;
6337 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
6338 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
6339 int i;
6340 emit_barrier(&ctx->ac, ctx->stage);
6341
6342 switch (ctx->options->key.tcs.primitive_mode) {
6343 case GL_ISOLINES:
6344 stride = 2;
6345 outer_comps = 2;
6346 inner_comps = 0;
6347 break;
6348 case GL_TRIANGLES:
6349 stride = 4;
6350 outer_comps = 3;
6351 inner_comps = 1;
6352 break;
6353 case GL_QUADS:
6354 stride = 6;
6355 outer_comps = 4;
6356 inner_comps = 2;
6357 break;
6358 default:
6359 return;
6360 }
6361
6362 ac_nir_build_if(&if_ctx, ctx,
6363 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6364 invocation_id, ctx->ac.i32_0, ""));
6365
6366 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6367 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6368
6369 mark_tess_output(ctx, true, tess_inner_index);
6370 mark_tess_output(ctx, true, tess_outer_index);
6371 lds_base = get_tcs_out_current_patch_data_offset(ctx);
6372 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
6373 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
6374 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
6375 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
6376
6377 for (i = 0; i < 4; i++) {
6378 inner[i] = LLVMGetUndef(ctx->ac.i32);
6379 outer[i] = LLVMGetUndef(ctx->ac.i32);
6380 }
6381
6382 // LINES reverseal
6383 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
6384 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
6385 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6386 ctx->ac.i32_1, "");
6387 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
6388 } else {
6389 for (i = 0; i < outer_comps; i++) {
6390 outer[i] = out[i] =
6391 ac_lds_load(&ctx->ac, lds_outer);
6392 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
6393 ctx->ac.i32_1, "");
6394 }
6395 for (i = 0; i < inner_comps; i++) {
6396 inner[i] = out[outer_comps+i] =
6397 ac_lds_load(&ctx->ac, lds_inner);
6398 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
6399 ctx->ac.i32_1, "");
6400 }
6401 }
6402
6403 /* Convert the outputs to vectors for stores. */
6404 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
6405 vec1 = NULL;
6406
6407 if (stride > 4)
6408 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
6409
6410
6411 buffer = ctx->hs_ring_tess_factor;
6412 tf_base = ctx->tess_factor_offset;
6413 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
6414 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
6415 unsigned tf_offset = 0;
6416
6417 if (ctx->options->chip_class <= VI) {
6418 ac_nir_build_if(&inner_if_ctx, ctx,
6419 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
6420 rel_patch_id, ctx->ac.i32_0, ""));
6421
6422 /* Store the dynamic HS control word. */
6423 ac_build_buffer_store_dword(&ctx->ac, buffer,
6424 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
6425 1, ctx->ac.i32_0, tf_base,
6426 0, 1, 0, true, false);
6427 tf_offset += 4;
6428
6429 ac_nir_build_endif(&inner_if_ctx);
6430 }
6431
6432 /* Store the tessellation factors. */
6433 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
6434 MIN2(stride, 4), byteoffset, tf_base,
6435 tf_offset, 1, 0, true, false);
6436 if (vec1)
6437 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
6438 stride - 4, byteoffset, tf_base,
6439 16 + tf_offset, 1, 0, true, false);
6440
6441 //store to offchip for TES to read - only if TES reads them
6442 if (ctx->options->key.tcs.tes_reads_tess_factors) {
6443 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
6444 LLVMValueRef tf_inner_offset;
6445 unsigned param_outer, param_inner;
6446
6447 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
6448 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
6449 LLVMConstInt(ctx->ac.i32, param_outer, 0));
6450
6451 outer_vec = ac_build_gather_values(&ctx->ac, outer,
6452 util_next_power_of_two(outer_comps));
6453
6454 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
6455 outer_comps, tf_outer_offset,
6456 ctx->oc_lds, 0, 1, 0, true, false);
6457 if (inner_comps) {
6458 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
6459 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
6460 LLVMConstInt(ctx->ac.i32, param_inner, 0));
6461
6462 inner_vec = inner_comps == 1 ? inner[0] :
6463 ac_build_gather_values(&ctx->ac, inner, inner_comps);
6464 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
6465 inner_comps, tf_inner_offset,
6466 ctx->oc_lds, 0, 1, 0, true, false);
6467 }
6468 }
6469 ac_nir_build_endif(&if_ctx);
6470 }
6471
6472 static void
6473 handle_tcs_outputs_post(struct nir_to_llvm_context *ctx)
6474 {
6475 write_tess_factors(ctx);
6476 }
6477
6478 static bool
6479 si_export_mrt_color(struct nir_to_llvm_context *ctx,
6480 LLVMValueRef *color, unsigned index, bool is_last,
6481 struct ac_export_args *args)
6482 {
6483 /* Export */
6484 si_llvm_init_export_args(ctx, color,
6485 V_008DFC_SQ_EXP_MRT + index, args);
6486
6487 if (is_last) {
6488 args->valid_mask = 1; /* whether the EXEC mask is valid */
6489 args->done = 1; /* DONE bit */
6490 } else if (!args->enabled_channels)
6491 return false; /* unnecessary NULL export */
6492
6493 return true;
6494 }
6495
6496 static void
6497 radv_export_mrt_z(struct nir_to_llvm_context *ctx,
6498 LLVMValueRef depth, LLVMValueRef stencil,
6499 LLVMValueRef samplemask)
6500 {
6501 struct ac_export_args args;
6502
6503 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
6504
6505 ac_build_export(&ctx->ac, &args);
6506 }
6507
6508 static void
6509 handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
6510 {
6511 unsigned index = 0;
6512 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
6513 struct ac_export_args color_args[8];
6514
6515 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
6516 LLVMValueRef values[4];
6517 bool last = false;
6518
6519 if (!(ctx->output_mask & (1ull << i)))
6520 continue;
6521
6522 if (i < FRAG_RESULT_DATA0)
6523 continue;
6524
6525 for (unsigned j = 0; j < 4; j++)
6526 values[j] = ac_to_float(&ctx->ac,
6527 radv_load_output(ctx, i, j));
6528
6529 if (!ctx->shader_info->info.ps.writes_z &&
6530 !ctx->shader_info->info.ps.writes_stencil &&
6531 !ctx->shader_info->info.ps.writes_sample_mask)
6532 last = ctx->output_mask <= ((1ull << (i + 1)) - 1);
6533
6534 bool ret = si_export_mrt_color(ctx, values,
6535 i - FRAG_RESULT_DATA0,
6536 last, &color_args[index]);
6537 if (ret)
6538 index++;
6539 }
6540
6541 /* Process depth, stencil, samplemask. */
6542 if (ctx->shader_info->info.ps.writes_z) {
6543 depth = ac_to_float(&ctx->ac,
6544 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
6545 }
6546 if (ctx->shader_info->info.ps.writes_stencil) {
6547 stencil = ac_to_float(&ctx->ac,
6548 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
6549 }
6550 if (ctx->shader_info->info.ps.writes_sample_mask) {
6551 samplemask = ac_to_float(&ctx->ac,
6552 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
6553 }
6554
6555 /* Export PS outputs. */
6556 for (unsigned i = 0; i < index; i++)
6557 ac_build_export(&ctx->ac, &color_args[i]);
6558
6559 if (depth || stencil || samplemask)
6560 radv_export_mrt_z(ctx, depth, stencil, samplemask);
6561 else if (!index)
6562 ac_build_export_null(&ctx->ac);
6563 }
6564
6565 static void
6566 emit_gs_epilogue(struct nir_to_llvm_context *ctx)
6567 {
6568 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
6569 }
6570
6571 static void
6572 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
6573 LLVMValueRef *addrs)
6574 {
6575 struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
6576
6577 switch (ctx->stage) {
6578 case MESA_SHADER_VERTEX:
6579 if (ctx->options->key.vs.as_ls)
6580 handle_ls_outputs_post(ctx);
6581 else if (ctx->options->key.vs.as_es)
6582 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
6583 else
6584 handle_vs_outputs_post(ctx, ctx->options->key.vs.export_prim_id,
6585 &ctx->shader_info->vs.outinfo);
6586 break;
6587 case MESA_SHADER_FRAGMENT:
6588 handle_fs_outputs_post(ctx);
6589 break;
6590 case MESA_SHADER_GEOMETRY:
6591 emit_gs_epilogue(ctx);
6592 break;
6593 case MESA_SHADER_TESS_CTRL:
6594 handle_tcs_outputs_post(ctx);
6595 break;
6596 case MESA_SHADER_TESS_EVAL:
6597 if (ctx->options->key.tes.as_es)
6598 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
6599 else
6600 handle_vs_outputs_post(ctx, ctx->options->key.tes.export_prim_id,
6601 &ctx->shader_info->tes.outinfo);
6602 break;
6603 default:
6604 break;
6605 }
6606 }
6607
6608 static void ac_llvm_finalize_module(struct nir_to_llvm_context * ctx)
6609 {
6610 LLVMPassManagerRef passmgr;
6611 /* Create the pass manager */
6612 passmgr = LLVMCreateFunctionPassManagerForModule(
6613 ctx->ac.module);
6614
6615 /* This pass should eliminate all the load and store instructions */
6616 LLVMAddPromoteMemoryToRegisterPass(passmgr);
6617
6618 /* Add some optimization passes */
6619 LLVMAddScalarReplAggregatesPass(passmgr);
6620 LLVMAddLICMPass(passmgr);
6621 LLVMAddAggressiveDCEPass(passmgr);
6622 LLVMAddCFGSimplificationPass(passmgr);
6623 LLVMAddInstructionCombiningPass(passmgr);
6624
6625 /* Run the pass */
6626 LLVMInitializeFunctionPassManager(passmgr);
6627 LLVMRunFunctionPassManager(passmgr, ctx->main_function);
6628 LLVMFinalizeFunctionPassManager(passmgr);
6629
6630 LLVMDisposeBuilder(ctx->ac.builder);
6631 LLVMDisposePassManager(passmgr);
6632 }
6633
6634 static void
6635 ac_nir_eliminate_const_vs_outputs(struct nir_to_llvm_context *ctx)
6636 {
6637 struct ac_vs_output_info *outinfo;
6638
6639 switch (ctx->stage) {
6640 case MESA_SHADER_FRAGMENT:
6641 case MESA_SHADER_COMPUTE:
6642 case MESA_SHADER_TESS_CTRL:
6643 case MESA_SHADER_GEOMETRY:
6644 return;
6645 case MESA_SHADER_VERTEX:
6646 if (ctx->options->key.vs.as_ls ||
6647 ctx->options->key.vs.as_es)
6648 return;
6649 outinfo = &ctx->shader_info->vs.outinfo;
6650 break;
6651 case MESA_SHADER_TESS_EVAL:
6652 if (ctx->options->key.vs.as_es)
6653 return;
6654 outinfo = &ctx->shader_info->tes.outinfo;
6655 break;
6656 default:
6657 unreachable("Unhandled shader type");
6658 }
6659
6660 ac_optimize_vs_outputs(&ctx->ac,
6661 ctx->main_function,
6662 outinfo->vs_output_param_offset,
6663 VARYING_SLOT_MAX,
6664 &outinfo->param_exports);
6665 }
6666
6667 static void
6668 ac_setup_rings(struct nir_to_llvm_context *ctx)
6669 {
6670 if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
6671 (ctx->stage == MESA_SHADER_TESS_EVAL && ctx->options->key.tes.as_es)) {
6672 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
6673 }
6674
6675 if (ctx->is_gs_copy_shader) {
6676 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_VS, false));
6677 }
6678 if (ctx->stage == MESA_SHADER_GEOMETRY) {
6679 LLVMValueRef tmp;
6680 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
6681 ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
6682
6683 ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.v4i32, "");
6684
6685 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
6686 tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, ctx->ac.i32_1, "");
6687 tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, "");
6688 ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
6689 }
6690
6691 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
6692 ctx->stage == MESA_SHADER_TESS_EVAL) {
6693 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
6694 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
6695 }
6696 }
6697
6698 static unsigned
6699 ac_nir_get_max_workgroup_size(enum chip_class chip_class,
6700 const struct nir_shader *nir)
6701 {
6702 switch (nir->info.stage) {
6703 case MESA_SHADER_TESS_CTRL:
6704 return chip_class >= CIK ? 128 : 64;
6705 case MESA_SHADER_GEOMETRY:
6706 return chip_class >= GFX9 ? 128 : 64;
6707 case MESA_SHADER_COMPUTE:
6708 break;
6709 default:
6710 return 0;
6711 }
6712
6713 unsigned max_workgroup_size = nir->info.cs.local_size[0] *
6714 nir->info.cs.local_size[1] *
6715 nir->info.cs.local_size[2];
6716 return max_workgroup_size;
6717 }
6718
6719 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
6720 static void ac_nir_fixup_ls_hs_input_vgprs(struct nir_to_llvm_context *ctx)
6721 {
6722 LLVMValueRef count = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6723 LLVMConstInt(ctx->ac.i32, 8, false),
6724 LLVMConstInt(ctx->ac.i32, 8, false), false);
6725 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
6726 ctx->ac.i32_0, "");
6727 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
6728 ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.vertex_id, ctx->vs_prim_id, "");
6729 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
6730 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
6731 }
6732
6733 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
6734 {
6735 for(int i = 5; i >= 0; --i) {
6736 ctx->gs_vtx_offset[i] = ac_build_bfe(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
6737 LLVMConstInt(ctx->ac.i32, (i & 1) * 16, false),
6738 LLVMConstInt(ctx->ac.i32, 16, false), false);
6739 }
6740
6741 ctx->gs_wave_id = ac_build_bfe(&ctx->ac, ctx->merged_wave_info,
6742 LLVMConstInt(ctx->ac.i32, 16, false),
6743 LLVMConstInt(ctx->ac.i32, 8, false), false);
6744 }
6745
6746 void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
6747 struct nir_shader *nir, struct nir_to_llvm_context *nctx)
6748 {
6749 struct ac_nir_context ctx = {};
6750 struct nir_function *func;
6751
6752 ctx.ac = *ac;
6753 ctx.abi = abi;
6754
6755 ctx.stage = nir->info.stage;
6756
6757 ctx.main_function = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6758
6759 nir_foreach_variable(variable, &nir->outputs)
6760 handle_shader_output_decl(&ctx, nir, variable);
6761
6762 ctx.defs = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6763 _mesa_key_pointer_equal);
6764 ctx.phis = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6765 _mesa_key_pointer_equal);
6766 ctx.vars = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
6767 _mesa_key_pointer_equal);
6768
6769 func = (struct nir_function *)exec_list_get_head(&nir->functions);
6770
6771 setup_locals(&ctx, func);
6772
6773 if (nir->info.stage == MESA_SHADER_COMPUTE)
6774 setup_shared(&ctx, nir);
6775
6776 visit_cf_list(&ctx, &func->impl->body);
6777 phi_post_pass(&ctx);
6778
6779 if (nir->info.stage != MESA_SHADER_COMPUTE)
6780 ctx.abi->emit_outputs(ctx.abi, AC_LLVM_MAX_OUTPUTS,
6781 ctx.abi->outputs);
6782
6783 free(ctx.locals);
6784 ralloc_free(ctx.defs);
6785 ralloc_free(ctx.phis);
6786 ralloc_free(ctx.vars);
6787 }
6788
6789 static
6790 LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
6791 struct nir_shader *const *shaders,
6792 int shader_count,
6793 struct ac_shader_variant_info *shader_info,
6794 const struct ac_nir_compiler_options *options)
6795 {
6796 struct nir_to_llvm_context ctx = {0};
6797 unsigned i;
6798 ctx.options = options;
6799 ctx.shader_info = shader_info;
6800 ctx.context = LLVMContextCreate();
6801
6802 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
6803 options->family);
6804 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
6805 LLVMSetTarget(ctx.ac.module, options->supports_spill ? "amdgcn-mesa-mesa3d" : "amdgcn--");
6806
6807 LLVMTargetDataRef data_layout = LLVMCreateTargetDataLayout(tm);
6808 char *data_layout_str = LLVMCopyStringRepOfTargetData(data_layout);
6809 LLVMSetDataLayout(ctx.ac.module, data_layout_str);
6810 LLVMDisposeTargetData(data_layout);
6811 LLVMDisposeMessage(data_layout_str);
6812
6813 enum ac_float_mode float_mode =
6814 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
6815 AC_FLOAT_MODE_DEFAULT;
6816
6817 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
6818
6819 memset(shader_info, 0, sizeof(*shader_info));
6820
6821 for(int i = 0; i < shader_count; ++i)
6822 ac_nir_shader_info_pass(shaders[i], options, &shader_info->info);
6823
6824 for (i = 0; i < AC_UD_MAX_SETS; i++)
6825 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
6826 for (i = 0; i < AC_UD_MAX_UD; i++)
6827 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
6828
6829 ctx.max_workgroup_size = 0;
6830 for (int i = 0; i < shader_count; ++i) {
6831 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
6832 ac_nir_get_max_workgroup_size(ctx.options->chip_class,
6833 shaders[i]));
6834 }
6835
6836 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
6837 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
6838
6839 ctx.abi.inputs = &ctx.inputs[0];
6840 ctx.abi.emit_outputs = handle_shader_outputs_post;
6841 ctx.abi.emit_vertex = visit_emit_vertex;
6842 ctx.abi.load_ubo = radv_load_ubo;
6843 ctx.abi.load_ssbo = radv_load_ssbo;
6844 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
6845 ctx.abi.load_resource = radv_load_resource;
6846 ctx.abi.clamp_shadow_reference = false;
6847
6848 if (shader_count >= 2)
6849 ac_init_exec_full_mask(&ctx.ac);
6850
6851 if (ctx.ac.chip_class == GFX9 &&
6852 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
6853 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
6854
6855 for(int i = 0; i < shader_count; ++i) {
6856 ctx.stage = shaders[i]->info.stage;
6857 ctx.output_mask = 0;
6858 ctx.tess_outputs_written = 0;
6859 ctx.num_output_clips = shaders[i]->info.clip_distance_array_size;
6860 ctx.num_output_culls = shaders[i]->info.cull_distance_array_size;
6861
6862 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6863 ctx.gs_next_vertex = ac_build_alloca(&ctx.ac, ctx.ac.i32, "gs_next_vertex");
6864 ctx.gs_max_out_vertices = shaders[i]->info.gs.vertices_out;
6865 ctx.abi.load_inputs = load_gs_input;
6866 ctx.abi.emit_primitive = visit_end_primitive;
6867 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6868 ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
6869 ctx.tcs_patch_outputs_read = shaders[i]->info.patch_outputs_read;
6870 ctx.abi.load_tess_varyings = load_tcs_varyings;
6871 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6872 ctx.abi.store_tcs_outputs = store_tcs_output;
6873 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
6874 ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
6875 ctx.abi.load_tess_varyings = load_tes_input;
6876 ctx.abi.load_tess_coord = load_tess_coord;
6877 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
6878 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
6879 if (shader_info->info.vs.needs_instance_id) {
6880 if (ctx.options->key.vs.as_ls) {
6881 ctx.shader_info->vs.vgpr_comp_cnt =
6882 MAX2(2, ctx.shader_info->vs.vgpr_comp_cnt);
6883 } else {
6884 ctx.shader_info->vs.vgpr_comp_cnt =
6885 MAX2(1, ctx.shader_info->vs.vgpr_comp_cnt);
6886 }
6887 }
6888 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
6889 shader_info->fs.can_discard = shaders[i]->info.fs.uses_discard;
6890 ctx.abi.lookup_interp_param = lookup_interp_param;
6891 ctx.abi.load_sample_position = load_sample_position;
6892 ctx.abi.load_sample_mask_in = load_sample_mask_in;
6893 }
6894
6895 if (i)
6896 emit_barrier(&ctx.ac, ctx.stage);
6897
6898 ac_setup_rings(&ctx);
6899
6900 LLVMBasicBlockRef merge_block;
6901 if (shader_count >= 2) {
6902 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
6903 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6904 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
6905
6906 LLVMValueRef count = ac_build_bfe(&ctx.ac, ctx.merged_wave_info,
6907 LLVMConstInt(ctx.ac.i32, 8 * i, false),
6908 LLVMConstInt(ctx.ac.i32, 8, false), false);
6909 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
6910 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
6911 thread_id, count, "");
6912 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
6913
6914 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
6915 }
6916
6917 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
6918 handle_fs_inputs(&ctx, shaders[i]);
6919 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
6920 handle_vs_inputs(&ctx, shaders[i]);
6921 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
6922 prepare_gs_input_vgprs(&ctx);
6923
6924 nir_foreach_variable(variable, &shaders[i]->outputs)
6925 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
6926
6927 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i], &ctx);
6928
6929 if (shader_count >= 2) {
6930 LLVMBuildBr(ctx.ac.builder, merge_block);
6931 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
6932 }
6933
6934 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
6935 unsigned addclip = shaders[i]->info.clip_distance_array_size +
6936 shaders[i]->info.cull_distance_array_size > 4;
6937 shader_info->gs.gsvs_vertex_size = (util_bitcount64(ctx.output_mask) + addclip) * 16;
6938 shader_info->gs.max_gsvs_emit_size = shader_info->gs.gsvs_vertex_size *
6939 shaders[i]->info.gs.vertices_out;
6940 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
6941 shader_info->tcs.outputs_written = ctx.tess_outputs_written;
6942 shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
6943 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
6944 shader_info->vs.outputs_written = ctx.tess_outputs_written;
6945 }
6946 }
6947
6948 LLVMBuildRetVoid(ctx.ac.builder);
6949
6950 if (options->dump_preoptir)
6951 ac_dump_module(ctx.ac.module);
6952
6953 ac_llvm_finalize_module(&ctx);
6954
6955 if (shader_count == 1)
6956 ac_nir_eliminate_const_vs_outputs(&ctx);
6957
6958 return ctx.ac.module;
6959 }
6960
6961 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
6962 {
6963 unsigned *retval = (unsigned *)context;
6964 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
6965 char *description = LLVMGetDiagInfoDescription(di);
6966
6967 if (severity == LLVMDSError) {
6968 *retval = 1;
6969 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
6970 description);
6971 }
6972
6973 LLVMDisposeMessage(description);
6974 }
6975
6976 static unsigned ac_llvm_compile(LLVMModuleRef M,
6977 struct ac_shader_binary *binary,
6978 LLVMTargetMachineRef tm)
6979 {
6980 unsigned retval = 0;
6981 char *err;
6982 LLVMContextRef llvm_ctx;
6983 LLVMMemoryBufferRef out_buffer;
6984 unsigned buffer_size;
6985 const char *buffer_data;
6986 LLVMBool mem_err;
6987
6988 /* Setup Diagnostic Handler*/
6989 llvm_ctx = LLVMGetModuleContext(M);
6990
6991 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
6992 &retval);
6993
6994 /* Compile IR*/
6995 mem_err = LLVMTargetMachineEmitToMemoryBuffer(tm, M, LLVMObjectFile,
6996 &err, &out_buffer);
6997
6998 /* Process Errors/Warnings */
6999 if (mem_err) {
7000 fprintf(stderr, "%s: %s", __FUNCTION__, err);
7001 free(err);
7002 retval = 1;
7003 goto out;
7004 }
7005
7006 /* Extract Shader Code*/
7007 buffer_size = LLVMGetBufferSize(out_buffer);
7008 buffer_data = LLVMGetBufferStart(out_buffer);
7009
7010 ac_elf_read(buffer_data, buffer_size, binary);
7011
7012 /* Clean up */
7013 LLVMDisposeMemoryBuffer(out_buffer);
7014
7015 out:
7016 return retval;
7017 }
7018
7019 static void ac_compile_llvm_module(LLVMTargetMachineRef tm,
7020 LLVMModuleRef llvm_module,
7021 struct ac_shader_binary *binary,
7022 struct ac_shader_config *config,
7023 struct ac_shader_variant_info *shader_info,
7024 gl_shader_stage stage,
7025 bool dump_shader, bool supports_spill)
7026 {
7027 if (dump_shader)
7028 ac_dump_module(llvm_module);
7029
7030 memset(binary, 0, sizeof(*binary));
7031 int v = ac_llvm_compile(llvm_module, binary, tm);
7032 if (v) {
7033 fprintf(stderr, "compile failed\n");
7034 }
7035
7036 if (dump_shader)
7037 fprintf(stderr, "disasm:\n%s\n", binary->disasm_string);
7038
7039 ac_shader_binary_read_config(binary, config, 0, supports_spill);
7040
7041 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
7042 LLVMDisposeModule(llvm_module);
7043 LLVMContextDispose(ctx);
7044
7045 if (stage == MESA_SHADER_FRAGMENT) {
7046 shader_info->num_input_vgprs = 0;
7047 if (G_0286CC_PERSP_SAMPLE_ENA(config->spi_ps_input_addr))
7048 shader_info->num_input_vgprs += 2;
7049 if (G_0286CC_PERSP_CENTER_ENA(config->spi_ps_input_addr))
7050 shader_info->num_input_vgprs += 2;
7051 if (G_0286CC_PERSP_CENTROID_ENA(config->spi_ps_input_addr))
7052 shader_info->num_input_vgprs += 2;
7053 if (G_0286CC_PERSP_PULL_MODEL_ENA(config->spi_ps_input_addr))
7054 shader_info->num_input_vgprs += 3;
7055 if (G_0286CC_LINEAR_SAMPLE_ENA(config->spi_ps_input_addr))
7056 shader_info->num_input_vgprs += 2;
7057 if (G_0286CC_LINEAR_CENTER_ENA(config->spi_ps_input_addr))
7058 shader_info->num_input_vgprs += 2;
7059 if (G_0286CC_LINEAR_CENTROID_ENA(config->spi_ps_input_addr))
7060 shader_info->num_input_vgprs += 2;
7061 if (G_0286CC_LINE_STIPPLE_TEX_ENA(config->spi_ps_input_addr))
7062 shader_info->num_input_vgprs += 1;
7063 if (G_0286CC_POS_X_FLOAT_ENA(config->spi_ps_input_addr))
7064 shader_info->num_input_vgprs += 1;
7065 if (G_0286CC_POS_Y_FLOAT_ENA(config->spi_ps_input_addr))
7066 shader_info->num_input_vgprs += 1;
7067 if (G_0286CC_POS_Z_FLOAT_ENA(config->spi_ps_input_addr))
7068 shader_info->num_input_vgprs += 1;
7069 if (G_0286CC_POS_W_FLOAT_ENA(config->spi_ps_input_addr))
7070 shader_info->num_input_vgprs += 1;
7071 if (G_0286CC_FRONT_FACE_ENA(config->spi_ps_input_addr))
7072 shader_info->num_input_vgprs += 1;
7073 if (G_0286CC_ANCILLARY_ENA(config->spi_ps_input_addr))
7074 shader_info->num_input_vgprs += 1;
7075 if (G_0286CC_SAMPLE_COVERAGE_ENA(config->spi_ps_input_addr))
7076 shader_info->num_input_vgprs += 1;
7077 if (G_0286CC_POS_FIXED_PT_ENA(config->spi_ps_input_addr))
7078 shader_info->num_input_vgprs += 1;
7079 }
7080 config->num_vgprs = MAX2(config->num_vgprs, shader_info->num_input_vgprs);
7081
7082 /* +3 for scratch wave offset and VCC */
7083 config->num_sgprs = MAX2(config->num_sgprs,
7084 shader_info->num_input_sgprs + 3);
7085
7086 /* Enable 64-bit and 16-bit denormals, because there is no performance
7087 * cost.
7088 *
7089 * If denormals are enabled, all floating-point output modifiers are
7090 * ignored.
7091 *
7092 * Don't enable denormals for 32-bit floats, because:
7093 * - Floating-point output modifiers would be ignored by the hw.
7094 * - Some opcodes don't support denormals, such as v_mad_f32. We would
7095 * have to stop using those.
7096 * - SI & CI would be very slow.
7097 */
7098 config->float_mode |= V_00B028_FP_64_DENORMS;
7099 }
7100
7101 static void
7102 ac_fill_shader_info(struct ac_shader_variant_info *shader_info, struct nir_shader *nir, const struct ac_nir_compiler_options *options)
7103 {
7104 switch (nir->info.stage) {
7105 case MESA_SHADER_COMPUTE:
7106 for (int i = 0; i < 3; ++i)
7107 shader_info->cs.block_size[i] = nir->info.cs.local_size[i];
7108 break;
7109 case MESA_SHADER_FRAGMENT:
7110 shader_info->fs.early_fragment_test = nir->info.fs.early_fragment_tests;
7111 break;
7112 case MESA_SHADER_GEOMETRY:
7113 shader_info->gs.vertices_in = nir->info.gs.vertices_in;
7114 shader_info->gs.vertices_out = nir->info.gs.vertices_out;
7115 shader_info->gs.output_prim = nir->info.gs.output_primitive;
7116 shader_info->gs.invocations = nir->info.gs.invocations;
7117 break;
7118 case MESA_SHADER_TESS_EVAL:
7119 shader_info->tes.primitive_mode = nir->info.tess.primitive_mode;
7120 shader_info->tes.spacing = nir->info.tess.spacing;
7121 shader_info->tes.ccw = nir->info.tess.ccw;
7122 shader_info->tes.point_mode = nir->info.tess.point_mode;
7123 shader_info->tes.as_es = options->key.tes.as_es;
7124 break;
7125 case MESA_SHADER_TESS_CTRL:
7126 shader_info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out;
7127 break;
7128 case MESA_SHADER_VERTEX:
7129 shader_info->vs.as_es = options->key.vs.as_es;
7130 shader_info->vs.as_ls = options->key.vs.as_ls;
7131 /* in LS mode we need at least 1, invocation id needs 2, handled elsewhere */
7132 if (options->key.vs.as_ls)
7133 shader_info->vs.vgpr_comp_cnt = MAX2(1, shader_info->vs.vgpr_comp_cnt);
7134 break;
7135 default:
7136 break;
7137 }
7138 }
7139
7140 void ac_compile_nir_shader(LLVMTargetMachineRef tm,
7141 struct ac_shader_binary *binary,
7142 struct ac_shader_config *config,
7143 struct ac_shader_variant_info *shader_info,
7144 struct nir_shader *const *nir,
7145 int nir_count,
7146 const struct ac_nir_compiler_options *options,
7147 bool dump_shader)
7148 {
7149
7150 LLVMModuleRef llvm_module = ac_translate_nir_to_llvm(tm, nir, nir_count, shader_info,
7151 options);
7152
7153 ac_compile_llvm_module(tm, llvm_module, binary, config, shader_info, nir[0]->info.stage, dump_shader, options->supports_spill);
7154 for (int i = 0; i < nir_count; ++i)
7155 ac_fill_shader_info(shader_info, nir[i], options);
7156
7157 /* Determine the ES type (VS or TES) for the GS on GFX9. */
7158 if (options->chip_class == GFX9) {
7159 if (nir_count == 2 &&
7160 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
7161 shader_info->gs.es_type = nir[0]->info.stage;
7162 }
7163 }
7164 }
7165
7166 static void
7167 ac_gs_copy_shader_emit(struct nir_to_llvm_context *ctx)
7168 {
7169 LLVMValueRef vtx_offset =
7170 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
7171 LLVMConstInt(ctx->ac.i32, 4, false), "");
7172 int idx = 0;
7173
7174 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
7175 int length = 4;
7176 int slot = idx;
7177 int slot_inc = 1;
7178 if (!(ctx->output_mask & (1ull << i)))
7179 continue;
7180
7181 if (i == VARYING_SLOT_CLIP_DIST0) {
7182 /* unpack clip and cull from a single set of slots */
7183 length = ctx->num_output_clips + ctx->num_output_culls;
7184 if (length > 4)
7185 slot_inc = 2;
7186 }
7187
7188 for (unsigned j = 0; j < length; j++) {
7189 LLVMValueRef value, soffset;
7190
7191 soffset = LLVMConstInt(ctx->ac.i32,
7192 (slot * 4 + j) *
7193 ctx->gs_max_out_vertices * 16 * 4, false);
7194
7195 value = ac_build_buffer_load(&ctx->ac, ctx->gsvs_ring,
7196 1, ctx->ac.i32_0,
7197 vtx_offset, soffset,
7198 0, 1, 1, true, false);
7199
7200 LLVMBuildStore(ctx->ac.builder,
7201 ac_to_float(&ctx->ac, value), ctx->abi.outputs[radeon_llvm_reg_index_soa(i, j)]);
7202 }
7203 idx += slot_inc;
7204 }
7205 handle_vs_outputs_post(ctx, false, &ctx->shader_info->vs.outinfo);
7206 }
7207
7208 void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
7209 struct nir_shader *geom_shader,
7210 struct ac_shader_binary *binary,
7211 struct ac_shader_config *config,
7212 struct ac_shader_variant_info *shader_info,
7213 const struct ac_nir_compiler_options *options,
7214 bool dump_shader)
7215 {
7216 struct nir_to_llvm_context ctx = {0};
7217 ctx.context = LLVMContextCreate();
7218 ctx.options = options;
7219 ctx.shader_info = shader_info;
7220
7221 ac_llvm_context_init(&ctx.ac, ctx.context, options->chip_class,
7222 options->family);
7223 ctx.ac.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
7224
7225 ctx.is_gs_copy_shader = true;
7226 LLVMSetTarget(ctx.ac.module, "amdgcn--");
7227
7228 enum ac_float_mode float_mode =
7229 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
7230 AC_FLOAT_MODE_DEFAULT;
7231
7232 ctx.ac.builder = ac_create_builder(ctx.context, float_mode);
7233 ctx.stage = MESA_SHADER_VERTEX;
7234
7235 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
7236
7237 ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out;
7238 ac_setup_rings(&ctx);
7239
7240 ctx.num_output_clips = geom_shader->info.clip_distance_array_size;
7241 ctx.num_output_culls = geom_shader->info.cull_distance_array_size;
7242
7243 struct ac_nir_context nir_ctx = {};
7244 nir_ctx.ac = ctx.ac;
7245 nir_ctx.abi = &ctx.abi;
7246
7247 nir_foreach_variable(variable, &geom_shader->outputs) {
7248 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
7249 handle_shader_output_decl(&nir_ctx, geom_shader, variable);
7250 }
7251
7252 ac_gs_copy_shader_emit(&ctx);
7253
7254 LLVMBuildRetVoid(ctx.ac.builder);
7255
7256 ac_llvm_finalize_module(&ctx);
7257
7258 ac_compile_llvm_module(tm, ctx.ac.module, binary, config, shader_info,
7259 MESA_SHADER_VERTEX,
7260 dump_shader, options->supports_spill);
7261 }